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GB1025453A - Improvements in or relating to semiconductor devices - Google Patents

Improvements in or relating to semiconductor devices

Info

Publication number
GB1025453A
GB1025453A GB378364A GB378364A GB1025453A GB 1025453 A GB1025453 A GB 1025453A GB 378364 A GB378364 A GB 378364A GB 378364 A GB378364 A GB 378364A GB 1025453 A GB1025453 A GB 1025453A
Authority
GB
United Kingdom
Prior art keywords
gold
slice
alloy
layer
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB378364A
Inventor
Jack Rowland Peters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB378364A priority Critical patent/GB1025453A/en
Priority to DEST23249A priority patent/DE1276826B/en
Publication of GB1025453A publication Critical patent/GB1025453A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

1,025,453. Semi-conductor devices &c. STANDARD TELEPHONES & CABLES Ltd. Jan. 29, 1964, No. 3783/64. Heading H1K. To mount a semi-conductor wafer a layer of an alloy containing gold and the semi-conductor is formed on one of the faces of the wafer and a mixture containing gold and a conductivity type determining impurity is added to the surface of this layer. The wafer is then placed with its prepared face in contact with a mount and heated in a neutral or reducing atmosphere so that on subsequent cooling the wafer becomes firmly attached to the mount. In an embodiment planar transistor structures are formed in an N-type silicon slice by diffusion into one face. The other face is lapped and the slice washed and dried. The slice is heated to 400‹ C. and gold containing a small amount of antimony evaporated on to form a layer of molten alloy with the silicon. This layer is solidified by cooling the slice to below 200‹ C. and a further amount of gold/antimony alloy deposited at this reduced temperature. Next the slice is separated into individual wafers each of which is placed with its alloy layer in contact with a gold-plated header. The assemblies are passed through a furnace at 450‹ C. (in a nitrogen or nitrogen/hydrogen atmosphere) when the gold/antimony acts as a brazing metal to join the wafers to the headers. Each device is provided with leads and encapsulated. In variants the temperature of the slice may be progressively reduced during the alloying operation and the alloy deposited in other than two stages. Arsenic may replace antimony in the doping impurity and boron may instead be used if the original slice is of P-type conductivity. Instead of doped gold a doped gold/ silicon alloy may be deposited during the process. The header may be nickel-plated or may be unplated iron/cobalt/nickel alloy. Germanium or intermetallic compounds may replace the silicon as semi-conductor. Devices other than transistors may be similarly mounted.
GB378364A 1964-01-29 1964-01-29 Improvements in or relating to semiconductor devices Expired GB1025453A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB378364A GB1025453A (en) 1964-01-29 1964-01-29 Improvements in or relating to semiconductor devices
DEST23249A DE1276826B (en) 1964-01-29 1965-01-23 Method for manufacturing semiconductor components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB378364A GB1025453A (en) 1964-01-29 1964-01-29 Improvements in or relating to semiconductor devices

Publications (1)

Publication Number Publication Date
GB1025453A true GB1025453A (en) 1966-04-06

Family

ID=9764835

Family Applications (1)

Application Number Title Priority Date Filing Date
GB378364A Expired GB1025453A (en) 1964-01-29 1964-01-29 Improvements in or relating to semiconductor devices

Country Status (2)

Country Link
DE (1) DE1276826B (en)
GB (1) GB1025453A (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2695852A (en) * 1952-02-15 1954-11-30 Bell Telephone Labor Inc Fabrication of semiconductors for signal translating devices
BE575275A (en) * 1958-02-03 1900-01-01
NL242265A (en) * 1958-09-30 1900-01-01
NL251527A (en) * 1959-05-12
DE1133834B (en) * 1960-09-21 1962-07-26 Siemens Ag Silicon rectifier and process for its manufacture
FR1335554A (en) * 1961-07-03 1963-08-23 Ass Elect Ind Improvements to mesa transistors

Also Published As

Publication number Publication date
DE1276826B (en) 1968-09-05

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