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GB1003489A - Binary information stores - Google Patents

Binary information stores

Info

Publication number
GB1003489A
GB1003489A GB1811863A GB1811863A GB1003489A GB 1003489 A GB1003489 A GB 1003489A GB 1811863 A GB1811863 A GB 1811863A GB 1811863 A GB1811863 A GB 1811863A GB 1003489 A GB1003489 A GB 1003489A
Authority
GB
United Kingdom
Prior art keywords
lines
reflected
pulse
pulses
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1811863A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1003489A publication Critical patent/GB1003489A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02Comparing digital values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1,003,489. Circuits embodying bi-stable magnetic elements. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 8, 1963 [May 9, 1962; Jan. 18, 1963], No. 18118/63. Heading H3B. In order to eliminate the effects in a memory of reflected pulses produced at the various connections by the drive pulses the word lines and their associated distribution busses are extended by suitable lengths such that the reflected pulses are sufficiently delayed so as not to interfere with the primary drive pulses. The memory of a first embodiment, Figs. 1, 2, comprises four plates 10, 20, 30, 40 each provided with twenty thin film memory cells and vertical word lines, e.g. 12, 13, 14, 15 connected each through a diode 12a, 13a, 14a, 15a to a distribution bus, 16 in the case of the drive wires of plate 10, which busbars are fed from drive pulse generators 17, 27, 37, 47. The lower ends of the word lines are connected to collector lines 61, 62, 63 and 60 in such a manner that only one word line (25, 35, 45, 15) associated with each distribution bus is connected to a particular collector line and also connected through switches 60a, 61a, 62a, 63a to ground. By selecting one of the switches to be closed a drive pulse from one of the generators passes through only one of the word lines so that as the magnetization vectors of the appropriate cells change from the easy direction to the hard direction negative or positive pulses will be induced in read lines 70a to 70e depending on the information in the cells. Write lines, not shown, are arranged parallel with and above the read lines. The drive pulses supplied by pulse generators 17, 27, 37, 47 are divided and reflected at the unavoidable connection points in the circuitry. Fig. 2 shows one of the distribution busses 16 and its associated word lines so that if diode 14a is conductive the current from the generator 17 is divided part I 1 passing through line 14, part I 2 continuing along the bus-bar 16 and part I 3 being reflected and returning to the pulse generator. Since an ideal termination at both ends of the busses with their characteristic resistance cannot be achieved and often is undesirable I 2 is at least partially reflected at the right hand end of the distribution bus and returns as I 2 <SP>1</SP> and I 3 is partially reflected and returns as I 3 <SP>1</SP>. At the point of connection the original drive pulse and reflected portions delayed by their proportionate times combine into a three-step drive pulse and this pulse will be dependent upon the position of the word line along the bus-bar so that the drive pulse will have different values for each word line. In accordance with the invention a length of line 16a having the same characteristic impedance as the distribution bus is inserted as shown and an equal length of line 16b terminated by resistor R corresponding to the characteristic resistance of the bus. The lengths of the lines are such that when the reflections arrive at the word line the primary drive pulses will have reached their maximum values and rotated the magnetization vectors of the cells. By reversing the polarities of the reflected pulses with respect to the driving pulse the reflected pulses may be employed to turn off the word pulse prior to the fading of the primary drive pulse. In the case of the portion I 2 <SP>1</SP> of the reflected pulse this is achieved by undermatching the termination of the distribution bus. The word lines may be extended between the memory matrix and the collector lines 60, 61, 62, 63 by a suitable length L so as to eliminate the adverse effects of drive pulses reflected from the collector lines and extending the lines also eliminates spurious outputs appearing due to non-selected cells having their magnetization vectors deflected because of the collector lines not being completely short-circuited to ground. In the magnetic film memory of Fig. 3 in which access to a word line 11, 21, 31, 41 is via switches 51 to 56 the pulses passing to and fro in the word lines are delayed by means of a suitable pulse delaying element 86 consisting of a portion of conductor line placed between each word line and the point of connection with ground potential. For absorbing reflected pulses diode 84 is connected as shown. Address register 58 in conjunction with conductors 64 to 67 and transistors 51 to 56 selects which one of the word lines is to be energized by the pulses from source 57. Read lines 71 to 78 connected to amplifier 79 and a regenerative loop 90 pick up signals due to the moving of the magnetization vectors of the cells from their easy position to their hard position. Since the stored information is destroyed by the read-out process the information just read out must be delivered back after a suitable delay. This may be achieved by either making use of the write lines 91 to 98 and the regenerated loop 90 or by utilizing the reflected drive pulse. Since the drive pulse passing through delay means such as the conductor extension 86 is reflected by the short-circuit and returns with reversed polarity to the same word line with a suitable delay the information is written back into the memory. The returning pulse is attenuated by shunt means comprising diode 84.
GB1811863A 1962-05-09 1963-05-08 Binary information stores Expired GB1003489A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH556962A CH407230A (en) 1962-05-09 1962-05-09 Magnetic layer storage
CH62463A CH434368A (en) 1962-05-09 1963-01-18 Magnetic layer storage

Publications (1)

Publication Number Publication Date
GB1003489A true GB1003489A (en) 1965-09-02

Family

ID=25685150

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1811863A Expired GB1003489A (en) 1962-05-09 1963-05-08 Binary information stores

Country Status (6)

Country Link
BE (1) BE632133A (en)
CH (2) CH407230A (en)
DE (2) DE1293858B (en)
GB (1) GB1003489A (en)
NL (1) NL292344A (en)
SE (1) SE324590B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781858B2 (en) 2002-04-02 2004-08-24 Hewlett-Packard Development Company, L.P. Cubic memory array
WO2004100267A1 (en) * 2003-04-03 2004-11-18 Hewlett-Packard Development Company, L.P. Cubic memory array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781858B2 (en) 2002-04-02 2004-08-24 Hewlett-Packard Development Company, L.P. Cubic memory array
WO2004100267A1 (en) * 2003-04-03 2004-11-18 Hewlett-Packard Development Company, L.P. Cubic memory array

Also Published As

Publication number Publication date
BE632133A (en)
CH407230A (en) 1966-02-15
DE1248725B (en) 1967-08-31
CH434368A (en) 1967-04-30
DE1293858B (en) 1969-04-30
SE324590B (en) 1970-06-08
NL292344A (en)

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