GB0616909D0 - Field programmable gate arrays - Google Patents

Field programmable gate arrays

Info

Publication number: GB0616909D0
Authority: GB; United Kingdom
Prior art keywords: programmable gate; field programmable; gate arrays; arrays; field
Prior art date: 2006-08-25
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Ceased

Application number

GBGB0616909.8A

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Ip2ipo Innovations Ltd

Original Assignee

Imperial Innovations Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2006-08-25

Filing date

2006-08-25

Publication date

2006-10-04

2006-08-25 Application filed by Imperial Innovations Ltd filed Critical Imperial Innovations Ltd

2006-08-25 Priority to GBGB0616909.8A priority Critical patent/GB0616909D0/en

2006-10-04 Publication of GB0616909D0 publication Critical patent/GB0616909D0/en

2007-08-17 Priority to PCT/GB2007/003152 priority patent/WO2008023152A1/en

Status Ceased legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Landscapes

Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Theoretical Computer Science (AREA)
Evolutionary Computation (AREA)
Geometry (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Design And Manufacture Of Integrated Circuits (AREA)
Logic Circuits (AREA)

GBGB0616909.8A 2006-08-25 2006-08-25 Field programmable gate arrays Ceased GB0616909D0 (en)

Priority Applications (2)

Application Number	Priority Date	Filing Date	Title
GBGB0616909.8A GB0616909D0 (en)	2006-08-25	2006-08-25	Field programmable gate arrays
PCT/GB2007/003152 WO2008023152A1 (en)	2006-08-25	2007-08-17	Logic circuit

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
GBGB0616909.8A GB0616909D0 (en)	2006-08-25	2006-08-25	Field programmable gate arrays

Publications (1)

Publication Number	Publication Date
GB0616909D0 true GB0616909D0 (en)	2006-10-04

Family

ID=37102859

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
GBGB0616909.8A Ceased GB0616909D0 (en)	2006-08-25	2006-08-25	Field programmable gate arrays

Country Status (2)

Country	Link
GB (1)	GB0616909D0 (en)
WO (1)	WO2008023152A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
GB0724177D0 (en)	2007-12-11	2008-01-23	Imp Innovations Ltd	A method of measuring delay in an integrated circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
GB2297409B (en) *	1995-01-27	1998-08-19	Altera Corp	Programmable logic devices
US6134703A (en) *	1997-12-23	2000-10-17	Lattice Semiconductor Corporation	Process for programming PLDs and embedded non-volatile memories
US6167558A (en) *	1998-02-20	2000-12-26	Xilinx, Inc.	Method for tolerating defective logic blocks in programmable logic devices
US6999952B1 (en) *	2001-04-18	2006-02-14	Cisco Technology, Inc.	Linear associative memory-based hardware architecture for fault tolerant ASIC/FPGA work-around

2006
- 2006-08-25 GB GBGB0616909.8A patent/GB0616909D0/en not_active Ceased
2007
- 2007-08-17 WO PCT/GB2007/003152 patent/WO2008023152A1/en active Application Filing

Also Published As

Publication number	Publication date
WO2008023152A1 (en)	2008-02-28

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Legal Events

Date	Code	Title	Description
2008-02-20	AT	Applications terminated before publication under section 16(1)