GB0105609D0 - Configuration of features of a digital processing device - Google Patents

Configuration of features of a digital processing device

Info

Publication number: GB0105609D0
Authority: GB; United Kingdom
Prior art keywords: features; configuration; processing device; digital processing; digital
Prior art date: 2001-03-07
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Ceased

Application number

GBGB0105609.2A

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Technologies UK Ltd

Original Assignee

NEC Technologies UK Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2001-03-07

Filing date

2001-03-07

Publication date

2001-04-25

2001-03-07 Application filed by NEC Technologies UK Ltd filed Critical NEC Technologies UK Ltd

2001-03-07 Priority to GBGB0105609.2A priority Critical patent/GB0105609D0/en

2001-04-02 Priority to GB0108194A priority patent/GB2373350B/en

2001-04-25 Publication of GB0105609D0 publication Critical patent/GB0105609D0/en

Status Ceased legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Landscapes

Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Theoretical Computer Science (AREA)
Evolutionary Computation (AREA)
Geometry (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Information Transfer Systems (AREA)

GBGB0105609.2A 2001-03-07 2001-03-07 Configuration of features of a digital processing device Ceased GB0105609D0 (en)

Priority Applications (2)

Application Number	Priority Date	Filing Date	Title
GBGB0105609.2A GB0105609D0 (en)	2001-03-07	2001-03-07	Configuration of features of a digital processing device
GB0108194A GB2373350B (en)	2001-03-07	2001-04-02	Configuration of features of a digital processing device

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
GBGB0105609.2A GB0105609D0 (en)	2001-03-07	2001-03-07	Configuration of features of a digital processing device

Publications (1)

Publication Number	Publication Date
GB0105609D0 true GB0105609D0 (en)	2001-04-25

Family

ID=9910151

Family Applications (2)

Application Number	Title	Priority Date	Filing Date
GBGB0105609.2A Ceased GB0105609D0 (en)	2001-03-07	2001-03-07	Configuration of features of a digital processing device
GB0108194A Expired - Fee Related GB2373350B (en)	2001-03-07	2001-04-02	Configuration of features of a digital processing device

Family Applications After (1)

Application Number	Title	Priority Date	Filing Date
GB0108194A Expired - Fee Related GB2373350B (en)	2001-03-07	2001-04-02	Configuration of features of a digital processing device

Country Status (1)

Country	Link
GB (2)	GB0105609D0 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4975831A (en) *	1988-05-09	1990-12-04	Intel Corporation	High-availability computer system with a predefinable configuration of the modules
US5230058A (en) *	1989-12-05	1993-07-20	Zilog, Inc.	IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors
US5590305A (en) *	1994-03-28	1996-12-31	Altera Corporation	Programming circuits and techniques for programming logic
US5727207A (en) *	1994-09-07	1998-03-10	Adaptec, Inc.	Method and apparatus for automatically loading configuration data on reset into a host adapter integrated circuit
US5909557A (en) *	1995-11-20	1999-06-01	Lucent Technologies Inc.	Integrated circuit with programmable bus configuration

2001
- 2001-03-07 GB GBGB0105609.2A patent/GB0105609D0/en not_active Ceased
- 2001-04-02 GB GB0108194A patent/GB2373350B/en not_active Expired - Fee Related

Also Published As

Publication number	Publication date
GB0108194D0 (en)	2001-05-23
GB2373350A (en)	2002-09-18
GB2373350B (en)	2004-03-17

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Legal Events

Date	Code	Title	Description
2002-10-09	AT	Applications terminated before publication under section 16(1)