FR3139933A1 - Phase change memory cell - Google Patents

Abstract

Phase change memory cell The present description relates to a phase change memory cell (301) comprising: – a first layer of a phase change material (215); – a heating element (209) located under the first layer (215); – a second insulating layer (203) covering one side of the heating element (209); and – a first stack comprising a third encapsulation layer (303) covering the side faces of the second layer (203) and a fourth encapsulation layer (305) covering the third layer (303) and being made of a material having a density lower than that of the material of the third layer (303). Figure for abstract: Fig. 3A

Description

Phase change memory cell

This description relates generally to electronic devices, and more particularly to memory devices comprising memory cells based on a phase change material, also called phase change memory cells.

In a phase-change memory cell, the phase-change material is capable of alternating, under the effect of heat, between a crystalline phase, electrically conductive, and an amorphous phase, electrically insulating. The crystalline and amorphous phases of the phase-change material of a memory cell make it possible to define, for this cell, two memory states corresponding for example respectively to the logic values 1 and 0. The heat necessary for the phase change is generally produced by the Joule effect, for example by means of a heating element located near the phase-change material and traversed by an electric current resulting from a voltage pulse applied between conduction terminals of the heating element.

In order to obtain phase change memory cells with increased energy efficiency, it would be desirable to optimize the thermal performance of current phase change memory cells, so that the electrical energy required to heat the phase change material is as low as possible. Advantageously, this would allow memory devices incorporating such cells to have lower energy consumption than current phase change memory devices.

One embodiment overcomes all or part of the drawbacks of known phase change material memory cells and known memory devices incorporating such cells.

For this, one embodiment provides a phase change memory cell comprising:
– a first layer in a phase change material;
– a heating element located under the first layer;
– a second insulating layer covering one side of the heating element; and
– a third insulating layer interposed between the first and second layers, made of a material having a density greater than that of the material of the second layer.

According to one embodiment, the second layer is made of silicon carbide or silicon carbonitride.

According to one embodiment, the third layer is silicon carbide, silicon nitride, silicon carbonitride, germanium nitride, carbon nitride or carbon.

According to one embodiment, the third layer is made of the same material as the second layer.

According to one embodiment, the second and third layers are made of silicon carbide.

According to one embodiment, the second and third layers are made of silicon nitride.

According to one embodiment, the cell further comprises a first conduction electrode located under and in contact with a face of the heating element opposite the first layer and a second conduction electrode located on and in contact with a face of the first layer opposite the heating element.

According to one embodiment, the heating element has an L shape.

According to one embodiment, the cell further comprises a stack comprising a fourth encapsulation layer covering the lateral faces of the first, second and third layers and a fifth encapsulation layer covering the fourth layer and having a density lower than that of the fourth layer.

According to one embodiment, the cell further comprises a sixth encapsulation layer coating the fifth layer and having a density greater than that of the fifth layer.

One embodiment provides a method of manufacturing a phase change memory cell comprising the following successive steps:
a) depositing, on a substrate, a first insulating layer and a second insulating layer coating the first insulating layer, the second insulating layer being made of a material having a density greater than that of the material of the second insulating layer;
(b) forming, in a trench passing through the first and second insulating layers, a heating element, one side of which is coated with the first and second insulating layers; and
c) depositing, on the side of the second insulating layer, a third layer of a phase change material.

According to one embodiment, the method further comprises, between steps b) and c), successive steps of depositing a fourth encapsulation layer coating the lateral faces of the first, second and third layers and a fifth encapsulation layer coating the fourth layer and having a density lower than that of the fourth layer.

According to one embodiment, the method further comprises, after the deposition of the fifth layer and before the deposition of the third layer, a step of deposition of a sixth encapsulation layer coating the fifth layer and having a density greater than that of the fifth layer.

Furthermore, one embodiment provides a phase change memory cell comprising:
– a first layer in a phase change material;
– a heating element located under the first layer;
– a second insulating layer covering one side of the heating element; and
– a first stack comprising a third encapsulation layer coating the side faces of the second layer and a fourth encapsulation layer coating the third layer and being made of a material having a density lower than that of the material of the third layer.

According to one embodiment, the fourth layer is coated with a second stack comprising an alternation of encapsulation layers having densities substantially equal to those of the third and fourth layers.

According to one embodiment, the fourth layer is coated with a second stack comprising successive encapsulation layers having decreasing densities, lower than those of the fourth layer.

According to one embodiment, the successive encapsulation layers of the second stack are made of the same material.

According to one embodiment, the cell further comprises a sixth encapsulation layer, coating the fourth layer or the second stack, the sixth layer having a density greater than that of the fourth layer.

According to one embodiment, the cell further comprises a first conduction electrode located under and in contact with a face of the heating element opposite the first layer and a second conduction electrode located on and in contact with a face of the first layer opposite the heating element.

According to one embodiment, the cell further comprises a third stack comprising a seventh encapsulation layer coating the lateral faces of the first layer and the second conduction electrode and an eighth encapsulation layer coating the seventh layer and having a density lower than that of the seventh layer.

According to one embodiment, the cell further comprises a ninth layer interposed between the first and second layers and having a density greater than that of the second layer, the second layer being made of silicon carbide or silicon carbonitride.

According to one embodiment, the ninth layer is made of silicon carbide, silicon nitride or silicon carbonitride and has a density greater than that of the second layer.

According to one embodiment, the ninth layer is made of germanium nitride, carbon nitride or carbon.

One embodiment provides a method of manufacturing a phase change memory cell comprising the following successive steps:
a) depositing, on a substrate, at least a first thermally insulating layer;
b) forming, in a trench passing through said at least one first layer, a heating element, one side of which is coated with said at least one first layer; and
c) forming a first stack comprising a second encapsulation layer coating the lateral faces of said at least one first layer and a third encapsulation layer coating the second layer, the third layer being made of a material having a density lower than that of the material of the second layer.

According to one embodiment, the method further comprises, after step c), a step d) of depositing a fourth encapsulation layer coating the third layer and having a density greater than that of the third layer.

These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in connection with the attached figures, among which:

THE And are sectional views illustrating, schematically and partially, an example of a memory device comprising memory cells based on a phase change material;

THE , , , , , , , And are sectional views illustrating, schematically and partially, a method of manufacturing a memory device comprising memory cells based on a phase change material according to one embodiment; and

THE And are sectional views illustrating, schematically and partially, a memory device comprising memory cells based on a phase change material according to one embodiment.

The same elements have been designated by the same references in the different figures. In particular, the structural and/or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the elements and circuits for controlling the phase-change memory cells of the memory devices described, which may in particular include electrical selection and connection elements, are not detailed, the embodiments described being compatible with the elements and circuits for controlling conventional phase-change memory cells.

Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

Unless otherwise specified, the expressions “approximately”, “approximately”, “substantially”, and “of the order of” mean to within 10%, preferably to within 5%.

THE And are sectional views, respectively according to plane AA of the and according to the BB plan of the , illustrating, schematically and partially, an example of a memory device 100 comprising memory cells 101 based on a phase change material, or phase change memory cells 101. The plane AA of the is substantially orthogonal to the plane BB of the .

For example, the memory device 100 is a non-volatile memory, for example an EEPROM (Electrically Erasable Programmable Read-Only Memory). The programming of each memory cell 101 of the memory device 100 is for example carried out at the end of the manufacture of the device 100 and can then be modified several times during its use.

In the example shown, the memory cells 101 are formed in and on a substrate 103, for example a wafer or a piece of wafer made of a semiconductor material, for example silicon.

In the illustrated example, each memory cell 101 comprises a contact recovery element 105, for example a conductive via, formed in the substrate 103. The contact recovery element 105 extends in the thickness of the substrate 103 from a face 103T of the substrate 103 (the upper face of the substrate 103, in the orientation of FIGS. 1A and 1B). As an example, the contact recovery element 105 is made of an electrically conductive material, for example a metal, for example copper (Cu) or tungsten (W), or a metal alloy, for example titanium nitride (TiN) or tantalum nitride (TaN).

In the example shown, each memory cell 101 further comprises a resistive heating element 107 located on and in contact with the contact recovery element 105 of the cell. In this example, the heating element 107 has a general L shape comprising a horizontal portion, extending laterally on and in contact with the upper face of the underlying contact recovery element 105, and a vertical portion, extending from one end of the horizontal portion along a direction substantially orthogonal to the face 103T of the substrate 103. The heating element 107 is made of an electrically conductive material. For example, the heating element is made of a metal or a metal alloy.

In the illustrated example, the heating element 107 of each cell 101 is interposed laterally between two electrically and thermally insulating regions 109. More precisely, in this example, the insulating regions 109 cover all the lateral faces of the heating element 107 parallel to the plane BB of the as well as the face of the horizontal portion of the heating element 107 opposite the face 103T of the substrate 103. In the orientation of FIGS. 1A and 1B, the upper faces of the insulating regions 109 are flush with the upper face of the vertical portion of the heating element 107. For example, the insulating region 109 is made of silicon nitride (SiN).

In the example shown, each memory cell 101 further comprises a region made of a phase change material 111. In the orientation of FIGS. 1A and 1B, the region made of phase change material 111 covers the upper faces of the insulating regions 109 and of the vertical portion of the heating element 107 of the cell. As an example, the region 111 is made of a so-called “chalcogenide” material, i.e. a material or an alloy comprising at least one chalcogen element, for example a material from the germanium telluride (GeTe) or germanium-antimony-tellurium (GeSbTe, also referred to by the acronym “GST”) family.

In the example illustrated in FIGS. 1A and 1B, the upper face of the phase change material region 111, in other words the face of the region 111 opposite the substrate 103, is coated with an electrically conductive region 113. As an example, the electrically conductive region 113 is made of a metal or a metal alloy, for example titanium nitride (TiN).

Although not illustrated in FIGS. 1A and 1B, the electrically conductive region 113 may be coated, on the side of its face opposite the phase change material region 111, with a dielectric region intended to confine the heat inside the cell 101.

In the example shown, each cell 101 further comprises an encapsulation layer 115 covering the sides of the stack formed by the insulating regions 109, the phase-change material region 111 and the electrically conductive region 113. The encapsulation layer 115 more precisely covers the lateral faces of the insulating regions 109, the lateral faces of the phase-change material region 111, and the lateral faces and the upper face of the conductive region 113. In the example shown, the encapsulation layer 115 further covers the lateral faces of the heating element 107 parallel to the plane of the , not coated by the insulating regions 109. The encapsulation layer 115 can also, as in the example illustrated in FIGS. 1A and 1B, extend between the memory cells 101. More precisely, in this example, the encapsulation layer 115 coats parts of the face 103T of the substrate 103 which are not coated either by the insulating regions 109 or by the heating element 107.

Although this has not been detailed in the figures, the memory cells 101 of the device 100 are for example arranged in a matrix. More precisely, the device 100 may for example comprise first lines, called bit lines, corresponding to rows of memory cells 101 parallel to each other and extending along a direction orthogonal to the plane of the , and second lines, called word lines, corresponding to rows of memory cells 101 parallel to each other and orthogonal to the bit lines.

Although this has not been detailed in FIGS. 1A and 1B, the contact recovery element 105 of each memory cell 101 passes through the substrate 103, for example, and makes it possible to connect the horizontal part of the overlying heating element 107 to a conduction terminal of a selection element, not shown, for example a MOS transistor (from the English “Metal-Oxide-Semiconductor”), located on the side of a face of the substrate 103 opposite the face 103T. The selection transistor, or selector, makes it possible to individually select each memory cell 101 of the device 100. For example, the selection transistors each comprise another conduction terminal connected to a node for applying a reference potential, for example ground, and a control terminal (gate) to which a control voltage is applied, depending on its value, to allow or prevent current flow between the conduction terminals (source and drain) of the transistor. The selection transistors of the memory cells 101 forming part of the same word line comprise, for example, a common gate, extending, for example, along a direction orthogonal to the plane of the .

Furthermore, all the memory cells forming part of the same bit line are for example interconnected, by their conductive regions 113, by means of a common electrode not shown in FIGS. 1A and 1B.

The memory cells 101 of the matrix of the memory device 100 can store data by modifying the phase of the material constituting their respective regions 111. In general, phase-change materials are materials capable of alternating, under the effect of a temperature variation, between a crystalline phase and an amorphous phase, the amorphous phase having an electrical resistance greater than that of the crystalline phase. In the case of the memory cells 101, this phenomenon is used to obtain an on state, allowing a current to flow between the contact recovery element 105 and the conductive region 113, when the material of the region 111 is in the crystalline phase, and a blocked state, preventing a current from flowing between the contact recovery element 105 and the conductive region 113, when at least part of the material of the region 111 is in the amorphous phase. In the present description, it is considered for simplicity that the entire region 111 undergoes the phase changes. However, in practice, the phase changes can take place in only a part of the region 111, for example located on and in contact with the upper face of the heating element 107.

The on (region 111 in crystalline phase) and off (region 111 in amorphous phase) states of each memory cell 101 correspond for example to logic values 1 and 0 respectively. When the cell 101 switches between logic states 1 and 0, the contact recovery element 105 and the conductive region 113 are for example subjected to a control voltage pulse causing a flow of current through the heating element 107. This current causes, by Joule effect then by radiation and/or conduction inside the structure of the cell 101, a rise in temperature of the region 111 from its lower face, located opposite the heating element 107.

More specifically, to switch the memory cell from logic state 1 to logic state 0, region 111 is heated by means of heating element 107, for example at a temperature T1 and for a duration d1. Temperature T1 and duration d1 are chosen so as to cause a phase change of the material of region 111 from the crystalline phase to the amorphous phase. Temperature T1 is for example higher than the melting temperature of the phase change material. For example, temperature T1 is between 600 and 1000°C and duration d1 is less than 500 ns.

Conversely, to switch the memory cell 101 from the logic state 0 to the logic state 1, the region 111 is heated by means of the heating element 107, for example at a temperature T2 lower than the temperature T1 and for a duration d2 greater than the duration d1. The temperature T2 and the duration d2 are chosen so as to cause a phase change of the material of the region 111 from the amorphous phase to the crystalline phase. The temperature T2 is for example higher than a melting temperature of the material of the region 111. For example, the temperature T2 is substantially equal to the temperature T1 and the duration d2 is less than 1 µs.

After manufacturing the memory device 100 and before writing or programming operations are implemented, the phase change material region 111 of each memory cell 101 is for example in a crystalline phase. In other words, the memory device 100 is, before writing, in an initial state where all its cells 101 contain the same logic value (the value 1, in this example). Data storage operations can then be carried out in the memory device 100, by operating a phase change of the regions 111 of a part of the memory cells 101 from the crystalline phase to the amorphous phase, corresponding in this example to a logic value 0, while the regions 111 of the other part of the cells 101 are maintained in their initial state, in other words in the crystalline phase corresponding in this example to the logic value 1.

To read one of the phase change memory cells 101 of the device 100, the cell is selected by biasing the gate of the associated selection transistor. A flow of a current, having a value sufficiently low to avoid any involuntary phase change, is then caused in the cell 101 by applying a potential difference between the conductive region 113 and the contact recovery element 105. An electrical resistance, between the conductive region 113 and the contact recovery element 105, can then be measured. This electrical resistance reflects the logic value, 0 or 1, previously stored in the memory cell 101.

Although this has not been detailed in FIGS. 1A and 1B, the device 100 may comprise other layers, for example layers of dielectric materials, arranged on the side of the face 103T of the substrate 103.

THE , , , , , , , And are sectional views illustrating, schematically and partially, successive steps of a method of manufacturing a memory device 200 comprising memory cells 201 based on a phase change material according to one embodiment.

The memory device 200 of FIGS. 2A to 2I includes elements in common with the memory device 100 of FIGS. 1A and 1B. These common elements will not be described again below.

There is a sectional view illustrating more precisely a structure obtained at the end of a deposition step, on the side of the face 103T of the substrate 103, of a stack of thermally insulating layers 203 and 205. In the example shown, the insulating layer 203 covers the upper face 103T of the substrate 103 and the upper face of the contact recovery elements 105 which are flush with the face 103T. In this example, the insulating layer 205 covers the face of the insulating layer 203 opposite the substrate 103 (the upper face of the insulating layer 203, in the orientation of the ).

According to one embodiment, the insulating layer 203 is made of a material having a density, or a volumetric mass, lower than that of the material of the insulating layer 205. The insulating layer 203 is for example made of silicon carbide (SiC) or silicon carbonitride (SiCN).

The insulating layer 205 is for example made of silicon nitride (SiN), silicon carbonitride, germanium nitride (GeN), carbon nitride (CN) or carbon (C). Alternatively, the insulating layers 203 and 205 are both made of silicon carbide (SiC) or silicon nitride (SiN), and the insulating layer 205 has a density, or volumetric mass, greater than that of the insulating layer 203. In this case, the layer 203 has for example a volumetric mass of between 0.5 and 1.5 g/cm ³ and the layer 205 has for example a volumetric mass greater than 2 g/cm ³ . For example, the insulating layer 203 has a thickness of between 50 nm and 150 nm, for example equal to approximately 80 nm, and the insulating layer 205 has a thickness of between 5 nm and 50 nm, for example equal to approximately 20 nm.

Layers 203 and 205 are for example both electrically insulating.

There is a sectional view illustrating a structure obtained at the end of a step of forming trenches 207 in the insulating layers 203 and 205. For the purposes of simplification, only one trench 207 is shown in FIG. .

In the example shown, the trench 207 extends from the upper face of the layer 205 to the face 103T of the substrate 103, completely crossing the layers 203 and 205. In this example, parts of the upper faces of two adjacent contact recovery elements 105 as well as a part of the face 103T of the substrate 103 located between the two contact recovery elements 105 are exposed at the bottom of the trench 207.

The trenches 207 are for example substantially parallel to each other and extend along a direction substantially orthogonal to the plane of the . The trenches 207 laterally separate disjointed portions of the layers 203 and 205. In this example, the portions of the layers 203 and 205 separated by the trenches 207 are substantially parallel to each other and extend along a direction substantially orthogonal to the plane of the .

For example, trenches 207 are formed by photolithography and then etching.

There is a sectional view illustrating a structure obtained at the end of a deposition step, on the side of the face 103T of the substrate 103, of an electrically conductive layer 209 coated with an electrically insulating layer 211.

In the example shown, the electrically conductive layer 209 covers the walls and the bottom of the trenches 207 and extends laterally over and in contact with the upper face of the layer 205. More specifically, in this example, the electrically conductive layer 209 covers the sides and the upper face of the parts of the layer 205 remaining after the formation of the trenches 207, the sides of the parts of the layer 203 remaining after the formation of the trenches 207, and the parts of the upper faces of the contact recovery elements 105 and of the face 103T of the substrate 103 previously exposed at the bottom of the trenches 207. The insulating layer 211 covers the face of the conductive layer 209 opposite the substrate 103 (the upper face of the conductive layer 209, in the orientation of the ).

For example, the conductive layer 209 has a thickness of between 1 nm and 20 nm, for example equal to approximately 3 nm, and the insulating layer 211 has a thickness of between 5 nm and 100 nm, for example equal to approximately 20 nm.

In the example illustrated in , layers 209 and 211 do not fill, that is to say do not completely fill, trench 207. This example is however not limiting, the stack formed by layers 209 and 211 being able to fill trench 207.

For example, the conductive layer 209 is made of a metal or a metal alloy, for example titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN) or titanium silicon nitride (TiSiN).

For example, the insulating layer 211 is made of silicon nitride (SiN) or silicon carbide (SiC).

There is a sectional view illustrating a structure obtained at the end of an anisotropic etching step of the layers 209 and 211. More precisely, in the example shown, the etching speed of the layers 209 and 211 is greater along a direction orthogonal to the face 103T of the substrate 103 than in directions parallel to the face 103T.

In the example illustrated in , the parts of layers 209 and 211 located directly above the parts of layers 203 and 205, in other words the parts of layers 209 and 211 not located inside the trenches 207, are eliminated. , there remain, inside each trench 207, two separate parts of the conductive layer 209 covering opposite sides and extending onto opposite parts of the bottom of the trench 207. Each part of the conductive layer 209 has a general L shape, a horizontal part of which covers at least part of the upper face of one of the contact recovery elements 105 and a vertical part of which covers the sides of the parts of the insulating layers 203 and 205 located near the contact recovery element 105.

Each L-shaped portion of the conductive layer 209 corresponds to a heating element of a memory cell 201 of the device 200, for example identical or analogous to the heating elements 107 of the cells 101 of the device 100 previously described in relation to FIGS. 1A and 1B.

In addition, in the example illustrated, there remain disjointed portions of the insulating layer 211 located inside the Ls formed by the portions of the layer 209. Each portion of the insulating layer 211 more precisely covers the upper face of the horizontal portion of the L formed by the portion of the layer 209, and the face of the vertical portion of the L facing the horizontal portion of the L. In the example shown, the portions of the insulating layer 211 have a flared shape. More precisely, each portion of the insulating layer 211 is wider in the vicinity of the horizontal portion of the L formed by the portion of the associated layer 209 than in the vicinity of the end of the vertical portion of the L opposite the horizontal portion.

There is a sectional view illustrating a structure obtained at the end of a deposition step, on the side of the face 103T of the substrate 103, of an electrically and thermally insulating layer 213.

In the example shown, the insulating layer 213 fills the trenches 207 and covers the upper face of the parts of the layer 205 previously exposed at the end of the anisotropic etching step. In the example shown, the insulating layer 213 also covers the free faces of the parts of the layers 209 and 211 remaining at the end of the anisotropic etching step, as well as the parts of the face 103T of the substrate 103 and the parts of the upper faces of the contact recovery elements 105 previously exposed at the end of the anisotropic etching step.

The insulating layer 213 is for example made of the same material as the insulating layer 203, for example silicon carbide (SiC). Alternatively, the layer 213 is made of a material different from the material of the layer 203, for example silicon dioxide (SiO ₂ ).

There and the are sectional views, respectively according to plane AA of the and according to the BB plan of the , illustrating a structure obtained at the end of a step of thinning the insulating layer 213 then depositing, on the side of the face 103T of the substrate 103, a layer of a phase change material 215 and an electrically conductive layer 217. The plane AA of the is substantially orthogonal to the plane BB of the .

In the example shown, only parts of the insulating layer 213 located inside the trenches 207 remain at the end of the thinning step, the parts of the insulating layer 213 located directly above the parts of the insulating layers 203 and 205 being completely eliminated. Furthermore, in this example, the thinning of the insulating layer 213 is carried out so as to reduce the thickness of the insulating layer 205 and the height of the parts of the layers 209 and 211 remaining at the end of the anisotropic etching step. In the example shown, each part of the layer 209 is separated from the part of the layer 213 located opposite by a thickness of material of the layer 211 greater than or equal to approximately 20 nm.

In the example shown, the phase change material layer 215 covers the upper faces of the parts of the layers 205, 209, 211 and 213 after thinning. In this example, the conductive layer 217 covers the upper face of the phase change material layer 215. The compositions of the phase change material layer 215 and of the conductive layer 217 are for example identical or analogous respectively to the compositions of the regions 111 and 113 of the memory cells 101 of the device 100.

For example, the phase change material layer 215 has a thickness of between 20 nm and 100 nm, for example equal to approximately 50 nm, and the conductive layer 217 has a thickness of between 10 nm and 100 nm, for example equal to approximately 50 nm.

In the example shown, the contact recovery elements 105 and the parts of the conductive layer 217 form conduction electrodes of the cell 201.

There and the are sectional views, respectively according to plane AA of the and according to the BB plan of the , illustrating a structure obtained at the end of a step of forming trenches 219 and 221 then depositing an encapsulation layer 223 on the side of the face 103T of the substrate 103. The plane AA of the is substantially orthogonal to the plane BB of the .

In the example shown, trenches 219 and 221 extend vertically in the structure, from the upper face of layer 217, to face 103T of substrate 103. Alternatively, trenches 219 may be omitted.

The trenches 219 are for example substantially parallel to each other and extend along a direction substantially orthogonal to the plane of the . The trenches 219 laterally separate the memory cells 201 forming part of the same word line of the memory device 200. Furthermore, the trenches 221 are substantially parallel to each other and extend along a direction substantially orthogonal to the plane of the . The trenches 221 laterally separate the memory cells 201 forming part of the same bit line of the memory device 200.

For example, trenches 219 and 221 are formed by photolithography then etching.

At the end of the step of forming the trenches 219 and 221, the heating element and the phase change material region of each memory cell 201 are electrically isolated from the heating elements and the phase change material regions of the neighboring memory cells 201.

In the example shown, the encapsulation layer 223 covers the structure comprising the parts of the insulating layers 203, 205 and 213, the parts of the phase change material layer 215 and the electrically conductive layer 217 of each memory cell 201. The encapsulation layer 223 more precisely covers all the lateral faces of the parts of the insulating layers 203, 205 and 213, all the lateral faces of the parts of the phase change material layer 215 and all the lateral faces and the upper face of the parts of the conductive layer 217, as well as the lateral faces of the L-shaped part of the layer 209 parallel to the plane of the , not coated by the insulating layers 203, 205 and 213. The encapsulation layer 223 can further extend between the memory cells 201, as in the example illustrated in FIGS. 2H and 2I. In this example, the layer 223 more particularly coats parts of the face 103T of the substrate 103 which are not coated either by the parts of the insulating layers 203 and 213, or by the heating element 209.

Although this has not been illustrated, the memory device 200 may further comprise selection elements, for example MOS transistors, located on the side of a face of the substrate 103 opposite the face 103T as explained previously in relation to FIGS. 1A and 1B for the memory device 100. In general, the memory device 200 has, for example, an operation identical or similar to the device 100 of FIGS. 1A and 1B.

An advantage of the memory device 200 of FIGS. 2H and 2I is that the layer 203 provides better thermal insulation of the memory cell 201, and therefore a more uniform heat distribution in the phase change material of the layer 215, in particular compared to the memory cell 101. As a result, the electrical energy required to heat the phase change material is lower in the case of the memory device 200 than in the case of the memory device 100. Advantageously, this allows the memory device 200 incorporating the cells 201 to have lower energy consumption than the memory device 100 incorporating the cells 101.

Furthermore, an advantage of the method for manufacturing the memory device 200 set out above in relation to FIGS. 2A to 2I is that it allows the insulating layer 205 to be interposed between the layer 203 and the phase change material layer 215. The insulating layer 205 advantageously allows the layer 203 to be chemically stabilized when the phase change material layer 215 is heated during the programming operations of the memory cell 201. More particularly, this allows the material of the layer 203 not to be in contact with the material of the layer 215 in the immediate vicinity of the heating element 209, and thus avoids undesirable chemical reactions between the material of the layer 203 and the material of the layer 215 during heating. This makes it possible to use, for the layer 203, more varied materials, and in particular materials having a better thermal insulation coefficient, than the materials which can be placed in direct contact with the layer 215 in the immediate vicinity of the heating element 209.

THE And are sectional views, respectively according to plane AA of the and according to the BB plan of the , illustrating, schematically and partially, a memory device 300 comprising memory cells 301 based on a phase change material according to one embodiment. The plane AA of the is substantially orthogonal to the plane BB of the .

Although Figures 3A and 3B illustrate an example in which the stack formed by layers 203 and 205 has lateral dimensions substantially identical to those of the stack formed by layers 215 and 217, the stack formed by layers 215 and 217 may, as a variant, have lateral dimensions different from those of the stack formed by layers 203 and 205.

The device 300 of FIGS. 3A and 3B comprises elements in common with the device 200 of FIGS. 2H and 2I. These common elements will not be detailed again below. The device 300 of FIGS. 3A and 3B differs from the device 200 of FIGS. 2H and 2I in that the device 300 comprises memory cells 301 comprising several encapsulation layers having different densities.

In the example shown, the memory cells 301 comprise an encapsulation layer 303 coating the structure comprising the parts of the insulating layers 203, 205 and 213 of each memory cell 301. The encapsulation layer 303 more precisely coats all the lateral faces of the parts of the insulating layers 203, 205 and 213, as well as the lateral faces of the L-shaped part of the layer 209 parallel to the plane of the , not coated by the insulating layers 203, 205 and 213. The encapsulation layer 303 can further extend between the memory cells 301, as in the example illustrated in FIGS. 3A and 3B. In this example, the layer 303 more particularly coats parts of the face 103T of the substrate 103 which are not coated either by the parts of the insulating layers 203 and 213, or by the heating element 209.

According to one embodiment, the encapsulation layer 303 is coated with at least one other encapsulation layer 305 (only one other encapsulation layer 305, in the example shown) made of a material having a density lower than that of the layer 303. For example, the layer 305 is made of the same material as the layer 303, for example silicon carbide, but has a density lower than that of the layer 303. As a variant, the layer 305 is made of a material different from the material of the layer 303. For example, the encapsulation layers 303 and 305 are respectively made of silicon nitride (SiN) and silicon carbide (SiC).

In the example shown, a dielectric filler material 307 coats the encapsulation layer 305 and fills the free spaces between the memory cells 301. In this example, the filler material 307 is flush with the upper face of the insulating layers 205 and 213.

In the example illustrated in FIGS. 3A and 3B, the memory cells 301 comprise another encapsulation layer 313 coating the structure comprising the portions of the phase change material layer 215 and the electrically conductive layer 217 of each memory cell 301. The encapsulation layer 223 more specifically coats all the lateral faces of the portions of the phase change material layer 215 and all the lateral faces and the upper face of the portions of the conductive layer 217. The encapsulation layer 313 may further extend between the memory cells 301, as in the example illustrated in FIGS. 3A and 3B. In this example, the layer 313 more particularly coats the upper faces of the encapsulation layers 303 and 305 and the filling material 307.

In the example shown, the encapsulation layer 313 is coated with at least one other encapsulation layer 315 (only one other encapsulation layer 315, in the example shown) made of a material having a density lower than that of the layer 313. For example, the layer 315 is made of the same material as the layer 313, for example silicon carbide, but has a density lower than that of the layer 313. Alternatively, the layer 315 is made of a material different from the material of the layer 313. For example, the encapsulation layers 313 and 315 are respectively made of the same materials and respectively have the same densities as the encapsulation layers 303 and 305.

The device 300 is for example obtained by a manufacturing method similar to that of the device 200 described above in relation to FIGS. 2A to 2I. For example, the heating elements 209 of the memory cells 301 are individualized after the deposition of the insulating layer 213, then the encapsulation layers 303 and 305 and the filling material 307 are deposited on the structure on the side of the upper face 103T of the substrate 103. The encapsulation layers 303 and 305, the filling material 307 and the insulating layer 213 are then thinned until the insulating layer 205 is reached, the layer 205 also being able to be thinned during this step. The phase change material layer 215 and the conductive layer 217 can then be deposited and then structured, for example by photolithography and then etching, so as to individualize the phase change material layer 215 and the conductive layer 217 of the memory cells 301. Finally, the encapsulation layers 313 and 315 can be successively deposited on the structure on the side of the face 103T of the substrate 103.

Although an exemplary embodiment has been described in connection with FIGS. 3A and 3B in which the encapsulation layers 303 and 305 and the filler material 307 are deposited before the phase change material layer 215, it could alternatively be provided to deposit the encapsulation layers 303 and 305 after the phase change material layer 215, for example after the deposition of the layer 217. In this case, the encapsulation layers 313 and 315 can be omitted, the stack of the encapsulation layers 303 and 305 then replacing the encapsulation layer 223 of FIGS. 2H and 2I.

An advantage of the memory device 300 of FIGS. 3A and 3B is that the stacking of the encapsulation layers 303 and 305 makes it possible to obtain better thermal insulation of the memory cell 301, and therefore a more uniform heat distribution in the phase change material of the layer 215, in particular compared to the memory cell 101. As a result, the electrical energy required to heat the phase change material is lower in the case of the memory device 300 than in the case of the memory device 100. Advantageously, this allows the memory device 300 integrating the cells 301 to have lower energy consumption than the memory device 100 integrating the cells 101.

3A and 3B is that the encapsulation layer 303, respectively 313, of higher density, is interposed between the layer 305, respectively 315, of lower density, and the layer 215 of the phase change material in the vicinity of the hottest point of the layer 215, that is to say in the vicinity of the surface of the layer 215 in contact with the heating element 209. The encapsulation layer 303, respectively 313 thus makes it possible to chemically stabilize the layer 305, respectively 315 during the heating of the layer of phase change material 215 during the programming operations of the memory cell 301. More particularly, this makes it possible to avoid undesirable chemical reactions between the material of the layer 305, respectively 315 and the material of the layer 215 during heating.

Although stacks each consisting of only two encapsulation layers 303, 313 and 305, 315 have been illustrated, it would be possible, as an alternative:
– to coat the encapsulation layer 305, respectively 315, with another encapsulation layer having a density lower than that of the encapsulation layer 305, respectively 315, for example a silicon carbide layer less dense than the layer 305, respectively 315;
– to coat the encapsulation layer 305, respectively 315, with another encapsulation layer having a density greater than that of the encapsulation layer 305, respectively 315, for example a silicon nitride layer or a silicon carbide layer denser than the layer 305, respectively 315;
– to coat the encapsulation layer 305, respectively 315, with another stack comprising an alternation of encapsulation layers of the type of layers 303 and 305, respectively 313 and 315, and which may end with a layer having a density substantially equal to that of the encapsulation layer 303, respectively 313, for example a layer of silicon nitride; or
– to coat the encapsulation layer 305, respectively 315, with another stack of encapsulation layers, made of different materials or of the same material, having densities lower than those of the layer 305, respectively 315, and decreasing as one moves away from the layer 305, respectively 315, for example so as to obtain an encapsulation layer made of a single material, for example silicon carbide, having a density gradient, said encapsulation layer being coated with an external layer having a high density, substantially equal to that of the encapsulation layer 303, respectively 313, for example a layer made of silicon nitride.

Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the embodiment of the memory device 300 of FIGS. 3A and 3B is transposable by those skilled in the art to the memory device 100 of FIGS. 1A and 1B.

Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the person skilled in the art is capable of choosing the deposition and etching techniques to be implemented to produce the different layers and regions of the devices described.

Claims (12)

Phase change memory cell (301) comprising:
– a first layer of a phase change material (215);
– a heating element (209) located under the first layer (215);
– a second insulating layer (203) covering a side of the heating element (209); and
– a first stack comprising a third encapsulation layer (303) covering the lateral faces of the second layer (203) and a fourth encapsulation layer (305) covering the third layer (303) and being made of a material having a density lower than that of the material of the third layer (303). Cell according to claim 1, in which the fourth layer (305) is coated with a second stack comprising an alternation of encapsulation layers having densities substantially equal to those of the third and fourth layers (303, 305). Cell according to claim 1, in which the fourth layer (305) is coated with a second stack comprising successive encapsulation layers having decreasing densities, lower than those of the fourth layer (305). Cell according to claim 3, in which the successive encapsulation layers of the second stack are made of the same material. Cell according to any one of claims 2 to 4, further comprising a sixth encapsulation layer, coating the fourth layer (305) or the second stack, the sixth layer having a density greater than that of the fourth layer (305). Cell according to any one of claims 1 to 5, further comprising a first conduction electrode (105) located under and in contact with a face of the heating element (209) opposite the first layer (215) and a second conduction electrode (217) located on and in contact with a face of the first layer (215) opposite the heating element (209). Cell according to claim 6, further comprising a third stack comprising a seventh encapsulation layer (313) coating the lateral faces of the first layer (215) and of the second conduction electrode (217) and an eighth encapsulation layer (315) coating the seventh layer (313) and having a density lower than that of the seventh layer (313). Cell according to any one of claims 1 to 7, further comprising a ninth layer (205) interposed between the first and second layers (215, 203) and having a density greater than that of the second layer (203), the second layer (203) being made of silicon carbide or silicon carbonitride. Cell according to claim 8, in which the ninth layer (205) is made of silicon carbide, silicon nitride or silicon carbonitride and has a density greater than that of the second layer (203). The cell of claim 8, wherein the ninth layer (205) is germanium nitride, carbon nitride or carbon. Method of manufacturing a phase change memory cell (301) comprising the following successive steps:
a) depositing, on a substrate (103), at least one first thermally insulating layer (203);
b) forming, in a trench passing through said at least one first layer (203), a heating element (209) one side of which is coated with said at least one first layer (203); and
c) forming a first stack comprising a second encapsulation layer (303) coating the lateral faces of said at least one first layer (203) and a third encapsulation layer (305) coating the second layer (303), the third layer (305) being made of a material having a density lower than that of the material of the second layer (303),
the method further comprising a step of forming a layer of a phase change material (215). Method according to claim 11, further comprising, after step c), a step d) of depositing a fourth encapsulation layer coating the third layer (305) and having a density greater than that of the third layer (305).