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FR3113326B1 - Procédé de calcul convolutif intra-mémoire et circuit intégré correspondant - Google Patents

Procédé de calcul convolutif intra-mémoire et circuit intégré correspondant Download PDF

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Publication number
FR3113326B1
FR3113326B1 FR2008327A FR2008327A FR3113326B1 FR 3113326 B1 FR3113326 B1 FR 3113326B1 FR 2008327 A FR2008327 A FR 2008327A FR 2008327 A FR2008327 A FR 2008327A FR 3113326 B1 FR3113326 B1 FR 3113326B1
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Prior art keywords
voltage signals
integrated circuit
convolutional calculation
pcmij
iwl
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Active
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FR2008327A
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English (en)
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FR3113326A1 (fr
Inventor
Antonino Conte
Rosa Francesco La
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STMicroelectronics Rousset SAS
STMicroelectronics SRL
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STMicroelectronics Rousset SAS
STMicroelectronics SRL
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Application filed by STMicroelectronics Rousset SAS, STMicroelectronics SRL filed Critical STMicroelectronics Rousset SAS
Priority to FR2008327A priority Critical patent/FR3113326B1/fr
Priority to US17/393,075 priority patent/US20220044099A1/en
Priority to EP21189279.9A priority patent/EP3955171A1/fr
Priority to CN202110899221.7A priority patent/CN114067884A/zh
Publication of FR3113326A1 publication Critical patent/FR3113326A1/fr
Application granted granted Critical
Publication of FR3113326B1 publication Critical patent/FR3113326B1/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G06F17/153—Multidimensional correlation or convolution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Biophysics (AREA)
  • Mathematical Physics (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Health & Medical Sciences (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • Evolutionary Computation (AREA)
  • Neurology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Le circuit intégré pour le calcul convolutif (CNVL) comprend une matrice (ARR) de points mémoires non volatils (MPTij) comprenant chacun une cellule mémoire résistive à changement de phase (PCMij) couplée à une ligne de bit (BLj), et un transistor bipolaire de sélection (BJTij) couplé en série à la cellule et ayant une borne de base reliée à une ligne de mot (WLi), un circuit convertisseur d’entrée (INCVRT) configuré pour recevoir et convertir des valeurs d’entrée (A1-A4) en signaux de tension (V1-V4) et pour appliquer successivement les signaux de tension (V1-V4) sur des lignes de bit sélectionnées (BL1-BL4) sur des intervalles de temps respectifs (t1-t4), et un circuit convertisseur de sortie (OUTCVRT) configuré pour intégrer sur les intervalles de temps successifs (t1-t4) les courants de lecture (IWL) résultant des signaux de tension (V1-V4) qui polarisent les cellules mémoires résistives à changement de phase respectives (PCMij) et circulant dans des lignes de mots sélectionnées, et pour convertir les courants de lecture intégrés (IWL) en valeurs de sortie (Bi). Figure de l’abrégé : Fig 4
FR2008327A 2020-08-06 2020-08-06 Procédé de calcul convolutif intra-mémoire et circuit intégré correspondant Active FR3113326B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR2008327A FR3113326B1 (fr) 2020-08-06 2020-08-06 Procédé de calcul convolutif intra-mémoire et circuit intégré correspondant
US17/393,075 US20220044099A1 (en) 2020-08-06 2021-08-03 Method for in-memory convolutional computation and corresponding integrated circuit
EP21189279.9A EP3955171A1 (fr) 2020-08-06 2021-08-03 Procédé de calcul de convolution en mémoire et circuit intégré correspondant
CN202110899221.7A CN114067884A (zh) 2020-08-06 2021-08-05 用于存储器中卷积计算的方法和对应的集成电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2008327A FR3113326B1 (fr) 2020-08-06 2020-08-06 Procédé de calcul convolutif intra-mémoire et circuit intégré correspondant
FR2008327 2020-08-06

Publications (2)

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FR3113326A1 FR3113326A1 (fr) 2022-02-11
FR3113326B1 true FR3113326B1 (fr) 2023-01-06

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FR2008327A Active FR3113326B1 (fr) 2020-08-06 2020-08-06 Procédé de calcul convolutif intra-mémoire et circuit intégré correspondant

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US (1) US20220044099A1 (fr)
EP (1) EP3955171A1 (fr)
CN (1) CN114067884A (fr)
FR (1) FR3113326B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11942144B2 (en) 2022-01-24 2024-03-26 Stmicroelectronics S.R.L. In-memory computation system with drift compensation circuit
US11894052B2 (en) * 2022-04-12 2024-02-06 Stmicroelectronics S.R.L. Compensated analog computation for an in-memory computation system
US12211582B2 (en) 2022-04-12 2025-01-28 Stmicroelectronics S.R.L. Signed and binary weighted computation for an in-memory computation system
CN118098310B (zh) * 2024-04-25 2024-08-20 南京大学 基于超前补偿型跨阻放大器的光电存算阵列读出电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8270193B2 (en) * 2010-01-29 2012-09-18 Unity Semiconductor Corporation Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
US8120941B2 (en) * 2008-11-07 2012-02-21 Seagate Technology Llc Bidirectional non-volatile memory array architecture
US7869267B2 (en) * 2008-12-29 2011-01-11 Numonyx B.V. Method for low power accessing a phase change memory device
WO2017105514A1 (fr) * 2015-12-18 2017-06-22 Intel Corporation Appareil et procédé de calcul en mémoire à l'aide de réseaux non-volatils
US10706923B2 (en) * 2017-09-08 2020-07-07 Arizona Board Of Regents On Behalf Of Arizona State University Resistive random-access memory for exclusive NOR (XNOR) neural networks
JP7130766B2 (ja) * 2018-04-05 2022-09-05 レイン・ニューロモーフィックス・インコーポレーテッド 効率的な行列乗算のためのシステムおよび方法
US11574209B2 (en) * 2019-05-30 2023-02-07 International Business Machines Corporation Device for hyper-dimensional computing tasks
US20210064379A1 (en) * 2019-08-29 2021-03-04 Arm Limited Refactoring MAC Computations for Reduced Programming Steps
CN110807519B (zh) * 2019-11-07 2023-01-17 清华大学 基于忆阻器的神经网络的并行加速方法及处理器、装置
US11636322B2 (en) * 2020-01-03 2023-04-25 Silicon Storage Technology, Inc. Precise data tuning method and apparatus for analog neural memory in an artificial neural network
US11537861B2 (en) * 2020-06-23 2022-12-27 Micron Technology, Inc. Methods of performing processing-in-memory operations, and related devices and systems
US11782642B2 (en) * 2021-06-14 2023-10-10 Western Digital Technologies, Inc. Systems and methods of determining degradation in analog compute-in-memory (ACIM) modules

Also Published As

Publication number Publication date
FR3113326A1 (fr) 2022-02-11
US20220044099A1 (en) 2022-02-10
CN114067884A (zh) 2022-02-18
EP3955171A1 (fr) 2022-02-16

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