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FR3098984B1 - Integrated circuit with double insulation of the deep and shallow trench type - Google Patents

Integrated circuit with double insulation of the deep and shallow trench type Download PDF

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Publication number
FR3098984B1
FR3098984B1 FR1908042A FR1908042A FR3098984B1 FR 3098984 B1 FR3098984 B1 FR 3098984B1 FR 1908042 A FR1908042 A FR 1908042A FR 1908042 A FR1908042 A FR 1908042A FR 3098984 B1 FR3098984 B1 FR 3098984B1
Authority
FR
France
Prior art keywords
integrated circuit
deep
shallow trench
transistors
trench type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1908042A
Other languages
French (fr)
Other versions
FR3098984A1 (en
Inventor
Thomas Bedecarrats
Philippe Galy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics France SAS
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR1908042A priority Critical patent/FR3098984B1/en
Priority to US16/927,510 priority patent/US11450689B2/en
Publication of FR3098984A1 publication Critical patent/FR3098984A1/en
Application granted granted Critical
Publication of FR3098984B1 publication Critical patent/FR3098984B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

Circuit intégré, comprenant, dans et sur un substrat semiconducteur du type silicium sur isolant, des rangées (TRKn, TRKn+1) s’étendant selon une direction (DR1) et comportant chacune des transistors MOS complémentaires (TRN, TRP) et les régions associées de prises de contact (NNCT, PNCT) permettant une polarisation de la grille arrière de ces transistors, tous les transistors (TRN, TRP) et lesdites régions associées de prises de contact (NNCT, PNCT) d’une même rangée étant mutuellement isolés par une première tranchée d’isolation (DTI1), et chaque rangée étant bordée sur ses deux bords parallèles à ladite direction (DR1) par deux deuxièmes tranchées d’isolation (STI1, STI2) moins profondes que la première tranchée (DTI1). Figure pour l’abrégé : Fig 4Integrated circuit, comprising, in and on a semiconductor substrate of the silicon-on-insulator type, rows (TRKn, TRKn + 1) extending in one direction (DR1) and each comprising complementary MOS transistors (TRN, TRP) and the regions associated contact points (NNCT, PNCT) allowing biasing of the rear gate of these transistors, all the transistors (TRN, TRP) and said associated contact point regions (NNCT, PNCT) of the same row being mutually isolated by a first insulation trench (DTI1), and each row being bordered on its two edges parallel to said direction (DR1) by two second insulation trenches (STI1, STI2) shallower than the first trench (DTI1). Figure for the abstract: Fig 4

FR1908042A 2019-07-17 2019-07-17 Integrated circuit with double insulation of the deep and shallow trench type Active FR3098984B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1908042A FR3098984B1 (en) 2019-07-17 2019-07-17 Integrated circuit with double insulation of the deep and shallow trench type
US16/927,510 US11450689B2 (en) 2019-07-17 2020-07-13 Integrated circuit with double isolation of deep and shallow trench-isolation type

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1908042A FR3098984B1 (en) 2019-07-17 2019-07-17 Integrated circuit with double insulation of the deep and shallow trench type
FR1908042 2019-07-17

Publications (2)

Publication Number Publication Date
FR3098984A1 FR3098984A1 (en) 2021-01-22
FR3098984B1 true FR3098984B1 (en) 2021-08-06

Family

ID=68501767

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1908042A Active FR3098984B1 (en) 2019-07-17 2019-07-17 Integrated circuit with double insulation of the deep and shallow trench type

Country Status (2)

Country Link
US (1) US11450689B2 (en)
FR (1) FR3098984B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3144402A1 (en) * 2022-12-21 2024-06-28 Stmicroelectronics International N.V. Electronic circuit comprising a transistor cell

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175659A1 (en) * 2005-02-07 2006-08-10 International Business Machines Corporation A cmos structure for body ties in ultra-thin soi (utsoi) substrates
US20130119506A1 (en) * 2011-11-10 2013-05-16 Toshiba America Electronic Components, Inc. Formation of sti trenches for limiting pn-junction leakage
US9214378B2 (en) * 2012-06-29 2015-12-15 International Business Machines Corporation Undercut insulating regions for silicon-on-insulator device
WO2014131459A1 (en) * 2013-02-28 2014-09-04 Commissariat à l'énergie atomique et aux énergies alternatives Low leakage dual sti integrated circuit including fdsoi transistors
US9356045B2 (en) * 2013-06-10 2016-05-31 Raytheon Company Semiconductor structure having column III-V isolation regions
US9525077B1 (en) * 2015-11-04 2016-12-20 Texas Instruments Incorporated Integration of a baritt diode
US10062710B2 (en) * 2016-05-11 2018-08-28 Globalfoundries Singapore Pte. Ltd. Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same
US10043826B1 (en) * 2017-07-26 2018-08-07 Qualcomm Incorporated Fully depleted silicon on insulator integration
US10460982B1 (en) * 2018-06-14 2019-10-29 International Business Machines Corporation Formation of semiconductor devices with dual trench isolations

Also Published As

Publication number Publication date
FR3098984A1 (en) 2021-01-22
US11450689B2 (en) 2022-09-20
US20210020660A1 (en) 2021-01-21

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