[go: up one dir, main page]

FR3098342B1 - structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF - Google Patents

structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF Download PDF

Info

Publication number
FR3098342B1
FR3098342B1 FR1907328A FR1907328A FR3098342B1 FR 3098342 B1 FR3098342 B1 FR 3098342B1 FR 1907328 A FR1907328 A FR 1907328A FR 1907328 A FR1907328 A FR 1907328A FR 3098342 B1 FR3098342 B1 FR 3098342B1
Authority
FR
France
Prior art keywords
semiconductor structure
layer
applications
porous layer
buried porous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1907328A
Other languages
English (en)
Other versions
FR3098342A1 (fr
Inventor
Emmanuel Augendre
Frédéric Gaillard
Thomas Lorne
Emmanuel Rolland
Christelle Veytizou
Isabelle Bertrand
Frédéric Allibert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1907328A priority Critical patent/FR3098342B1/fr
Priority to TW109109850A priority patent/TWI849089B/zh
Priority to PCT/EP2020/058316 priority patent/WO2021001066A1/fr
Priority to CN202080048789.1A priority patent/CN114424332A/zh
Priority to JP2021578062A priority patent/JP7464631B2/ja
Priority to KR1020227003597A priority patent/KR20220025892A/ko
Priority to US17/623,499 priority patent/US12119258B2/en
Priority to EP20712591.5A priority patent/EP3994722A1/fr
Publication of FR3098342A1 publication Critical patent/FR3098342A1/fr
Application granted granted Critical
Publication of FR3098342B1 publication Critical patent/FR3098342B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
  • Porous Artificial Stone Or Porous Ceramic Products (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L’invention concerne une structure semi-conductrice (10) pour applications radiofréquences comprenant : - un substrat support (2) en silicium comportant une couche méso-poreuse (3), - une couche diélectrique (4) disposée sur la couche méso-poreuse (3), - une couche superficielle (5) disposée sur la couche diélectrique (4). La structure (10) est remarquable en ce que : - la couche méso-poreuse (3) comporte des pores creux dont les parois internes sont majoritairement tapissées d’oxyde, et présente une épaisseur comprise entre 3 et 40 microns et une résistivité supérieure à 20 kohm.cm sur toute son épaisseur, - le substrat support (2) présente une résistivité comprise entre 0.5 et 4 ohm.cm. L’invention concerne également un procédé de fabrication d’une structure semi-conductrice (10). Figure à publier avec l’abrégé : F igure 1
FR1907328A 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF Active FR3098342B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1907328A FR3098342B1 (fr) 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF
TW109109850A TWI849089B (zh) 2019-07-02 2020-03-24 供無線射頻應用之包含埋置多孔層之半導體結構
CN202080048789.1A CN114424332A (zh) 2019-07-02 2020-03-25 用于射频应用的包括埋置多孔层的半导体结构
JP2021578062A JP7464631B2 (ja) 2019-07-02 2020-03-25 高周波アプリケーション用の埋め込みポーラス層を含む半導体構造
PCT/EP2020/058316 WO2021001066A1 (fr) 2019-07-02 2020-03-25 Structure semi-conductrice comprenant une couche poreuse enterree, pour applications rf
KR1020227003597A KR20220025892A (ko) 2019-07-02 2020-03-25 Rf 응용들을 위한 매립된 다공성 층을 포함하는 반도체 구조물
US17/623,499 US12119258B2 (en) 2019-07-02 2020-03-25 Semiconductor structure comprising a buried porous layer for RF applications
EP20712591.5A EP3994722A1 (fr) 2019-07-02 2020-03-25 Structure semi-conductrice comprenant une couche poreuse enterree, pour applications rf

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1907328 2019-07-02
FR1907328A FR3098342B1 (fr) 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF

Publications (2)

Publication Number Publication Date
FR3098342A1 FR3098342A1 (fr) 2021-01-08
FR3098342B1 true FR3098342B1 (fr) 2021-06-04

Family

ID=68138491

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1907328A Active FR3098342B1 (fr) 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF

Country Status (8)

Country Link
US (1) US12119258B2 (fr)
EP (1) EP3994722A1 (fr)
JP (1) JP7464631B2 (fr)
KR (1) KR20220025892A (fr)
CN (1) CN114424332A (fr)
FR (1) FR3098342B1 (fr)
TW (1) TWI849089B (fr)
WO (1) WO2021001066A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12027582B2 (en) * 2021-10-05 2024-07-02 Globalfoundries U.S. Inc. IC structure including porous semiconductor layer under trench isolation
US12119352B2 (en) 2022-01-06 2024-10-15 Globalfoundries U.S. Inc. IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation
GB2625281A (en) * 2022-12-12 2024-06-19 Iqe Plc Systems and methods for porous wall coatings
GB2625286A (en) * 2022-12-12 2024-06-19 Iqe Plc Systems and methods for tuning porous bandgaps to reduce thermal donor effects
GB2625285A (en) * 2022-12-12 2024-06-19 Iqe Plc Systems and methods for stress reduction in porous layers
GB2625283A (en) * 2022-12-12 2024-06-19 Iqe Plc Systems and methods for reducing defects in epitaxy on porous
GB2625284A (en) * 2022-12-12 2024-06-19 Iqe Plc Systems and methods for controlling porous resistivities
FR3144694A1 (fr) * 2022-12-28 2024-07-05 Commissariat A L' Energie Atomique Et Aux Energies Alternatives Procédé de fabrication d’une structure multicouche comprenant une couche de silicium poreux

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4708577B2 (ja) * 2001-01-31 2011-06-22 キヤノン株式会社 薄膜半導体装置の製造方法
US20040262686A1 (en) * 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
JP5673170B2 (ja) 2011-02-09 2015-02-18 信越半導体株式会社 貼り合わせ基板、貼り合わせ基板の製造方法、半導体デバイス、及び半導体デバイスの製造方法
FR2977075A1 (fr) * 2011-06-23 2012-12-28 Soitec Silicon On Insulator Procede de fabrication d'un substrat semi-conducteur, et substrat semi-conducteur
FR2977070A1 (fr) 2011-06-23 2012-12-28 Soitec Silicon On Insulator Procede de fabrication d'un substrat semi-conducteur comprenant du silicium poreux, et substrat semi-conducteur
FR2985812B1 (fr) 2012-01-16 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de test de substrats semi-conducteurs pour applications radiofrequences
FR3024587B1 (fr) * 2014-08-01 2018-01-26 Soitec Procede de fabrication d'une structure hautement resistive
WO2016149113A1 (fr) 2015-03-17 2016-09-22 Sunedison Semiconductor Limited Couche de piégeage de charge thermiquement stable destinée à être utilisée dans la fabrication de structures semi-conducteur sur isolant
FR3040108B1 (fr) 2015-08-12 2017-08-11 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse
US10181428B2 (en) 2015-08-28 2019-01-15 Skyworks Solutions, Inc. Silicon on porous silicon
FR3062238A1 (fr) 2017-01-26 2018-07-27 Soitec Support pour une structure semi-conductrice
CN108807284B (zh) * 2017-04-28 2020-06-26 环球晶圆股份有限公司 一种外延接合基板及其制造方法

Also Published As

Publication number Publication date
US12119258B2 (en) 2024-10-15
WO2021001066A1 (fr) 2021-01-07
TW202103320A (zh) 2021-01-16
JP7464631B2 (ja) 2024-04-09
US20220359272A1 (en) 2022-11-10
CN114424332A (zh) 2022-04-29
EP3994722A1 (fr) 2022-05-11
TWI849089B (zh) 2024-07-21
JP2022538463A (ja) 2022-09-02
FR3098342A1 (fr) 2021-01-08
KR20220025892A (ko) 2022-03-03

Similar Documents

Publication Publication Date Title
FR3098342B1 (fr) structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF
JP6089252B2 (ja) 無線周波数用途又は電力用途のための電子装置及びそのような装置を製造するためのプロセス
EP3227905B1 (fr) Structure pour applications radiofréquences
EP0801419B1 (fr) Procédé d'obtention d'un film mince de matériau semiconducteur comprenant notamment des composants électroniques
TWI259560B (en) Process for forming thick oxides on Si or SiC for semiconductor devices
JPH04154147A (ja) 半導体装置およびその製造方法
KR19990063519A (ko) 반도체물품의 에칭방법과 장치 및 이것을 사용한 반도체물품의 제조방법
CN112236853B (zh) 用于集成射频器件的衬底及其制造方法
FR2869457A1 (fr) Dispositif a semiconducteur du type a separation dielectrique
FR3062517A1 (fr) Structure pour application radiofrequence
EP1103072A1 (fr) Structure semiconductrice en couche mince comportant une couche de repartition de chaleur
JP7036043B2 (ja) 高抵抗材料の抵抗率測定方法
JP3054637B2 (ja) 集積回路のパッシベーション方法
CN112602267A (zh) 复合基板和复合基板的制造方法
CN106062922B (zh) 复合基板
JP5989559B2 (ja) 複合基板
FR2851079A1 (fr) Structure semi-conductrice sur substrat a forte rugosite
US4004046A (en) Method of fabricating thin monocrystalline semiconductive layer on an insulating substrate
US20020102863A1 (en) Sputtered insulating layer for wordline stacks
FR3091004B1 (fr) Structure de type semi-conducteur pour applications digitales et radiofréquences
EP1407486A2 (fr) Transistor et procede de fabrication d'un transistor sur un substrat sige/soi
JP3864886B2 (ja) Ｓｏｉウエーハ
JPS61144036A (ja) 半導体装置およびその製造方法
US7622362B2 (en) Method for manufacturing semiconductor device
JPS59178747A (ja) 半導体装置の製法

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20210108

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6