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FR3097076B1 - Prises de contact pour composant électronique - Google Patents

Prises de contact pour composant électronique Download PDF

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Publication number
FR3097076B1
FR3097076B1 FR1905958A FR1905958A FR3097076B1 FR 3097076 B1 FR3097076 B1 FR 3097076B1 FR 1905958 A FR1905958 A FR 1905958A FR 1905958 A FR1905958 A FR 1905958A FR 3097076 B1 FR3097076 B1 FR 3097076B1
Authority
FR
France
Prior art keywords
electronic component
region
contact sockets
semiconductor region
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1905958A
Other languages
English (en)
Other versions
FR3097076A1 (fr
Inventor
Julien Borrel
Magali Gregoire
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR1905958A priority Critical patent/FR3097076B1/fr
Priority to US16/892,732 priority patent/US11322363B2/en
Publication of FR3097076A1 publication Critical patent/FR3097076A1/fr
Application granted granted Critical
Publication of FR3097076B1 publication Critical patent/FR3097076B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Connecting Device With Holders (AREA)

Abstract

Prises de contact pour composant électronique La présente description concerne un procédé comprenant : a) l'implantation (300), dans une région semiconductrice (140), d'atomes à une concentration plus élevée dans une partie périphérique (310) que dans une partie centrale (320) ; b) la formation d'une région métallique recouvrant la région semiconductrice ; et c) la formation d'une région intermétallique à partir de la région métallique et de la région semiconductrice (140). Figure pour l'abrégé : Fig. 3
FR1905958A 2019-06-05 2019-06-05 Prises de contact pour composant électronique Active FR3097076B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1905958A FR3097076B1 (fr) 2019-06-05 2019-06-05 Prises de contact pour composant électronique
US16/892,732 US11322363B2 (en) 2019-06-05 2020-06-04 Contacts for electronic component

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1905958 2019-06-05
FR1905958A FR3097076B1 (fr) 2019-06-05 2019-06-05 Prises de contact pour composant électronique

Publications (2)

Publication Number Publication Date
FR3097076A1 FR3097076A1 (fr) 2020-12-11
FR3097076B1 true FR3097076B1 (fr) 2023-08-18

Family

ID=67875691

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1905958A Active FR3097076B1 (fr) 2019-06-05 2019-06-05 Prises de contact pour composant électronique

Country Status (2)

Country Link
US (1) US11322363B2 (fr)
FR (1) FR3097076B1 (fr)

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208472A (en) * 1988-05-13 1993-05-04 Industrial Technology Research Institute Double spacer salicide MOS device and method
US5177027A (en) * 1990-08-17 1993-01-05 Micron Technology, Inc. Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path
JP3514500B2 (ja) * 1994-01-28 2004-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US5624869A (en) * 1994-04-13 1997-04-29 International Business Machines Corporation Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen
JP2751895B2 (ja) * 1995-10-31 1998-05-18 日本電気株式会社 半導体装置の製造方法
US6010952A (en) * 1997-01-23 2000-01-04 Lsi Logic Corporation Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation
JP3684849B2 (ja) * 1997-06-17 2005-08-17 セイコーエプソン株式会社 Ｍｉｓ型電界効果トランジスタを含む半導体装置及びその製造方法
TW423056B (en) * 1997-11-21 2001-02-21 Taiwan Semiconductor Mfg Large-angled pre-amorphization implant technique for integrated circuit
US6204132B1 (en) * 1998-05-06 2001-03-20 Texas Instruments Incorporated Method of forming a silicide layer using an angled pre-amorphization implant
US6150243A (en) * 1998-11-05 2000-11-21 Advanced Micro Devices, Inc. Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer
US6255214B1 (en) * 1999-02-24 2001-07-03 Advanced Micro Devices, Inc. Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions
JP2001036080A (ja) * 1999-07-26 2001-02-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6297148B1 (en) * 1999-08-19 2001-10-02 Advanced Micro Devices, Inc. Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation
US6376342B1 (en) * 2000-09-27 2002-04-23 Vanguard International Semiconductor Corporation Method of forming a metal silicide layer on a source/drain region of a MOSFET device
US6765269B2 (en) * 2001-01-26 2004-07-20 Integrated Device Technology, Inc. Conformal surface silicide strap on spacer and method of making same
US6380057B1 (en) * 2001-02-13 2002-04-30 Advanced Micro Devices, Inc. Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant
US6589836B1 (en) * 2002-10-03 2003-07-08 Taiwan Semiconductor Manufacturing Company One step dual salicide formation for ultra shallow junction applications
US7105412B1 (en) * 2005-03-22 2006-09-12 United Microelectronics Corp. Silicide process utilizing pre-amorphization implant and second spacer
US7344985B2 (en) * 2005-04-01 2008-03-18 Texas Instruments Incorporated Nickel alloy silicide including indium and a method of manufacture therefor
US20060286757A1 (en) * 2005-06-15 2006-12-21 John Power Semiconductor product and method for forming a semiconductor product
JP5367340B2 (ja) * 2008-10-30 2013-12-11 株式会社東芝 半導体装置および半導体装置の製造方法
US8614134B2 (en) * 2011-03-21 2013-12-24 Globalfoundries Inc. Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation

Also Published As

Publication number Publication date
US20200388505A1 (en) 2020-12-10
FR3097076A1 (fr) 2020-12-11
US11322363B2 (en) 2022-05-03

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