FR3088437A1 - DURATION GENERATION CIRCUIT - Google Patents

Abstract

The present description relates to a circuit for generating a reference duration (30) of a critical path of an electronic device (10), comprising at least one memory cell (32-C).

Description

DESCRIPTION

TITLE: Duration generation circuit

Technical Field This description relates generally to electronic devices, and more particularly, memory arrays. The present description applies more particularly to the production of a circuit for monitoring a memory array.

PRIOR ART [0002] There are different methods for ensuring the proper functioning of an electronic device.

It would be desirable to be able to improve at least certain aspects of the monitoring circuits of electronic devices used.

Summary of the invention [0004] One embodiment overcomes all or part of the drawbacks of known monitoring circuits of an electronic device.

One embodiment provides a circuit for generating a reference duration of a critical path of an electronic device, comprising at least one memory cell.

According to one embodiment, the electronic device comprises at least one memory matrix.

According to one embodiment, said at least one memory cell is of the same type as the memory cells of the memory array of the electronic device.

According to one embodiment, the circuit is adapted to generate a reference signal from an input signal from the electronic device.

B17161 - 17-GR1-0742 [0009] According to one embodiment, said at least one memory cell is associated with logic circuits.

According to one embodiment, the logic circuits include at least one write circuit, at least one read circuit, and at least one bit line precharge circuit.

Another embodiment provides a circuit for monitoring a critical path of an electronic device comprising a generation circuit described above.

According to one embodiment, the circuit further comprises a comparator.

According to one embodiment, the comparator is adapted to compare an output signal from the electronic device to the reference signal.

According to one embodiment, the circuit is adapted to supply a control signal to the electronic device.

Another embodiment provides a method for monitoring a critical path of an electronic device, in which an output signal from the electronic device is compared to a reference signal generated by a duration generation circuit. reference comprising at least one memory cell.

According to one embodiment, the circuit for generating a reference duration is included in a monitoring circuit.

Brief description of the drawings These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:

B17161 - 17-GR1-0742 [0018] [Fig. 1] FIG. 1 represents a diagram, in the form of blocks, of an electronic system and of an embodiment of a circuit for monitoring a critical path;

[Fig. 2] FIG. 2 represents a diagram, in the form of blocks, of an embodiment of a circuit for generating a reference duration;

[Fig. 3] FIG. 3 represents a diagram, in the form of blocks, of another embodiment of a circuit for generating a reference duration; and [0021] [Fig. 4] FIG. 4 represents an electronic diagram of a reference memory cell associated with logic circuits.

Description of the embodiments The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the various embodiments may have the same references and may have identical structural, dimensional and material properties.

For clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

Unless otherwise specified, when reference is made to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when reference is made to two elements connected or coupled together, this means that these two elements can be connected or be linked or coupled via one or more other elements.

B17161 - 17-GR1-0742 Unless otherwise specified, the expressions approximately, approximately, substantially, and of the order of mean to the nearest 10%, preferably to the nearest 5%.

Figure 1 is a diagram, in the form of blocks, of an electronic device 10 and an embodiment of a monitoring circuit 20. In this embodiment, the circuit 20 is a monitoring circuit of a critical path of the device 10. In the following description, the critical path of a device is called the electrical path between an input and an output of the device which takes the longest time to be traveled by an applied signal. at the entrance.

The electronic device 10 is a device comprising different electronic circuits, for example memory arrays, logic circuits, supply circuits, etc. According to one embodiment, the electronic device 10 comprises, in its critical path, at least one memory array 12 (MEM). By way of example, the device 10 can also comprise, in its critical path, various other types of electronic circuits. The device 10 receives, at the input, a Sig-in signal, and supplies, at the output, a Sig-out signal. The device 10 also receives a control signal Sc.

The monitoring circuit 20 receives, at the input, the signal Sig-in, and possibly the signal Sig-out, and supplies, at the output, the control signal Sc. For example, the circuit 20 is included (on-board or integrated) in the device 10.

The monitoring circuit 20 includes:

a circuit 22 for generating a reference duration Dref; a comparator 24; and an analysis circuit 26.

B17161 - 17-GR1-0742 The circuit 22 for generating a reference duration Dref receives, at input, the signal Sig-in, and provides, at output, a reference signal Sig-Dref. The Sig-Dref signal is the Sig-in signal delayed by the reference duration Dref. The reference duration Dref corresponds to the theoretical delay of the critical path of the device 10, that is to say the delay estimated by a designer, taken by a signal passing through the critical path of the device 10. To generate the reference duration Dref , the circuit 22 is composed of one or more delay circuits, the sum of the delays imposed on a signal is equal to the reference duration Dref. The device 10 comprising at least one memory matrix in its critical path, the circuit 22 comprises at least one delay circuit adapted to simulate the delay that a signal takes while passing through a memory matrix.

According to one embodiment, the circuit 22 comprises one or more reference memory cells 22-MEM, associated with usual logic circuits (write, read circuit, etc.). Each reference memory cell 22-MEM is of the same type as the memory cells used in the memory array 12 (MEM) present in the critical path of the device 10.

More particularly, a reference memory cell is a memory cell used in a memory array to estimate the duration of a read or write operation on the memory cells used in the memory array.

A reference memory cell associated with usual logic circuits is generally called self-sequencing circuit (self time circuit). An example of a self-sequencing circuit will be described in relation to FIG. 4.

B17161 - 17-GR1-0742 As in a memory matrix, the 22-MEM reference memory cells make it possible to estimate the time of an operation on a memory cell and therefore to estimate the delay taken by a passing signal by one or more memory cells.

An advantage of using memory cells of the same type as those present in the critical path is that the reference duration Dref established by the circuit 22 is closer to the real delay taken by the signal Sig-out at the output of the device 10 compared to the Sig-in signal.

The circuit 22 may further include one or more other delay circuits without a reference memory cell, but for example various logic components. These other delay circuits can for example make it possible to estimate the delay that takes a signal passing through other circuits than memory arrays, included in the critical path of the device 10.

According to one embodiment, the circuit 22 for generating the reference duration Dref is a modular duration circuit, that is to say a circuit for which a designer and / or a user can adjust the duration of reference generated. For this, the reference duration generation circuit comprises one or more multiplexers adapted to select one or more delay circuits, to add their delays in order to obtain the desired reference duration Dref.

The comparator 24 receives the Sigout and Sig-Dref signals as input, and provides, at the output, a signal Comp for comparing the Sig-out and Sig-Dref signals.

The analysis circuit 26 receives, at the input, the comparison signal Comp, and supplies, at the output, the control signal Sc. The analysis circuit 26 is adapted to determine,

B17161 - 17-GR1-0742 from the Comp signal, if the device 10 has a malfunction. The analysis circuit 26 is, moreover, adapted to supply the control signal Sc which makes it possible to supply the device 10 with commands in relation to the malfunction or malfunctions detected from the signal Comp. By way of example, the control signal can trigger a reinitialization step or an erasure of the data of the device 10 in the event of detection of an attack on the circuit 10. According to an alternative embodiment, the analysis circuit 2 6 can be adapted to supply the control signal Sc to other electronic circuits, forming for example higher levels, of the device 10. Any usual analysis circuit is compatible with the embodiments described.

The operation of the monitoring circuit 20 is as follows. The monitoring circuit 20 generates, from the input signal Sig-in, the signal Sig-Dref delayed by the reference duration Dref. The signal Sig-Dref is then compared to the output signal Sig-out of the device 10. The comparison signal Comp is then studied by the analysis circuit 26 which generates a control signal Sc from its analysis.

According to another embodiment (shown in dotted lines in FIG. 1), the monitoring circuit 20 can receive as input only the signal Sig-in. In this case, a Sig-out-ref signal, clone of the Sig-out signal, is generated from, for example, a periodic shift register 22ref, (from the English Linear Feedback Shift Register) forming part of the circuit. monitoring device 20. The comparator 24 in this case compares the signal Sig-Dref and the signal Sig-Outref to provide the signal Comp.

Figure 2 is a diagram, in the form of blocks, of an embodiment of a circuit 30 for generating the reference duration Dref.

B17161 - 17-GR1-0742 The circuit 30 is an exemplary embodiment of the circuit 22 described in relation to FIG. 1. Thus, the circuit 30 receives, at input, the signal Sig-in, and supplies, at output , the reference signal Sig-Dref.

In Figure 2, the circuit 30 includes two delay circuits 31 and 32 with adjustable delay, connected in series.

The circuit 31 includes an input, receiving the Sig-in signal, and an output, providing an intermediate signal Sig-int3. The circuit 31 includes several delay elements 31-C (four delay elements are shown in FIG. 2) and a multiplexer 31-M. The elements 31-C are connected, for example connected, in series between the input of the circuit 31 and a multiplexer 31-M. By way of example, the delay elements are all identical and impose the same delay on a signal passing through them successively. As a variant, the delay elements are different and impose different delays on a signal passing through them successively. The 31-M multiplexer allows a number of delay elements to be selected. More particularly, the multiplexer 31-M comprises several inputs (five inputs in FIG. 2), each input being connected to an output of a delay element 31-C, with the exception of the first which receives the signal Sig-in. The 31-M multiplexer also receives a 31Comm control signal making it possible to choose the input of the 31-M multiplexer to be output. This makes it possible to pass the Sig-in signal only through a precise number of delay elements and therefore to choose the delay added by the circuit 31.

The circuit 32 includes an input, receiving the signal Sig-int3, and an output, providing the reference signal Sig-Dref. Circuit 32 includes several reference memory cells associated with logic circuits 32-C (three reference memory cells are represented in FIG. 2)

B17161 - 17-GR1-0742 and a 32-M multiplexer. The memory cells 32-C are connected, for example connected, in series between the input of the circuit 32 and a multiplexer 32-M. The 32-M multiplexer allows you to select a number of memory cells. More particularly, the multiplexer 32-M comprises several inputs (four inputs in FIG. 2), each input being connected to an output of a delay element 32-C, with the exception of the first which is connected to the output of the multiplexer 31-M. The 32-M multiplexer also receives a 32-Comm control signal making it possible to choose the input of the 32-M multiplexer to be output. This makes it possible to pass the Sig-in signal only through a precise number of delay elements and therefore to choose the delay imposed by the circuit 31.

Figure 3 is a diagram, in the form of blocks, of an embodiment of a circuit 40 for generating the reference duration Dref.

The circuit 40 is an exemplary embodiment of the circuit 22 described in relation to FIG. 1. Thus, the circuit 40 receives, at the input, the signal Sig-in, and supplies, at the output, the reference signal Sig- Ref.

In Figure 3, the circuit 40 comprises, between two switches (selectors) 41, 42, for example multiplexers, at least two sets 43, 44 of components adapted to delay a signal.

The switch 41 comprises for example two inputs, a first receiving the signal Sig-in and a second receiving an intermediate signal Sig-int4 from the switch 42, and at least two outputs connected to the inputs of the sets 43, 44 of components. The switch 41 also receives a control signal 41-Comm.

B17161 - 17-GR1-0742 The switch 42 includes at least two inputs connected to the outputs of the sets of components 43, 44, and for example two outputs, a first output providing the Sig-Dref signal, and a second output providing the signal Sig-int4 to one of the inputs of the switcher 41. The switcher 42 also receives a control signal 42-Comm.

The assembly 43 includes one or more electronic components 43-C (four components are shown in FIG. 3) connected, for example connected, in series between an output of the switch 41 and an input of the switch 42. For example, the components 43-C are all identical and impose the same delay on a signal passing through them successively, or, as a variant, the components 43-C are different from each other and impose different delays on a signal passing through them successively.

The assembly 44 includes one or more reference memory cells associated with logic circuits 44-C. The cells 44-C are connected, for example connected, in series between an output of the switch 41 and an input of the switch 42.

The operation of the circuit 40 is as follows. The switcher 41 is controlled by the signal 41-Comm to send the Sig-in signal to one of the sets 43, 44. The Sig-in signal is then delayed by the components 43-C, or 44-C. If the delay accumulated by the signal Sig-in is equal to Dref, the switcher 42 is controlled by the signal 42-Comm to supply the signal Sig-Dref. Otherwise the switcher 42 is controlled to supply the signal Sig-int4 to the switcher 41. The switcher 41 is then controlled by the signal 41-Comm to supply the signal Sig-int4 to one of the sets 43, 44, in order to '' increase its delay compared to the Sig-in signal. The signal Sig-int4 can for example pass several times in the

B17161 - 17-GR1-0742 different sets until its delay with respect to the Sig-in signal is equal to the reference duration Dref.

Figure 4 is an electrical diagram of a circuit 50 d ^{1 self-} sequencing of a reference memory cell associated with logic circuits.

The logic circuit 50 includes:

a precharge circuit 51;

a circuit 52 for charging a word line;

a circuit 53 for discharging the memory cell;

a circuit 54 for charging the memory cell;

a circuit 55 for reading the memory cell; and a bit line 56.

The precharge circuit 51 comprises for example a transistor 51T, for example a P-type MOS transistor. The source of the transistor 51T is connected, preferably connected, to a terminal receiving a supply potential VDD. The drain of transistor 51T is connected, preferably connected, to bit line 56. The gate of transistor 51T is connected, preferably connected, to a terminal receiving an input signal IN. The circuit 51 makes it possible to load a bit line 56 at the supply potential VDD when the input signal IN is at a low level.

The load circuit of the word line 52 comprises a transistor 52T, for example an N-type MOS transistor. The source and the drain of the transistor 52T are connected, preferably connected, to a terminal receiving the potential of VDD power supply. The gate of transistor 52T is connected, preferably connected, to the terminal receiving the signal IN. The circuit 52 makes it possible to load a word line associated with the memory cell.

The discharge circuit of the memory cell 53 includes two transistors 53T1 and 53T2, for example

B17161 - 17-GR1-0742 N-type MOS transistors. The source of transistor 53T2 is connected, preferably connected, to a terminal receiving a reference potential GND, for example ground. The drain of transistor 53T2 and the source of transistor 53T1 are connected, preferably connected, to each other. The gate of transistor 53T2 is connected, preferably connected, to a terminal receiving the supply potential VDD. The drain of transistor 53T1 is connected, preferably connected, to bit line 56. The gate of transistor 53T1 is connected, preferably connected, to the terminal receiving the input signal IN. The circuit 53 makes it possible to simulate a state at 0 of the reference memory cell by connecting the bit line to the reference potential when the input signal IN is at a high state.

According to another embodiment (not shown), the discharge circuit 53 may include a memory cell forced to produce a state at 0, by programming means included in the circuit 53, when the signal IN selects it.

The load circuit of the memory cell 54 comprises two transistors 54T1 and 54T2, for example MOS transistors of type N and P respectively. The drain of transistor 54T1 is connected, preferably connected, to bit line 56. The source of transistor 54T1 and the drain of transistor 54T2 are connected, preferably connected, to each other. The gate of transistor 54T1 is connected, preferably connected, to a terminal receiving the reference potential GND. The source of transistor 54T2 is connected, preferably connected, to a terminal receiving the supply potential VDD. The gate of transistor 54T2 is connected, preferably connected, to a terminal receiving the reference potential GND. The circuit 54 makes it possible to simulate a state at 1 of the reference memory cell by connecting the bit line to the supply potential when the input signal IN is at a state

B17161 - 17-GR1-0742 high. The circuit 50 generally comprises several circuits 54 making it possible to simulate a state at 1 of several memory cells connected in parallel to the reference memory cell. This makes it possible to simulate the leakage currents of these memory cells which can slow down the signals propagated by bit line 56.

According to another embodiment, the circuit 54 could include a memory cell forced to produce a state of 1, by programming means included in the circuit 54. These programming means are for example configured so that the memory cells produce a state at 1 low enough to produce a current of the same order of magnitude as a leakage current.

The circuits 53 and 54 can be assimilated to writing circuits. The read circuit 55 of the reference memory cell is an inverter circuit which makes it possible to adjust the voltage levels of the signal of the bit line to provide an output signal OUT.

One might have thought of testing various parameters of an electronic device to monitor its proper functioning. For this, we could have added sensors to monitor, in real time, said parameters. However, each parameter to be evaluated would in this case require a test circuit, or a sensor, and to embed these test circuits or these sensors in the electronic device would be expensive and / or bulky.

An advantage of the embodiments presented in relation to Figures 1 to 4 is that the device 10 comprises only a single monitoring circuit.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and

B17161 - 17-GR1-0742 variants could be combined, and other variants will be apparent to those skilled in the art. Reference memory cells may be added to other types of circuit for generating a reference duration.

Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims (12)

1. Circuit for generating a reference duration (22, 30, 40) of a critical path of an electronic device (10), comprising at least one memory cell (22-MEM, 32-C, 44C). 2. The circuit of claim 1, wherein the electronic device (10) comprises at least one memory array (12). 3. The circuit of claim 2, wherein said at least one memory cell (22-MEM, 32-C, 44-C) is of the same type as the memory cells of the memory array (12) of the electronic device (10) . 4. Circuit according to any one of claims 1 to 3, adapted to generate a reference signal (Sig-Dref) from an input signal (Sig-in) of the electronic device (10). 5. Circuit according to any one of claims 1 to 4, in which said at least one memory cell (22-MEM, 32-C, 44-C) is associated with logic circuits. 6. The circuit as claimed in claim 5, in which the logic circuits comprise at least one write circuit (53, 54), at least one read circuit (55), and at least one bit line precharge circuit. (51). 7. Monitoring circuit (20) of a critical path of an electronic device (10) comprising a generation circuit according to any one of claims 1 to 6. 8. The circuit of claim 7, further comprising a comparator (24). 9. The circuit of claims 8 in its attachment to claim 3, wherein the comparator (24) is B17161 - 17-GR1-0742 suitable for comparing an output signal (Sig-out) from the electronic device (10) with the reference signal (SigDref). 10. Circuit according to any one of claims 7 to 9, adapted to supply a control signal (Sc) to the electronic device (10). 11. Method for monitoring a critical path of an electronic device (10), in which an output signal (Sig-out) of the electronic device is compared with a reference signal (Sig-Dref) generated by a circuit generation of a reference duration (22, 30, 40) comprising at least one memory cell (22-MEM, 32-C, 44-C). 12. The method of claim 11, wherein the circuit for generating a reference duration (22, 30, 40) is included in a monitoring circuit (20).