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FR2999801B1 - Procede de fabrication d'une structure - Google Patents

Procede de fabrication d'une structure

Info

Publication number
FR2999801B1
FR2999801B1 FR1203428A FR1203428A FR2999801B1 FR 2999801 B1 FR2999801 B1 FR 2999801B1 FR 1203428 A FR1203428 A FR 1203428A FR 1203428 A FR1203428 A FR 1203428A FR 2999801 B1 FR2999801 B1 FR 2999801B1
Authority
FR
France
Prior art keywords
support substrate
interlayer
forming
substrate
donor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1203428A
Other languages
English (en)
Other versions
FR2999801A1 (fr
Inventor
Patrick Raynaud
Alexandre Chibko
Sylvain Peru
Isabelle Bertrand
Sothachett Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1203428A priority Critical patent/FR2999801B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to CN201380064142.8A priority patent/CN104871306B/zh
Priority to JP2015547155A priority patent/JP6354057B2/ja
Priority to EP13805521.5A priority patent/EP2932528B1/fr
Priority to PCT/IB2013/002692 priority patent/WO2014091285A1/fr
Priority to RU2015118945A priority patent/RU2607336C1/ru
Priority to US14/646,642 priority patent/US9653536B2/en
Priority to KR1020157015337A priority patent/KR102135644B1/ko
Priority to TW102146277A priority patent/TWI623037B/zh
Publication of FR2999801A1 publication Critical patent/FR2999801A1/fr
Application granted granted Critical
Publication of FR2999801B1 publication Critical patent/FR2999801B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Photovoltaic Devices (AREA)
  • Recrystallisation Techniques (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Ce procédé de fabrication d'une structure (3) comportant successivement un substrat support (2), une couche diélectrique (10), une couche active (11), une couche intercalaire (20) en silicium polycristallin, comporte les étapes : a) fournir un substrat donneur, b) former une zone de fragilisation dans le substrat donneur, c) fournir le substrat support (2), d) former la couche intercalaire (20) sur le substrat support (2), e) former la couche diélectrique (10), f) assembler le substrat donneur (1) et le substrat support (2), g) fracturer le substrat donneur (1) suivant la zone de fragilisation, h) soumettre la structure (3) à un recuit de renforcement d'au moins 10 minutes, le procédé de fabrication étant remarquable en ce que l'étape d) est exécutée de sorte que le silicium polycristallin de la couche intercalaire (20) présente une orientation de grains entièrement aléatoire, et en ce que le recuit de renforcement est exécuté à une température strictement supérieure à 950°C et inférieure à 1200°C.
FR1203428A 2012-12-14 2012-12-14 Procede de fabrication d'une structure Active FR2999801B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR1203428A FR2999801B1 (fr) 2012-12-14 2012-12-14 Procede de fabrication d'une structure
JP2015547155A JP6354057B2 (ja) 2012-12-14 2013-12-02 構造を作製するための方法
EP13805521.5A EP2932528B1 (fr) 2012-12-14 2013-12-02 Procédé de fabrication d'une structure
PCT/IB2013/002692 WO2014091285A1 (fr) 2012-12-14 2013-12-02 Procédé de fabrication d'une structure
CN201380064142.8A CN104871306B (zh) 2012-12-14 2013-12-02 用于制造结构的方法
RU2015118945A RU2607336C1 (ru) 2012-12-14 2013-12-02 Способ изготовления структуры
US14/646,642 US9653536B2 (en) 2012-12-14 2013-12-02 Method for fabricating a structure
KR1020157015337A KR102135644B1 (ko) 2012-12-14 2013-12-02 구조를 제조하기 위한 방법
TW102146277A TWI623037B (zh) 2012-12-14 2013-12-13 製造結構的方法及用於高頻應用之結構

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1203428A FR2999801B1 (fr) 2012-12-14 2012-12-14 Procede de fabrication d'une structure

Publications (2)

Publication Number Publication Date
FR2999801A1 FR2999801A1 (fr) 2014-06-20
FR2999801B1 true FR2999801B1 (fr) 2014-12-26

Family

ID=48050807

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1203428A Active FR2999801B1 (fr) 2012-12-14 2012-12-14 Procede de fabrication d'une structure

Country Status (9)

Country Link
US (1) US9653536B2 (fr)
EP (1) EP2932528B1 (fr)
JP (1) JP6354057B2 (fr)
KR (1) KR102135644B1 (fr)
CN (1) CN104871306B (fr)
FR (1) FR2999801B1 (fr)
RU (1) RU2607336C1 (fr)
TW (1) TWI623037B (fr)
WO (1) WO2014091285A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016081313A1 (fr) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited Procédé de fabrication de plaquettes de semi-conducteur sur isolant à haute résistivité comprenant couches de piégeage de charges
WO2016140850A1 (fr) * 2015-03-03 2016-09-09 Sunedison Semiconductor Limited Procédé pour déposer des films de silicium polycristallin de piégeage de charge sur des substrats de silicium avec une contrainte de film pouvant être maîtrisée
FR3048306B1 (fr) * 2016-02-26 2018-03-16 Soitec Support pour une structure semi-conductrice
FR3049763B1 (fr) * 2016-03-31 2018-03-16 Soitec Substrat semi-conducteur sur isolant pour applications rf
FR3074960B1 (fr) * 2017-12-07 2019-12-06 Soitec Procede de transfert d'une couche utilisant une structure demontable

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5080933A (en) * 1990-09-04 1992-01-14 Motorola, Inc. Selective deposition of polycrystalline silicon
JP2691244B2 (ja) * 1990-11-28 1997-12-17 株式会社日立製作所 誘電体分離基板
FR2773261B1 (fr) * 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
JP3484961B2 (ja) * 1997-12-26 2004-01-06 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
US6368938B1 (en) * 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
US20090325362A1 (en) 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
FR2892228B1 (fr) 2005-10-18 2008-01-25 Soitec Silicon On Insulator Procede de recyclage d'une plaquette donneuse epitaxiee
US7005160B2 (en) * 2003-04-24 2006-02-28 Asm America, Inc. Methods for depositing polycrystalline films with engineered grain structures
EP1665367A2 (fr) * 2003-09-26 2006-06-07 Universite Catholique De Louvain Procede de fabrication d'une structure semiconductrice multicouche a pertes ohmiques reduites
WO2005120775A1 (fr) 2004-06-08 2005-12-22 S.O.I. Tec Silicon On Insulator Technologies Planarisation d'une couche heteroepitaxiale
DE602005025534D1 (fr) 2005-01-31 2011-02-03 Freescale Semiconductor Inc
JP4934966B2 (ja) * 2005-02-04 2012-05-23 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
KR101470814B1 (ko) * 2006-01-20 2014-12-09 에이엠지 아이디얼캐스트 솔라 코포레이션 광전 변환 소자용 단결정 캐스트 실리콘 및 단결정 캐스트 실리콘 바디들을 제조하는 방법 및 장치
EP1835533B1 (fr) 2006-03-14 2020-06-03 Soitec Méthode de fabrication de plaquettes composites et procédé de recyclage d'un substrat donneur usagé
DE602006000423T2 (de) 2006-03-31 2008-05-21 S.O.I.Tec. Silicon On Insulator Technologies S.A. Verfahren zur Herstellung eines Verbundmaterials und Verfahren zur Auswahl eines Wafers
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FR2953640B1 (fr) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
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FR2977974B1 (fr) 2011-07-13 2014-03-07 Soitec Silicon On Insulator Procede de mesure de defauts dans un substrat de silicium
FR2987682B1 (fr) 2012-03-05 2014-11-21 Soitec Silicon On Insulator Procede de test d'une structure semi-conducteur sur isolant et application dudit test pour la fabrication d'une telle structure

Also Published As

Publication number Publication date
RU2607336C1 (ru) 2017-01-10
JP2016506619A (ja) 2016-03-03
KR20150093696A (ko) 2015-08-18
EP2932528A1 (fr) 2015-10-21
TW201436038A (zh) 2014-09-16
WO2014091285A1 (fr) 2014-06-19
FR2999801A1 (fr) 2014-06-20
TWI623037B (zh) 2018-05-01
US9653536B2 (en) 2017-05-16
EP2932528B1 (fr) 2021-03-24
CN104871306A (zh) 2015-08-26
JP6354057B2 (ja) 2018-07-11
CN104871306B (zh) 2018-07-24
KR102135644B1 (ko) 2020-07-20
US20150303247A1 (en) 2015-10-22

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