[go: up one dir, main page]

FR2987937B1 - Procede de realisation de plaquettes semi-conductrices - Google Patents

Procede de realisation de plaquettes semi-conductrices

Info

Publication number
FR2987937B1
FR2987937B1 FR1200753A FR1200753A FR2987937B1 FR 2987937 B1 FR2987937 B1 FR 2987937B1 FR 1200753 A FR1200753 A FR 1200753A FR 1200753 A FR1200753 A FR 1200753A FR 2987937 B1 FR2987937 B1 FR 2987937B1
Authority
FR
France
Prior art keywords
semiconductor wafers
making semiconductor
making
wafers
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1200753A
Other languages
English (en)
Other versions
FR2987937A1 (fr
Inventor
Julien Vitiello
Jean Luc Delcarri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kobus SAS
Original Assignee
Altatech Semiconductor SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1200753A priority Critical patent/FR2987937B1/fr
Application filed by Altatech Semiconductor SAS filed Critical Altatech Semiconductor SAS
Priority to CN201380013617.0A priority patent/CN104247004A/zh
Priority to KR1020147028221A priority patent/KR20150013445A/ko
Priority to US14/382,731 priority patent/US20150031202A1/en
Priority to DE112013001383.5T priority patent/DE112013001383T5/de
Priority to SG11201405664PA priority patent/SG11201405664PA/en
Priority to PCT/FR2013/050491 priority patent/WO2013135999A1/fr
Publication of FR2987937A1 publication Critical patent/FR2987937A1/fr
Application granted granted Critical
Publication of FR2987937B1 publication Critical patent/FR2987937B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR1200753A 2012-03-12 2012-03-12 Procede de realisation de plaquettes semi-conductrices Active FR2987937B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR1200753A FR2987937B1 (fr) 2012-03-12 2012-03-12 Procede de realisation de plaquettes semi-conductrices
KR1020147028221A KR20150013445A (ko) 2012-03-12 2013-03-08 반도체 웨이퍼들을 제조하기 위한 방법
US14/382,731 US20150031202A1 (en) 2012-03-12 2013-03-08 Method for manufacturing semiconductor wafers
DE112013001383.5T DE112013001383T5 (de) 2012-03-12 2013-03-08 Verfahren zur Herstellung von Halbleiterwafern
CN201380013617.0A CN104247004A (zh) 2012-03-12 2013-03-08 半导体晶片的制作方法
SG11201405664PA SG11201405664PA (en) 2012-03-12 2013-03-08 Method for manufacturing semiconductor wafers
PCT/FR2013/050491 WO2013135999A1 (fr) 2012-03-12 2013-03-08 Procédé de réalisation de plaquettes semi-conductrices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1200753A FR2987937B1 (fr) 2012-03-12 2012-03-12 Procede de realisation de plaquettes semi-conductrices

Publications (2)

Publication Number Publication Date
FR2987937A1 FR2987937A1 (fr) 2013-09-13
FR2987937B1 true FR2987937B1 (fr) 2014-03-28

Family

ID=47002907

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1200753A Active FR2987937B1 (fr) 2012-03-12 2012-03-12 Procede de realisation de plaquettes semi-conductrices

Country Status (7)

Country Link
US (1) US20150031202A1 (fr)
KR (1) KR20150013445A (fr)
CN (1) CN104247004A (fr)
DE (1) DE112013001383T5 (fr)
FR (1) FR2987937B1 (fr)
SG (1) SG11201405664PA (fr)
WO (1) WO2013135999A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140267A (zh) * 2015-07-29 2015-12-09 浙江大学 半导体衬底及选择性生长半导体的方法
US10096516B1 (en) * 2017-08-18 2018-10-09 Applied Materials, Inc. Method of forming a barrier layer for through via applications
DE102019006097A1 (de) * 2019-08-29 2021-03-04 Azur Space Solar Power Gmbh Passivierungsverfahren für ein Durchgangsloch einer Halbleiterscheibe
US11289370B2 (en) 2020-03-02 2022-03-29 Nanya Technology Corporation Liner for through-silicon via

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5807785A (en) * 1996-08-02 1998-09-15 Applied Materials, Inc. Low dielectric constant silicon dioxide sandwich layer
US6114216A (en) * 1996-11-13 2000-09-05 Applied Materials, Inc. Methods for shallow trench isolation
US20050136684A1 (en) 2003-12-23 2005-06-23 Applied Materials, Inc. Gap-fill techniques
JP4376715B2 (ja) * 2004-07-16 2009-12-02 三洋電機株式会社 半導体装置の製造方法
US7429529B2 (en) * 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
JP2010515275A (ja) * 2006-12-29 2010-05-06 キューファー アセット リミテッド. エル.エル.シー. スルーチップ接続を有するフロントエンドプロセス済ウェハ
KR100840665B1 (ko) * 2007-05-18 2008-06-24 주식회사 동부하이텍 반도체 소자의 제조방법 및 이를 이용한 시스템 인 패키지
CN101728283A (zh) * 2008-10-16 2010-06-09 上海华虹Nec电子有限公司 芯片互联工艺中芯片互联通孔的制备方法
CN102054752A (zh) * 2009-11-03 2011-05-11 中芯国际集成电路制造(上海)有限公司 硅通孔制作方法
US20120015113A1 (en) * 2010-07-13 2012-01-19 Applied Materials, Inc. Methods for forming low stress dielectric films
FR2963024B1 (fr) 2010-07-26 2016-12-23 Altatech Semiconductor Reacteur de depot chimique en phase gazeuse ameliore
US8487410B2 (en) * 2011-04-13 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias for semicondcutor substrate and method of manufacture

Also Published As

Publication number Publication date
FR2987937A1 (fr) 2013-09-13
KR20150013445A (ko) 2015-02-05
CN104247004A (zh) 2014-12-24
SG11201405664PA (en) 2014-10-30
DE112013001383T5 (de) 2014-11-27
WO2013135999A1 (fr) 2013-09-19
US20150031202A1 (en) 2015-01-29

Similar Documents

Publication Publication Date Title
EP3018696B8 (fr) Procédé de fabrication d'un substrat semi-conducteur
EP2790209A4 (fr) Procédé de fabrication pour dispositif à semi-conducteurs
EP2978018A4 (fr) Procédé de fabrication d'un substrat de module de puissance
FR2981341B1 (fr) Procede de fabrication de xerogels
EP2717300A4 (fr) Dispositif à semi-conducteurs
EP2613351A4 (fr) Modules semi-conducteurs
EP2613350A4 (fr) Modules semi-conducteurs
TWI563540B (en) Semiconductor device manufacturing method
TWI562366B (en) Manufacturing method of semiconductor device
JP2012134470A5 (ja) 半導体装置
EP2725623A4 (fr) Dispositif à semi-conducteur
EP2966679A4 (fr) Procédé de fabrication de substrat de module de puissance
EP2736067A4 (fr) Procédé de fabrication de dispositif à semi-conducteur
SG11201406661YA (en) Method for manufacturing bonded wafer
SG11201502119TA (en) Method for manufacturing soi wafer
FR2998290B1 (fr) Procede de potabilisation
SG11201501873QA (en) Method for manufacturing soi wafer
HK1158825A1 (zh) 半導體管芯切單方法
FR2995231B1 (fr) Procede de trefilage
FR2995135B1 (fr) Procede de realisation de transistors fet
EP2821133A4 (fr) Procédé de fabrication de microparticules
EP2690558A4 (fr) Dispositif à semi-conducteur
FR2987937B1 (fr) Procede de realisation de plaquettes semi-conductrices
FI20125179L (fi) Menetelmä kelluttamiseksi
FR2960094B1 (fr) Procede de fabrication de puces semiconductrices

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

CA Change of address

Effective date: 20180330

CD Change of name or company name

Owner name: UNITY SEMICONDUCTOR, FR

Effective date: 20180330

TP Transmission of property

Owner name: KOBUS SAS, FR

Effective date: 20180720

PLFP Fee payment

Year of fee payment: 9

PLFP Fee payment

Year of fee payment: 10

PLFP Fee payment

Year of fee payment: 11

PLFP Fee payment

Year of fee payment: 12

PLFP Fee payment

Year of fee payment: 13