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FR2965645B1 - Methode de test pour dispositifs electroniques integres a semi-conducteur et architecture de test correspondante - Google Patents

Methode de test pour dispositifs electroniques integres a semi-conducteur et architecture de test correspondante

Info

Publication number
FR2965645B1
FR2965645B1 FR1058043A FR1058043A FR2965645B1 FR 2965645 B1 FR2965645 B1 FR 2965645B1 FR 1058043 A FR1058043 A FR 1058043A FR 1058043 A FR1058043 A FR 1058043A FR 2965645 B1 FR2965645 B1 FR 2965645B1
Authority
FR
France
Prior art keywords
electronic devices
semiconductor integrated
integrated electronic
test method
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1058043A
Other languages
English (en)
Other versions
FR2965645A1 (fr
Inventor
Alberto Pagani
Jean-Michel Bard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
STMicroelectronics SRL
Original Assignee
STMicroelectronics Grenoble 2 SAS
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS, STMicroelectronics SRL filed Critical STMicroelectronics Grenoble 2 SAS
Priority to FR1058043A priority Critical patent/FR2965645B1/fr
Priority to US13/252,895 priority patent/US8829931B2/en
Publication of FR2965645A1 publication Critical patent/FR2965645A1/fr
Application granted granted Critical
Publication of FR2965645B1 publication Critical patent/FR2965645B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR1058043A 2010-10-05 2010-10-05 Methode de test pour dispositifs electroniques integres a semi-conducteur et architecture de test correspondante Expired - Fee Related FR2965645B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1058043A FR2965645B1 (fr) 2010-10-05 2010-10-05 Methode de test pour dispositifs electroniques integres a semi-conducteur et architecture de test correspondante
US13/252,895 US8829931B2 (en) 2010-10-05 2011-10-04 Testing method for semiconductor integrated electronic devices and corresponding test architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1058043A FR2965645B1 (fr) 2010-10-05 2010-10-05 Methode de test pour dispositifs electroniques integres a semi-conducteur et architecture de test correspondante

Publications (2)

Publication Number Publication Date
FR2965645A1 FR2965645A1 (fr) 2012-04-06
FR2965645B1 true FR2965645B1 (fr) 2012-10-12

Family

ID=43827355

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1058043A Expired - Fee Related FR2965645B1 (fr) 2010-10-05 2010-10-05 Methode de test pour dispositifs electroniques integres a semi-conducteur et architecture de test correspondante

Country Status (2)

Country Link
US (1) US8829931B2 (fr)
FR (1) FR2965645B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8343781B2 (en) * 2010-09-21 2013-01-01 International Business Machines Corporation Electrical mask inspection
US9134357B1 (en) * 2011-03-25 2015-09-15 Maxim Integrated, Inc. Universal direct docking at probe test
KR101910933B1 (ko) * 2011-12-21 2018-10-24 에스케이하이닉스 주식회사 반도체 집적회로 및 그의 테스트 제어방법
DE102013217093A1 (de) * 2013-08-28 2015-03-05 Robert Bosch Gmbh Verfahren zum Anpassen der Parameter eines Reglers für mikromechanische Aktoren und Vorrichtungen
US10838002B2 (en) * 2017-10-30 2020-11-17 Indium Corporation Burn-in preform and method of making the same
KR20190066482A (ko) * 2017-12-05 2019-06-13 삼성전자주식회사 인터포저를 사용하는 번 인 테스트 장치 및 테스트 방법
US12253564B2 (en) * 2023-03-17 2025-03-18 Silicon Motion, Inc. Mechanism capable of performing on-chip test and verification

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5968149A (en) * 1998-01-07 1999-10-19 International Business Machines Corporation Tandem operation of input/output data compression modules
US6624761B2 (en) * 1998-12-11 2003-09-23 Realtime Data, Llc Content independent data compression method and system
US6829737B1 (en) * 2000-08-30 2004-12-07 Micron Technology, Inc. Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results
US7119567B2 (en) * 2002-09-12 2006-10-10 Infineon Technologies North America Corp. System and method for testing one or more dies on a semiconductor wafer
US7181663B2 (en) * 2004-03-01 2007-02-20 Verigy Pte, Ltd. Wireless no-touch testing of integrated circuits
US7327153B2 (en) * 2005-11-02 2008-02-05 Texas Instruments Incorporated Analog built-in self-test module
US7405586B2 (en) * 2006-03-20 2008-07-29 Intel Corporation Ultra low pin count interface for die testing
US7888955B2 (en) * 2007-09-25 2011-02-15 Formfactor, Inc. Method and apparatus for testing devices using serially controlled resources
IT1392071B1 (it) * 2008-11-27 2012-02-09 St Microelectronics Srl Metodo per eseguire un testing elettrico di dispositivi elettronici

Also Published As

Publication number Publication date
US20120081137A1 (en) 2012-04-05
US8829931B2 (en) 2014-09-09
FR2965645A1 (fr) 2012-04-06

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Legal Events

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Effective date: 20150630