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FR2963985A1 - Gallium nitride vertical Schottky diode, has heavily doped p-type and n-type gallium nitride guard rings respectively provided at peripheries of electrode and lightly doped layer, where electrode is arranged on lightly doped layer - Google Patents

Gallium nitride vertical Schottky diode, has heavily doped p-type and n-type gallium nitride guard rings respectively provided at peripheries of electrode and lightly doped layer, where electrode is arranged on lightly doped layer Download PDF

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FR2963985A1
FR2963985A1 FR1056654A FR1056654A FR2963985A1 FR 2963985 A1 FR2963985 A1 FR 2963985A1 FR 1056654 A FR1056654 A FR 1056654A FR 1056654 A FR1056654 A FR 1056654A FR 2963985 A1 FR2963985 A1 FR 2963985A1
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layer
type
doped
lightly doped
gan
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Daniel Alquier
Arnaud Yvon
Yvon Cordier
Eric Frayssinet
Mark Allen Kennard
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Centre National de la Recherche Scientifique CNRS
Soitec SA
STMicroelectronics Tours SAS
Universite de Tours
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Centre National de la Recherche Scientifique CNRS
Soitec SA
Universite Francois Rabelais de Tours
STMicroelectronics Tours SAS
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Priority to FR1056654A priority Critical patent/FR2963985A1/en
Publication of FR2963985A1 publication Critical patent/FR2963985A1/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/01Manufacture or treatment
    • H10D8/051Manufacture or treatment of Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne une diode Schottky verticale comprenant successivement, sur un substrat conducteur (20), une couche (14) de GaN fortement dopée de type N ; une couche (13) de GaN faiblement dopée de type N ; un contact Schottky (22) sur la couche de GaN faiblement dopée de type N.The invention relates to a vertical Schottky diode comprising successively, on a conductive substrate (20), a layer (14) of strongly doped GaN type N; a layer (13) of lightly doped GaN type N; a Schottky contact (22) on the lightly doped N-type GaN layer.

Description

B9707 - 09-T0-222 1 DIODE SCHOTTKY VERTICALE AU NITRURE DE GALLIUM Domaine de l'invention La présente invention concerne une diode Schottky comprenant un contact Schottky entre une couche de nitrure de gallium (GaN) et une couche métallique. FIELD OF THE INVENTION The present invention relates to a Schottky diode comprising a Schottky contact between a layer of gallium nitride (GaN) and a metal layer.

Exposé de l'art antérieur Les diodes Schottky au nitrure de gallium présentent des qualités intéressantes notamment du fait que leur tension de claquage en inverse est très élevée (de l'ordre de 600 volts pour moins de 10 }gym d'épaisseur) et que leur chute de tension en direct est particulièrement faible, inférieure à 2 V pour une surface active inférieure à 4 mm2 et pour des courants de 4 à 8 A. La figure 1 est une vue en coupe destinée à illustrer un procédé classique de fabrication d'une diode Schottky au nitrure de gallium. Pour cela, on part d'un substrat cristallin 1, par exemple en saphir (Al203), en silicium ou en carbure de silicium. Sur ce substrat, pour obtenir un accord de maille avec du GaN, il faut prévoir une couche tampon intermédiaire 2, par exemple en nitrure de silicium, en nitrure d'aluminium ou en nitrure de gallium. Sur la couche tampon intermédiaire 2, on fait croître par épitaxie une couche de GaN 3 fortement dopée de type N (N+) puis une couche de nitrure de gallium 4 faiblement B9707 - 09-T0-222 BACKGROUND OF THE PRIOR ART Schottky diodes with gallium nitride have interesting qualities, in particular because their reverse breakdown voltage is very high (of the order of 600 volts for less than 10 g / cm thick) and their direct voltage drop is particularly low, less than 2 V for an active surface area less than 4 mm 2 and for currents of 4 to 8 A. Figure 1 is a sectional view intended to illustrate a conventional method of manufacturing a Schottky diode with gallium nitride. For this, we start from a crystalline substrate 1, for example sapphire (Al203), silicon or silicon carbide. On this substrate, to obtain a mesh with GaN, it is necessary to provide an intermediate buffer layer 2, for example silicon nitride, aluminum nitride or gallium nitride. On the intermediate buffer layer 2, epitaxially grown a layer of GaN 3 strongly doped N (N +) then a layer of gallium nitride 4 weakly B9707 - 09-T0-222

2 dopée de type N pour obtenir un contact Schottky avec une couche supérieure 5, par exemple en tungstène, titane-tungstène, nitrure de tungstène, nitrure de titane, nickel, or, nickel-or, platine, platine-or, platine-nickel... 2 doped N-type to obtain a Schottky contact with an upper layer 5, for example tungsten, titanium-tungsten, tungsten nitride, titanium nitride, nickel, gold, nickel-gold, platinum, platinum-gold, platinum-nickel ...

Il se pose un problème du fait qu'il résulte de ce procédé de fabrication l'existence d'une couche tampon isolante 2 entre le substrat 1 et la structure de diode Schottky. Cette couche tampon est isolante et interdit la réalisation d'une diode verticale entre le substrat 1 et le contact Schottky 5. A problem arises because it results from this manufacturing process the existence of an insulating buffer layer 2 between the substrate 1 and the Schottky diode structure. This buffer layer is insulating and prohibits the production of a vertical diode between the substrate 1 and the Schottky contact 5.

Les figures 2A et 2B illustrent deux modes de réalisation de diodes Schottky obtenues à partir de la structure décrite en figure 1. Dans les figures 2A et 2B, de mêmes éléments sont désignés par de mêmes références qu'en figure 1. La figure 2A représente une structure de diode Schottky de type mesa. La surface de la couche 4 faiblement dopée de type N au-dessus de la couche 3 fortement dopée de type N est limitée de sorte qu'une partie périphérique de la couche 3 est apparente et qu'il est possible d'y placer une deuxième électrode 6. Pour obtenir une couche de GaN 4 d'étendue limitée, il faut ou bien procéder à une épitaxie sélective au-dessus d'une partie non masquée de la couche 3, ou bien graver la couche 4 après sa formation. Un inconvénient de cette structure réside dans sa difficulté de fabrication. FIGS. 2A and 2B illustrate two embodiments of Schottky diodes obtained from the structure described in FIG. 1. In FIGS. 2A and 2B, the same elements are designated with the same references as in FIG. 1. FIG. a Schottky diode structure of mesa type. The surface of the lightly doped N-type layer 4 above the heavily doped N-type layer 3 is limited so that a peripheral portion of the layer 3 is apparent and a second layer can be placed therein. electrode 6. To obtain a layer of GaN 4 of limited extent, it is necessary either to carry out a selective epitaxy over an unmasked part of the layer 3, or to etch the layer 4 after its formation. A disadvantage of this structure lies in its difficulty of manufacture.

Un autre inconvénient est qu'une telle diode n'est pas une diode verticale et que sa chute de tension en direct n'est donc pas minimale pour une surface de puce donnée. La figure 2B représente une autre structure possible dans laquelle, après fabrication d'une diode par le procédé illustré en figure 1, on perce des ouvertures à partir de la face arrière, ces ouvertures traversant tout le substrat 1 et la couche tampon 2 pour déboucher dans la couche 3 de GaN fortement dopée de type N. Ces ouvertures sont ensuite remplies d'un matériau conducteur 7. Une métallisation de face arrière 8 est en contact avec ce matériau conducteur 7. Another disadvantage is that such a diode is not a vertical diode and therefore its live voltage drop is not minimal for a given chip area. FIG. 2B shows another possible structure in which, after manufacture of a diode by the method illustrated in FIG. 1, apertures are pierced from the rear face, these openings passing through all the substrate 1 and the buffer layer 2 to unblock in the layer 3 of heavily doped GaN type N. These openings are then filled with a conductive material 7. A rear face metallization 8 is in contact with this conductive material 7.

B9707 - 09-T0-222 B9707 - 09-T0-222

3 Ce type de structure présente l'inconvénient d'avoir un procédé de fabrication particulièrement complexe et ne constitue pas réellement une diode verticale. Il existe donc un besoin pour une diode Schottky au 5 nitrure de gallium à fonctionnement réellement vertical. Résumé C'est un objet d'un mode de réalisation de la présente invention que de prévoir une telle diode Schottky au nitrure de gallium qui soit verticale et ne présente pas au moins certains 10 des inconvénients des dispositifs de l'art antérieur. Résumé Ainsi, un mode de réalisation de la présente invention prévoit une diode Schottky verticale comprenant successivement, sur un substrat conducteur, une couche de GaN fortement dopée de 15 type N ; une couche de GaN faiblement dopée de type N ; un contact Schottky sur la couche de GaN faiblement dopée de type N. Selon un mode de réalisation de la présente invention, le substrat conducteur comprend un substrat de silicium forte- 20 ment dopé revêtu d'une couche métallique à l'interface avec la couche fortement dopée de type N de GaN. Selon un mode de réalisation de la présente invention, le contact Schottky sur la couche de GaN faiblement dopée de type N est localisé. 25 Selon un mode de réalisation de la présente invention, la périphérie de la région de contact Schottky est entourée d'un anneau de garde fortement dopé de type P dans la couche de GaN. Selon un mode de réalisation de la présente invention, la périphérie extérieure de la couche de GaN faiblement dopée de 30 type N comprend un anneau d'arrêt de canal fortement dopé de type N. La présente invention prévoit aussi un procédé de fabrication d'une diode Schottky verticale, comprenant les étapes suivantes : 35 former sur un premier substrat une couche tampon ; B9707 - 09-T0-222 This type of structure has the disadvantage of having a particularly complex manufacturing process and does not actually constitute a vertical diode. There is therefore a need for a gallium nitride Schottky diode with truly vertical operation. SUMMARY It is an object of one embodiment of the present invention to provide such a gallium nitride Schottky diode that is vertical and does not exhibit at least some of the disadvantages of the prior art devices. Thus, an embodiment of the present invention provides a vertical Schottky diode comprising successively, on a conductive substrate, a N-type heavily doped GaN layer; a lightly doped N type GaN layer; A Schottky contact on the N-type lightly doped GaN layer. According to one embodiment of the present invention, the conductive substrate comprises a highly doped silicon substrate coated with a metal layer at the interface with the layer. strongly doped type N GaN. According to one embodiment of the present invention, the Schottky contact on the N-type lightly doped GaN layer is located. According to one embodiment of the present invention, the periphery of the Schottky contact region is surrounded by a heavily doped P-type guard ring in the GaN layer. According to one embodiment of the present invention, the outer periphery of the N-type lightly doped GaN layer comprises a heavily doped N-type channel stop ring. The present invention also provides a method of manufacturing a vertical Schottky diode, comprising the steps of: forming on a first substrate a buffer layer; B9707 - 09-T0-222

4 faire croître sur la couche tampon une couche de GaN faiblement dopée de type N ; faire croître sur la couche faiblement dopée une couche de GaN fortement dopée de type N ; assembler la structure obtenue avec un deuxième substrat fortement conducteur, du côté de la couche fortement dopée de type N ; éliminer le premier substrat et la couche tampon ; former un contact Schottky sur la couche faiblement 10 dopée de type N. Brève description des dessins Ces objets, caractéristiques et avantages, ainsi que d'autres seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif 15 en relation avec les figures jointes parmi lesquelles : la figure 1 est une vue en coupe destinée à illustrer un procédé de fabrication d'une structure Schottky au nitrure de gallium selon l'art antérieur ; les figures 2A et 2B sont des vues en coupe représen-20 tant deux exemples de réalisation de diodes Schottky selon l'art antérieur ; les figures 3A et 3B illustrent deux étapes de fabrication d'une diode Schottky au nitrure de gallium selon un mode de réalisation de la présente invention ; et 25 les figures 4 et 5 sont des vues en coupe illustrant deux exemples de réalisation de diodes Schottky selon des modes de réalisation de la présente invention. Par souci de clarté, de mêmes parties ou éléments ont été désignés par de mêmes références aux différentes figures et, 30 de plus, comme cela est habituel dans la représentation des circuits microélectroniques, les diverses figures ne sont pas tracées à l'échelle. Description détaillée La figure 3A représente une première étape de fabrica-35 tion d'une diode Schottky au nitrure de gallium selon un mode de B9707 - 09-T0-222 4 growing on the buffer layer a lightly doped N-type GaN layer; growing on the lightly doped layer a strongly doped N-type GaN layer; assembling the resulting structure with a second, highly conductive substrate on the side of the heavily doped N-type layer; removing the first substrate and the buffer layer; A brief description of the drawings. These and other objects, features, and advantages will be discussed in detail in the following description of particular non-limiting embodiments. in relation to the attached figures among which: Figure 1 is a sectional view for illustrating a method of manufacturing a Schottky gallium nitride structure according to the prior art; FIGS. 2A and 2B are cross-sectional views showing two exemplary embodiments of Schottky diodes according to the prior art; FIGS. 3A and 3B illustrate two steps of manufacturing a gallium nitride Schottky diode according to one embodiment of the present invention; and Figures 4 and 5 are sectional views illustrating two exemplary embodiments of Schottky diodes according to embodiments of the present invention. For the sake of clarity, the same parts or elements have been designated with the same references in the various figures and, moreover, as is customary in the representation of the microelectronic circuits, the various figures are not drawn to scale. DETAILED DESCRIPTION FIG. 3A represents a first step of fabricating a gallium nitride Schottky diode in a B9707-09-T0-222 mode.

réalisation de la présente invention. On commence par réaliser une première tranche W1 comprenant un substrat 11, par exemple en saphir (Al2O3), en silicium ou en carbure de silicium revêtu d'une couche tampon 12, par exemple en SiN, A1N, GaN, AlGaN. Sur 5 cette couche tampon, on fait croître une couche de nitrure de gallium 13 faiblement dopée de type N puis une couche de nitrure de gallium 14 fortement dopée de type N. On notera que l'ordre de formation des couches 13 et 14 est inversé par rapport à l'ordre des couches 3 et 4 de la figure 1. On réalise ensuite une deuxième tranche W2 destinée à être accolée à la surface supérieure de la tranche W1. Cette tranche W2 est en un matériau conducteur, par exemple une tranche de silicium 20 fortement dopée. Eventuellement, on forme sur la surface supérieure de la couche de GaN(N+) 14 une couche conductrice d'accrochage, par exemple une couche métallique 15. Ensuite, on accole les tranches W1 et W2 et on élimine le substrat 11 et la couche tampon 13 pour obtenir la structure illustrée en figure 3B. Il reste alors à former un contact Schottky sur la surface apparente de la couche de GaN faiblement dopée 13 et éventuellement également un contact sur la face apparente de la tranche très conductrice 20. On obtient ainsi, après retournement, la structure représentée en figure 4 dans laquelle l'électrode Schottky 22 est localisée par un dépôt antérieur d'une couche isolante 23, par exemple en oxyde (USG, PSG, BSG, BPSG, TEOS, ou autre). On a ainsi obtenu une diode Schottky complètement verticale entre la métallisation 22 et un contact de face arrière 24. A titre d'exemple, et sans que cela soit limitatif : - la tranche de silicium 20 pourra avoir une épaisseur finale de 100 à 300 }gym, - la couche métallique optionnelle 15 pourra être en tungstène et avoir une épaisseur de 50 à 500 nm, par exemple de l'ordre de 0,2 }gym, B9707 - 09-T0-222 embodiment of the present invention. Firstly, a first wafer W1 comprising a substrate 11, for example sapphire (Al2O3), silicon or silicon carbide coated with a buffer layer 12, for example SiN, AlN, GaN, AlGaN, is produced. On this buffer layer, a N-type lightly doped gallium nitride layer 13 is grown followed by a heavily doped N-type gallium nitride layer 14. It will be noted that the formation order of the layers 13 and 14 is reversed. relative to the order of the layers 3 and 4 of FIG. 1. A second wafer W2 is then produced intended to be contiguous to the upper surface of the wafer W1. This wafer W2 is made of a conductive material, for example a heavily doped silicon wafer. Optionally, on the upper surface of the GaN (N +) layer 14, a conductive bonding layer is formed, for example a metal layer 15. Next, the W1 and W2 wafers are bonded together and the substrate 11 and the buffer layer are removed. 13 to obtain the structure illustrated in FIG. 3B. It then remains to form a Schottky contact on the apparent surface of the lightly doped GaN layer 13 and possibly also a contact on the apparent face of the highly conductive wafer 20. Thus, after turning, the structure shown in FIG. wherein the Schottky electrode 22 is located by an anterior deposition of an insulating layer 23, for example oxide (USG, PSG, BSG, BPSG, TEOS, or other). Thus, a completely vertical Schottky diode has been obtained between the metallization 22 and a rear-face contact 24. By way of example, and without being limiting: the silicon wafer 20 may have a final thickness of 100 to 300 the optional metal layer 15 may be tungsten and have a thickness of 50 to 500 nm, for example of the order of 0.2 μm, B9707-09-T0-222

6 - la couche de GaN 14 fortement dopée de type N (N+) pourra avoir une épaisseur de 0,2 à 3 }gym, et - la couche de GaN 13 faiblement dopée de type N pourra avoir une épaisseur de 1 à 10 }gym selon la tenue en 5 tension inverse souhaitée de la diode Schottky. La figure 5 représente une variante de la structure de la figure 4 dans laquelle on a prévu un anneau de garde 31 de type P à la périphérie de la diode Schottky, et éventuellement un anneau 32 fortement dopé de type N à la périphérie du campo- 10 saut pour servir d'arrêt de canal. Ainsi, selon un avantage principal des modes de réalisation décrits de la présente invention, on obtient une diode Schottky parfaitement verticale sans qu'il existe une interface isolante (la couche tampon des diodes de l'art antérieur).6 - the N-type strongly doped GaN 14 layer (N +) may have a thickness of 0.2 to 3 μm, and the N-type lightly doped GaN layer 13 may have a thickness of 1 to 10 μm; depending on the desired reverse voltage behavior of the Schottky diode. FIG. 5 represents a variant of the structure of FIG. 4 in which there is provided a P-type guard ring 31 at the periphery of the Schottky diode, and possibly a strongly doped N-type ring 32 at the periphery of the 10 jump to serve as a channel stop. Thus, according to a main advantage of the described embodiments of the present invention, a perfectly vertical Schottky diode is obtained without there being an insulating interface (the buffer layer of the diodes of the prior art).

15 On notera que la présente invention est susceptible de nombreuses variantes en ce qui concerne notamment la nature du substrat 20 et la présence éventuelle d'une couche métallique 15. En divers emplacements de la présente description on 20 mentionne des régions "faiblement" dopées et "fortement" dopées. L'homme de l'art saura interpréter ces mentions sans ambigüité en tenant compte de la fonction des régions correspondantes, par exemple assurer une tenue en tension ou avoir un rôle de contact ohmique.It will be appreciated that the present invention is capable of many variations with respect in particular to the nature of the substrate 20 and the possible presence of a metal layer 15. At various locations of the present disclosure, "weakly" doped regions are mentioned. "strongly" doped. Those skilled in the art will be able to interpret these mentions without ambiguity by taking into account the function of the corresponding regions, for example to ensure a resistance in tension or to have a role of ohmic contact.

25 Parmi les dopants utilisables pour doper du GaN, on pourra choisir pour le type N Si, S et Ge et pour le type P Mg, Be, Zn et C. Among the dopants that can be used for doping GaN, it will be possible to choose for the type N Si, S and Ge and for the type P Mg, Be, Zn and C.

Claims (6)

REVENDICATIONS1. Diode Schottky verticale comprenant successivement, sur un substrat conducteur (20) : une couche (14) de GaN fortement dopée de type N ; une couche (13) de GaN faiblement dopée de type N ; un contact Schottky (22) sur la couche de GaN faible- ment dopée de type N. REVENDICATIONS1. A vertical Schottky diode comprising successively, on a conductive substrate (20): a layer (14) of strongly doped GaN type N; a layer (13) of lightly doped GaN type N; a Schottky contact (22) on the N-type weakly doped GaN layer. 2. Diode Schottky selon la revendication 1, dans laquelle le substrat conducteur (20) comprend un substrat de silicium fortement dopé revêtu d'une couche métallique à l'interface avec la couche (14) fortement dopée de type N de GaN. The Schottky diode according to claim 1, wherein the conductive substrate (20) comprises a highly doped silicon substrate coated with a metal layer at the interface with the GaN N-type strongly doped layer (14). 3. Diode Schottky selon la revendication 1 ou 2, dans laquelle le contact Schottky sur la couche (13) de GaN faible-ment dopée de type N est localisé. 3. Schottky diode according to claim 1 or 2, wherein the Schottky contact on the N-type low-doped GaN layer (13) is located. 4. Diode Schottky selon la revendication 3, dans laquelle la périphérie de la région de contact Schottky est entourée d'un anneau de garde (31) fortement dopé de type P dans la couche de GaN. The Schottky diode according to claim 3, wherein the periphery of the Schottky contact region is surrounded by a P-type heavily doped guard ring (31) in the GaN layer. 5. Diode Schottky selon la revendication 3 ou 4, dans 20 laquelle la périphérie extérieure de la couche (13) de GaN faiblement dopée de type N comprend un anneau d'arrêt de canal (32) fortement dopé de type N. The Schottky diode according to claim 3 or 4, wherein the outer periphery of the N-type lightly doped GaN layer (13) comprises a strongly doped N-type channel stop ring (32). 6. Procédé de fabrication d'une diode Schottky verti- cale selon la revendication 1, comprenant les étapes suivantes : 25 former sur un premier substrat (11) une couche tampon (12) ; faire croître sur la couche tampon (12) une couche (13) de GaN faiblement dopée de type N ; faire croître sur la couche faiblement dopée une 30 couche (14) de GaN fortement dopée de type N ; assembler la structure obtenue avec un deuxième substrat fortement conducteur (20), du côté de la couche fortement dopée de type N ; éliminer le premier substrat et la couche tampon ;B9707 - 09-T0-222 8 former un contact Schottky (22) sur la couche faible-ment dopée de type N. 6. A method of manufacturing a vertical Schottky diode according to claim 1, comprising the steps of: forming on a first substrate (11) a buffer layer (12); growing on the buffer layer (12) a layer (13) of lightly doped GaN type N; growing on the lightly doped layer a layer (14) of heavily doped N-type GaN; assembling the resulting structure with a second, highly conductive substrate (20) on the side of the heavily doped N-type layer; removing the first substrate and the buffer layer; forming a Schottky contact (22) on the weakly doped N-type layer.
FR1056654A 2010-08-18 2010-08-18 Gallium nitride vertical Schottky diode, has heavily doped p-type and n-type gallium nitride guard rings respectively provided at peripheries of electrode and lightly doped layer, where electrode is arranged on lightly doped layer Pending FR2963985A1 (en)

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WO2016042330A1 (en) * 2014-09-17 2016-03-24 Anvil Semiconductors Limited High voltage semiconductor devices
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CN113471302A (en) * 2021-07-09 2021-10-01 弘大芯源(深圳)半导体有限公司 Schottky diode with inner and outer potential protection rings
CN115148599A (en) * 2022-05-25 2022-10-04 深圳市汇芯通信技术有限公司 A vertical high-voltage JBS diode and its manufacturing method
CN115206799A (en) * 2022-08-10 2022-10-18 扬州扬杰电子科技股份有限公司 An etching process in which the top layer is metallic nickel

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