FR2951291A1 - Direct memory access controller for transferring data to e.g. peripheral, has blocking unit to block reading or writing work pointer if pointer points outside memory space reserved for reading or free memory space reserved for writing - Google Patents

Abstract

The controller (10) has an updation unit formed of management modules (24, 30) and firmware (40) for updating a reading or writing work pointer according to preset update logic. The logic has forward or backward movements of the pointer inside a circular buffer memory (16). A blocking unit formed of the modules and the firmware blocks the work pointer if the reading work pointer points outside a memory space reserved for reading or if the writing work pointer points outside a free memory space for writing defined from a writing pointer to an address preceding a reading pointer. Independent claims are also included for the following: (1) a method of transfer of data from a data source towards a recipient of the data by a direct memory access controller (2) a computer program downloadable from a communication network and/or recorded on a medium readable by a computer and/or executable by a direct memory access controller comprising a set of program code instructions for executing a method of transfer of data from a data source towards a recipient of the data.

Description

The present invention relates to a multi-address memory direct access controller, a method for transferring data from at least one data source to a plurality of recipients of that data implemented by that controller and a corresponding computer program.

Such a controller, qualified as a DMA (English "Direct Memory Access") controller, is generally used in a data processing device CPU such as for example an integrated circuit. It is used to transfer data processed or provided by the central processing unit, from or to peripheral devices such as communication ports, hard disks or any memory, between these devices and a local memory of the device by example, without the intervention of the central processing unit except to initiate and conclude the transfer. A DMA controller is for example very useful in a system where repeated access to fast devices could otherwise almost block or at least slow down the processing performed by the central unit. Its presence optimizes the processing time of software applications executed by the central unit by letting the DMA controller handle data transfers to and from the local memory. The invention more particularly applies to a direct memory access controller for the transfer of data from at least one data source to several recipients of this data, via a buffer memory comprising a predetermined number of elementary memory locations. successive, the access controller comprising a writes management module adapted to write data received from the source into the buffer memory and a storage pointer storage means indicating a basic location of the buffer memory in which a datum can be written. Such a DMA controller is for example described in the European patent published under the number EP 0 933 926. However it does not use one but more buffers. Its role is to write, in these buffers, data which are read successively by several receiver decoders having read access to these buffers. A write pointer, defined for each buffer, is incremented by an elementary memory location address at each write operation by the DMA controller of a data item in the corresponding buffer memory. But to transmit a sequence of data received from at least one source to multiple recipients, the DMA controller must be programmed to distribute the data to the plurality of intended buffers, one per recipient, managing updates of all pointers corresponding writing. This solution is quite complex. A simpler solution is to provide only one buffer in which the DMA controller writes all the data and in which they are then read sequentially to be transferred to the different recipients. But in this configuration, the sequential reading of the data for their transfer to all recipients is blocked as soon as one of the recipients blocks the reading of data.

It may thus be desired to provide a direct access controller in memory that makes it possible to overcome the aforementioned problems and constraints. The invention therefore relates to a direct memory access controller for transferring data from at least one data source to several recipients of this data, via a buffer memory comprising a predetermined number of successive memory elementary locations, the access controller comprising a writes management module adapted to write data received from the source into the buffer memory and means for storing a write pointer indicating an elementary location of the buffer memory in which data can be written, the access controller being further such that, for each recipient, the storage means comprises a read pointer indicating a basic location of the buffer in which data can be read for this recipient and the controller comprises means for executing a firmware for updating this read pointer according to an update logic. predetermined day for this recipient.

By firmware, we mean a software embedded in a hardware component such as an integrated circuit, more precisely in a volatile memory or not of this component. This term is used in the rest of the description as a translation of the English term "firmware". Thus, each firmware associated with a read pointer allows the direct memory access controller to flexibly manage reads and then data transmissions from the buffer to the corresponding recipient, independently of the other recipient or recipients. In other words, if a first recipient blocks the reading of data and therefore interrupts the execution of the firmware and the update of the read pointer associated with it, it does not prevent the execution of another firmware and the update of another read pointer associated with another recipient. This other recipient then normally receives its data, even if the first recipient remains blocked, even though the data is sequentially written by the direct memory controller in a single buffer.

Optionally, the buffer memory is circular, each elementary location being identified by an address between a base address and a vertex address of the circular buffer, and the direct memory access controller according to the invention may comprise in addition, a read management module designed to read data stored in the circular buffer memory and transfer them to the recipients and means for blocking read or write respectively in the circular buffer memory according to the relative positions of the elementary locations indicated by said read pointers and said write pointer. Thus, the buffer fulfills an intermediate buffer function with blocking read / write between the source and the recipient. This function is managed using the read pointers and the write pointer by the direct memory access controller which has write and read accesses in this circular buffer. In this way, it is able to synchronize the incoming data stream (s) (flow generated by the source (s)) with the outgoing data flows (flows generated by the recipients) without having to synchronize with the central processing unit. Optionally also, a direct memory access controller according to the invention may comprise means for selecting, from among the set of read pointers, the read pointer indicating the least advanced elementary location with respect to the elementary location indicated by the write pointer taking into account a predetermined direction of the updates, these selection means being activated at each update of any of the reading pointers, and the reading blocking means, respectively write, in the circular buffer can be based on the relative positions of the elementary locations indicated by said selected read pointer and said write pointer. Optionally also, the read-blocking means are adapted to block any read of data in the circular buffer when an update of any one of the read pointers causes the address to which the pointer points to selected reading reaches or exceeds the address to which the write pointer points, and the write lock means is arranged to block any write of data in the circular buffer when a write pointer update is the address to which it points reaches or exceeds the address to which the selected read pointer points.

Optionally also, the storage means further comprise, for each recipient, a read pointer called "work pointer", different from said read pointers, the controller having means for executing an update firmware. the job pointer of each recipient, each read performed by the job pointer, according to a predetermined update logic for this recipient. Thus, it is possible to consider more flexibility in reading or writing data in the circular buffer without the direct memory access controller losing its ability to synchronize incoming and outgoing flows.

Optionally also, the predetermined update logic for the job pointer of each recipient has at least one address hop in the circular buffer so as to read the data assigned to that recipient in a different order from that in which they were written in the circular buffer.

Thus, the circular buffer whose memory direct access controller manages the tracking of reads and writes is not used by the controller as a simple list of FIFO type from the point of view of the recipients. By scheduling updates of the job pointers according to a predetermined logic, it is possible to change the sequence of data assigned to the respective recipients, between their reception from the source and their transmission to the recipients via the circular buffer. Optionally also, the reading pointer selected is a read pointer to free memory space for writing data, the working pointer of each recipient is a read pointer read data retention, and the pointer of The write is automatically updated incrementally without an address jump at each write operation of a data item in the circular buffer. Optionally also, a direct memory access controller according to the invention may include means for releasing memory space in the circular buffer memory designed to release, for a data write, a memory space between the location the old address pointed and the location before that of the new address pointed by the selected reading pointer, each update of the latter by the selection means. The invention also relates to a method of transferring data from at least one data source to several recipients of these data by a direct memory access controller as defined above, such that, each data received from the source being transmitted by the controller to a buffer memory and each piece of data to be transmitted to one of the recipients being read into the buffer memory by a read management module, it comprises, for each recipient, a succession of steps of reading data and of updating a read pointer associated with this recipient, this succession of steps being executed by the read management module and defined in a read and update firmware of the read pointer of this recipient according to a predetermined update logic for this recipient.

Finally, the invention also relates to a computer program downloadable from a communication network and / or recorded on a computer-readable medium and / or executable by a direct memory access controller, comprising code instructions of program for executing the steps of a data transfer method as defined previously when said program is executed by a direct memory controller. The invention will be better understood with the aid of the following description, given solely by way of example and with reference to the appended drawings in which: FIG. 1 schematically represents the general structure of an access controller 2 shows schematically the advantageous operation of the direct memory access controller of FIG. 1 in a blocking situation of a recipient, FIG. 3 schematically represents the advantageous operation of the direct memory access controller of FIG. the structure of a circular buffer managed by the direct memory access controller of FIG. 1, and FIG. 4 illustrates the successive steps of a data transfer method, according to one embodiment of the invention.

The direct memory access controller or DMA controller 10 shown in FIG. 1 has the function of transferring data from at least one data source 12 to several recipients 141, ..., 14 ;, ..., 14, of these data via a buffer memory 16 comprising a predetermined number of successive memory elementary locations. For the implementation of the invention, it is necessary that the DMA controller 10 has access to the buffer memory 16 in writing and optional that there is read access. But in the example illustrated in FIG. 1, it is able to access write and read data at the elementary locations of the buffer memory 16 via a module 18 for controlling write access and read access. data interfacing between the DMA controller 10 and a storage medium incorporating the buffer memory 16. Note that in an alternative embodiment, the DMA controller, then carrying the reference 20, includes the storage medium incorporating the buffer memory 16 and the module 18 for controlling write and read accesses. In practice, it may be in the form of an autonomous on-chip system, for example a CMOS-type integrated circuit. As a nonlimiting example of implementation, according to a conceivable architecture called NoC (Network on Chip) or network on chip, the DMA controller 10 or 20 is considered as consisting of functional elements communicating between them via links of a packet-switched network. According to this architecture, to carry out the transfer of data from the source 12 to the recipients 141, ..., 14 ;, ..., 14m, the DMA controller 10 or 20 comprises the following elements: a link 22 for receiving data from the source 12, a module 24 for managing the data entries by the controller 10 or 20 in the buffer memory 16, this module being activated by data that it receives from the link 22, a transmission link 26 data to the buffer memory 16 for writing this data in elementary memory locations via the write and read access control module 18, a link 28 for receiving data from the memory buffer 16 for reading this data in elementary memory locations via the read / write access control module 18, a data readout management module 30 by the controller 10 u 20 in the buffer memory 16, able to receive the data provided by the link 28, and a link 32 for transmitting the data read to the recipients 141, ..., 14 ;, 14n. Thanks to these elements, the DMA controller 10 or 20 transmits each data received from the source 12 to the buffer memory 16, each data item intended to be transmitted to one of the recipients 141, ..., 14 ;, ..., 14n is then read into the buffer memory 16 by the DMA controller 10 or 20. The buffer 16 thus fulfills an intermediate buffer function between the source 12 and the recipients 141, ..., 14 ;, ..., 14n. It will be noted that in another possible embodiment of the invention not illustrated, when the DMA controller 10 does not integrate the buffer memory 16 and that in addition it does not itself have read access to the data. in the buffer 16, it is the recipients 141, ..., 14 ;, ..., 14n which will read directly into the buffer memory 16 the data intended for them. But in this case, in a conventional manner and not detailed, even if the data does not pass through the DMA controller 10, it still retains a mechanism for triggering readings by the recipients. Buffer 16 may be implemented in different ways known per se, but in a preferred embodiment, it is in the form of a circular buffer.

It then occupies a memory space between a base address and a vertex address. A write or read pointer associated with this circular buffer is incremented between the base address and the vertex address and returns to the base address incrementally after reaching the vertex address: this is which qualifies this buffer memory "circular buffer". The advantage of this circular buffer configuration, for example of the type FIFO (of the English "First ln First Out"), is to avoid memory reallocation constraints in case of receipt of additional data, since everything happens. passes as if it were possible to write indefinitely data in such memory as the address to which the writing pointer points does not reach an elementary location in which is stored data that has not yet been read, that is to say as long as the memory is not full. In this case, optionally, the data reception link 22 comprises a FIFO-type input buffer 34, for example for temporarily storing data received from the source 12 while the circular buffer memory 16 is blocked by write because it is full. Optionally also, the link 32 for transmitting the read data comprises an output buffer 36 of FIFO type, for example for temporarily storing data read in the circular buffer memory 16 while the output network is temporarily saturated or at least one of the recipients is blocked in reading. To allow the distribution of the data stream entering the DMA controller to the recipients 141, ..., 14 ;, ..., 14m, it further comprises means 38 for storing descriptors of the circular buffer 16 .

These descriptors comprise at least one base pointer PB pointing to a base address of the circular buffer 16 in its storage medium, a vertex pointer PS pointing to a vertex address of the circular buffer 16 in its storage medium , a write pointer PE pointing to an elementary location address of the circular buffer 16 where a next data received by the DMA controller 10 or 20 can be written and several read pointers PLI, ..., PLi,. .., PLn. Each read pointer PLi points to an elementary location address of the circular buffer 16 where a next data item may be read to be transmitted to the recipient 14;

Since the buffer memory 16 is a circular memory whose size is defined by the number of elementary locations between the base and vertex addresses designated by the PB and PS pointers, each elementary location of this memory to which pointers can point. for writing and reading PE and PLI, ..., PLi, ..., PLn is identified by an address between the base address and the vertex address. The base and vertex pointers PB and PS are predetermined and intended to remain constant while the write pointers PE, respectively PLI read, ..., PLi, ..., PLn, are variable. They can actually be updated by incrementing with or without address jumps thus defining a sense of updates.

The write pointer PE is for example more specifically intended to be updated by incrementing a basic location in the direction from the base to the top, following a write operation in the circular buffer. On the other hand, the read pointers PLI, ..., PLi,..., PLn are updated respectively by the execution of firmware 401,..., 40 ;,..., 4On. Their updating is predetermined so that each reading pointer PLi points to a basic location in which is stored data actually to be transferred to the corresponding recipient 14 ;. The firmware 401, ..., 40 ;, ..., 40n are for example stored in the same storage medium as the circular buffer memory 16. They are, in general, executed by a management module readings in the circular buffer memory 16, whether it is internal or external to the DMA controller. In the particular example of FIG. 1, they are more precisely executed by the read management module 30 of the DMA controller 10 or 20.

As indicated above, the circularity of the buffer 16 is related to the fact that when a write or read pointer reaches the vertex address of the memory, incrementing that pointer by one elementary location causes it to point to the base address of the memory. Therefore, the data stored temporarily in the circular buffer 16 waiting to be read, either by the DMA controller 10 or 20 to be transmitted to the recipients 141, ..., 14 ;, ..., 14n, or directly by the recipients 141, ..., 14 ;, ..., 14n, are located between the address of the read pointer PLi the least advanced compared to the write pointer given the meaning of the updates and the address preceding that of the write pointer PE, in the direction of the base towards the top. On the other hand, the memory space in the circular buffer between the address of the write pointer PE and the address preceding that of the read pointer PLi the least advanced with respect to the write pointer, in the sense of the base to the top, is a free space for writing. This structure of the circular buffer 16 associated with the descriptors PB, PS, PE and PLI, ..., PLi, ..., PLn is illustrated in FIG. 3 which will be detailed later. The advantageous operation of the direct memory access controller 10 or 20 of FIG. 1 is illustrated in FIG. 2, in a particular application, which is simple but nonlimiting. According to this application, the source 12 provides a sequence of data alternating data (white points) intended to be transferred to a recipient 141 and data (black dots) intended to be transferred to a recipient 142. Thanks to the incremental update address address of the write pointer PE, these data are stored in the circular buffer 16 in the order of the sequence provided by the source 12. The data intended to be transferred to the recipient 141 are read in the circular buffer memory 16 by executing a firmware 401 for updating a read pointer PLI pointing at each moment to the elementary location of the next piece of data to read for the recipient 141. The updating logic applied by this firmware 401 for the intended application is therefore to increment the read pointer PLI by skipping an address at each data read performed in. to the recipient 141 so as not to read data assigned to the recipient 142. Similarly, the data to be transferred to the recipient 142 are read into the circular buffer 16 by executing a firmware 402 bet update of a read pointer PL2 pointing at each moment to the elementary location of the next piece of data to be read for the recipient 142. The update logic applied by this firmware 402 is also to increment the read pointer PL2 by skipping an address at each read of data performed for the recipient 142 so as not to read data assigned to the recipient 141. The two firmware 401 and 402 are independent and can therefore be executed in parallel by the DMA controller 10 or 20, the blocking of one of the two, in particular because the corresponding recipient blocks reading, does not affect the other. It is therefore clear that the DMA controller is thus able to simply and efficiently manage the transfer of data to multiple recipients without one of them can block alone the transfer of all data. In combination with this transfer function without blocking by one of the recipients, it is possible, in a particular embodiment of the invention, to provide that the DMA controller can also perform a function of synchronizing the incoming and outgoing flows. To implement this particular embodiment, it is necessary for the DMA controller to include the read management module 30 previously defined. In this case, this module 30 for managing the readings can be programmed to: select, from the set of read pointers PLI, ..., PLi, ..., PLn, the read pointer noted PLS indicating the location elementary least advanced relative to the basic location indicated by the write pointer PE given the predetermined direction of the updates, and make this selection with each update of any of the reading pointers PLI,. .., PLi, ..., PLn following a reading of data made for any of the recipients. On the basis of these considerations, the data writes management module 24 is designed to allow or block the writing of a piece of data in the circular buffer memory 16 as a function, in particular, of the relative values of the write pointer PE and the pointer selected reading PLS. It is also designed to automatically update the PE write pointer using a sequencer by incrementing it from a basic location. More specifically, in a simple variant of this particular embodiment of the invention, a piece of data to be written in the circular buffer memory 16 must be written at the address indicated by the write pointer PE; its writing must be blocked if an update of the PE write pointer previously performed by the writes management module 24 makes the address to which it points reaches or exceeds the address to which the PLS reading pointer points (full memory). On the basis of these same considerations, the data read management module 30 is designed to allow or block the reading of data in the circular buffer memory 16 as a function, in particular, of the relative values of the write pointer PE and the pointer. selected reading PLS. It is also designed to update each read pointer PLi by the execution of each firmware 40; More precisely, in a simple variant of this particular embodiment of the invention, a piece of data to be read in the circular buffer memory 16 for a recipient 14; must be read at the address indicated by the read pointer PLi; its reading must be blocked if an update of the read pointer PLi performed previously by the read management module 30 makes the address to which the selected reading pointer PLS points reaches or exceeds the address pointed to by the pointer PE writing (empty memory). Specifically, so that the blocking and unblocking read and write in the circular buffer 16 operate as indicated above, the module 24 for writing management can be programmed to, after each update of the PE write pointer: block any write of data in the circular buffer 16 if the write pointer PE reaches the selected read pointer PLS (indicating that the memory is full), and unblock the reading of data in the circular buffer 16 if it was locked and the PE write pointer again exceeds the selected PLS read pointer. Similarly, the module 30 for managing the readings can be programmed to, after each update of a read pointer PLi: - block any reading of data in the circular buffer memory 16 if the selected read pointer PLS reaches the pointer write PE (indicating that the memory is empty), and unblock the writing of data in the circular buffer 16 if it was blocked and the selected read pointer PLS exceeds the read pointer PE. In this way, the writes management module 24 performs a write blocking function when the memory 16 is full and read-free when the empty memory fills up again. The read management module 30 performs a read-lock function when the memory 16 is empty and write-off when the full memory is empty again. The above detailed operation of the write and read management modules 24 and 30 is only one example of implementation of the write and read blocking means in the circular buffer memory 16 by means of the pointers d. writing and reading PE and PLI, ..., PLi, ..., PLn. But it will be apparent to those skilled in the art that other implementations or variants can be envisaged to make the circular buffer 16 with reads and write-offs depending on the value of the write and read pointers PE and PLI, etc. , PLi, ..., PLn. These features make the DMA controller 10 or 20 capable of synchronizing the incoming stream of data from the source 12 and the outgoing streams to the recipients 141, ..., 14 ;, ..., 14n. As a result, in an integrated circuit comprising a microprocessor, the data source 12 which is for example a local memory for temporary storage of the data processed or used by the microprocessor, the recipients 141, ..., 14 ;, .. ., 14n which are for example any functional devices or operators and the DMA controller according to its variant embodiment including the circular buffer memory 16, the microprocessor can transfer data to the source 12 independently of the transfers made by the DMA controller between source 12 and recipients 141, ..., 14 ;, ..., 14n.

In combination with this synchronization function of the DMA controller, it is possible, in another embodiment of the invention and according to a first variant, to define for each recipient 14; a new read pointer, called "job pointer". For each recipient 14 ;, this working pointer is different from the reading pointer PLi defined above. Like him, it is stored in the storage means 38. It is variable and intended to be updated by the firmware 40; after each read operation he performs. In Figure 3 which illustrates a simple two-recipient embodiment 141 and 142, two work pointers PT1 and PT2 are added to the write pointer PE and the read pointers PL1 and PL2.

Firmware 40; can be defined so that the update logic of the PTi work pointer reads the data for the recipient 14; in an order that is not that of the sequence transmitted by the source 12. By introducing this new pointer PTi for each recipient 14; and the possibility of updating it by forward and backward address jumps as illustrated in FIG. 3, in the circular buffer memory 16 and more precisely in the list of data assigned to the recipient 14; is not used as a simple FIFO type list. The job pointers PT1,..., PTi,..., PTn enable the DMA controller 10 or 20 to reorder itself each sequence of data to be transferred between the source 12 and any of the recipients 141,. ., 14 ;, ..., 14n.

In this first variant, the selected read pointer PLS is then a read pointer to free memory space for writing data. In other words, with each selection of one of the read pointers as the selected read pointer, the memory space between the location of the old address pointed to and the location preceding that of the new address pointed to by the selected reading pointer PLS is automatically released for writing. This is because, as previously indicated, the memory space in the circular buffer 16 between the address of the write pointer PE and the address preceding that of the selected read pointer PLS in the base direction to the summit is considered in principle as a free space for writing.

In the simple example of FIG. 3, the read pointer PLI is the least advanced relative to the write pointer PE. It is therefore it which is selected and also taken as reference to define the beginning of the memory space storing data to be read and transferred to the recipients. More specifically, the memory space with the reference A designates a memory area in which there are data assigned to the recipient 141 that have not yet been read and data assigned to the recipient 142 that have been read: this zone n ' is not yet free to write. The memory space bearing the reference B designates a memory area in which there are data assigned to the recipients 141 and 142 which have not yet been read: this zone is a fortiori not free to write. Each working pointer PTi is, meanwhile, a read pointer retention of read data. In other words, when data must be read in the circular buffer 16 to be transmitted to the recipient 14 ;, it is read at the address indicated by the work pointer PTi, but the update of the work pointer PTi after this reading does not release the corresponding elementary location for writing. Indeed, the read displacements of the working pointer PT i do not necessarily follow the sequence of the data assigned to the recipient 14; in ascending order of addresses. They are freely predetermined by the firmware 40; in an arbitrary order, preferably between the read pointer PLi and the write pointer PE. According to the applications, a data read a first time by the working pointer PT i can notably be read again and the data can be read in a different order from that of their storage in the circular buffer memory 16.

It is therefore noted that in this embodiment where each working pointer PTi is a read pointer, each firmware 40; includes instructions, executed by the read management module 30, for updating the two reading pointers associated with the recipient 14; : instructions that may include forward and / or backward address jumps depending on the intended application for the PTi work pointer, instructions that may include address jumps, but only forward, depending on the addresses where find the data assigned to the recipient 14; and according to the programmed displacements for the working pointer PTi, for the reading pointer PLi.

On the other hand, none of the firmware 401,..., 40 ;,..., 40n includes instructions for updating the write pointer PE, this being for example updated by a sequencer without address jump and incrementally each write operation of a data in the circular buffer memory 16.

It will also be noted that, as illustrated in FIG. 3, the displacements of the working pointers PT1,..., PTi,..., PTn must be programmed so that they point in the zone of the circular buffer memory 16 which comprises actually data to read respectively for the recipients 141, ..., 14 ;, ..., 14n. If one of them points, after an update, outside this zone, then it can be provided according to the targeted applications, either to generate an error message, or to block it at this position until the PE write pointer catches it. According to the invention, this blocks the execution of the firmware 40; corresponding to the blocked PTi work pointer, but this does not block the execution of any other firmware 40; associated with another recipient 14;

In a symmetrical embodiment of the previous embodiment, to reorder the data sequence, it would also be possible to define a single work pointer PT as a write pointer. In this second variant, the write pointer PE would be a memory reservation write pointer for writing data in the circular buffer memory 16. In other words, whenever it would be set to day, the memory space between the location of the old dotted address and the location before that of the new address pointed by this PE write pointer would automatically be reserved for writing. The working pointer PT would, meanwhile, an effective writing pointer write data in any predetermined order in the memory space reserved by the pointer PE. But this second variant is less interesting to consider than the previous one because it is likely to cause blockages on the write side of the data in the circular buffer 16. In a data transfer application by a controller DMA, it is preferred to manage blocking downstream, the side of the readings in the circular buffer, rather than upstream, write side. An example of a method of transferring data to several recipients 14; that can be implemented by the DMA controller 10 or 20 will now be detailed, in the context of the first aforementioned embodiment variant, in which the DMA controller is in blocking read and write management of the circular buffer memory 16 and in which working pointers PT1, ..., PTi, PTn are introduced as read pointers to retention of read data. The successive steps of this method are illustrated in FIG. 4. During a first step 100, the controller 10 or 20 is waiting for an instruction to read or write data in the circular buffer 16 This step 100 is followed by a write triggering step 102, on the instruction to write a piece of data in the circular buffer memory 16. During this write triggering step, the writing management module 24 is activated. .

As a non-limiting exemplary embodiment, it extracts from the storage means 38 the value of a first descriptor indicating whether the writing in the circular buffer memory 16 is blocked or not. Then, during a test step 104, according to the value of this first descriptor, it is decided to continue or not to write the data considered. If the first descriptor indicates that the writing is blocked, we go back to step 100, otherwise we go to a step 106. In step 106, the writes management module 24 extracts storage means 38 the address to which the PE write pointer points. It then executes the writing of the data considered in the corresponding elementary location. Then, during an updating step 108, the address pointed by the write pointer PE is incremented by one elementary location in the circular buffer memory 16. Finally, during a step 110, the module 24 writes from the storage means 38 the address to which points the selected read pointer PLS then eventually updates the value of the first write blocking descriptor and that of a second descriptor blocking readings, in the following situations: if after the update of step 108, the address pointed by the write pointer PE reaches that pointed by the selected read pointer PLS (indication that the memory 16 is full), modification of the first descriptor for the latter to indicate a blocking of the writes, if after the updating of step 108, the address pointed by the writing pointer PE differs from that pointed by the reading pointer selected PLS while the second descriptor indicates a blocking readings, modification of the second descriptor for the latter indicates an authorization readings. Step 110 is followed by a return to step 100. Step 100 is also followed by a step 112i of triggering a read of data by the firmware 40 ;, on instruction to read data in the circular buffer 16 for the recipient 14; During this read triggering step, the read management module 30 is activated. As a nonlimiting exemplary embodiment, it extracts from the storage means 38 the value of the second descriptor indicating whether the reading in the circular buffer memory 16 is blocked or not. Then, during a test step 114i, the read management module 30 determines whether the recipient 14; is ready to receive the given data. This test can be done in many ways. If the DMA controller 10 or 20 has the output buffer 36, then it can be considered that a data transfer can be performed as long as this output buffer 36 is not full. Failing or in addition, a conventional communication protocol may provide that the recipient 14; informs the DMA controller 10 or 20 of its ability to receive data by messages in the predetermined format. If the transfer of the data to the recipient 14; is not possible, go back to step 100 and run firmware 40; is blocked, otherwise we go to another test step 116i. During this test step 116i, according to the value of the second descriptor, it is decided to continue or not to read the data considered. If the second descriptor indicates that the reading is blocked, go back to step 100 and the execution of the firmware 40; is blocked, otherwise we go to a reading step 118i. During this step 118i, the read management module 30 extracts from the storage means 38 the address to which the working pointer PTi points. It then executes the reading of the data considered in the corresponding elementary location.

Then, during an updating step 120i, the address pointed by the working pointer PTi is updated, either forwards or backwards, by the module 30 for managing the readings. according to the instructions of the firmware 40 ;. If this is also provided by the instructions of the firmware 40, the read pointer PLi can be updated also at this step causing the updating of the selected reading pointer PLS.

Finally, during a step 122i, the read management module 30 possibly updates the value of the first write blocking descriptor and that of the second read blocking descriptor, in the following situations: if after the update in step 120i, the address pointed by the selected reading pointer PLS reaches that pointed by the write pointer PE (indication that the memory 16 is empty), modifying the second descriptor so that the latter indicates a blocking of the readings if, after the update of step 120i, the address pointed by the selected read pointer PLS differs from that pointed by the write pointer PE, while the first descriptor indicates a blocking of writes, modification of the first descriptor for the latter to indicate an authorization of the entries. Step 122i is followed by a return to step 100. As already stated above, each firmware 40; provides for the execution of steps 112i to 122i, knowing that several firmware can be run in parallel, blocking one does not block the others. It is clear that the previously described direct memory access controller and its operation for data transfer makes it possible to simply manage the transfer of data from at least one source to several recipients, without a recipient blocked from reading blocking the data transfer. or other recipients. It will also be noted that the invention is not limited to the embodiments envisaged. In particular, in the foregoing, to simplify the description, it has been envisaged an application where the transfer is made from a single source, but the principle of the invention applies in the same way with several sources. Similarly, a direct memory access controller according to the invention can manage several circular buffers and therefore several sets of descriptors (pointers, blocking descriptors, etc.) associated. More generally, it will be apparent to those skilled in the art that various modifications may be made to the embodiments described above, in light of the teaching just disclosed. In the following claims, the terms used are not to be construed as limiting the claims to the embodiments set forth in this specification, but should be interpreted to include all the equivalents that the claims are intended to cover because of their formulation and whose prediction is within the reach of the person skilled in the art by applying his general knowledge to the implementation of the teaching which has just been disclosed to him.

Claims (10)

REVENDICATIONS1. Direct Memory Access Controller (10, 20) for transferring data from at least one data source (12) to multiple recipients (141, ..., 14 ;, ..., 14n) of this data, via a buffer (16) comprising a predetermined number of successive memory elementary locations, the access controller including a writes management module (24) adapted to write data received from the source (12) into the memory buffer (16) and means (38) for storing a write pointer (PE) indicating an elementary location of the buffer in which data may be written, characterized in that for each recipient (141, 142 ), the storage means (38) comprises a read pointer (PL1, PL2) indicating an elementary location of the buffer memory (16) in which data can be read for this recipient (141, 142) and the controller includes means for executing a firmware (401, 402) of update of this read pointer (PLI, PL2) according to a predetermined update logic for this recipient. A direct memory access controller (10, 20) according to claim 1, wherein the buffer memory (16) is circular, each elementary location being identified by an address between a base address and a vertex address of the circular buffer, the controller further comprising a read management module (30) adapted to read data stored in the circular buffer (16) and transfer them to the recipients (141, ..., 14 ;,. .., 14n) and read / write lock means (24, 30, 40) in the circular buffer (16) as a function of the relative positions of the elementary locations indicated by said read pointers (PL1, PL2 ) and said write pointer (PE). 3. A direct memory access controller (10, 20) according to claim 2, comprising means (30) for selecting, among the set of reading pointers (PLI, PL2) of the reading pointer (PLS) indicating the least advanced elementary location relative to the elementary location indicated by the write pointer (PE) given a predetermined direction of the updates, these selection means (30) being activated at each update of any one of the read pointers (PLI, PL2), and in which the reading blocking means (24, 30, 40), respectively writing, in the circular buffer memory (16) are based on the relative positions of the elementary locations indicated by said selected read pointer (PLS) and said write pointer (PE). The direct memory access controller (10, 20) according to claim 3, wherein the read-blocking means (30, 40) is arranged to block any reading of data in the circular buffer (16) when updating any of the read pointers (PL1, PL2) causes the address to which the selected read pointer (PLS) points to reach or exceed the address to which the write pointer points (PE ), and wherein the write-blocking means (24, 40) is arranged to block any write of data in the circular buffer (16) when an update of the write pointer (PE) causes the write pointer (16) to address to which it points reaches or exceeds the address to which the selected read pointer (PLS) points. A direct memory access controller (10, 20) according to any one of claims 2 to 4, wherein the storage means (38) further comprises, for each recipient (141, 142), a pointer ( PT1, PT2) for reading said "working pointer", different from said read pointers (PLI, PL2), the controller comprising means (30) for executing a firmware (401, 402) for updating the pointer of each recipient (141, 142), at each reading performed by this working pointer (PT1, PT2), according to a predetermined update logic for this recipient. A direct memory access controller (10, 20) according to claim 5, wherein the predetermined update logic for the working pointer (PT1, PT2) of each recipient (141, 142) comprises at least one an address jump in the circular buffer to read the data assigned to that recipient (141, 142) in an order different from that in which they were written in the circular buffer (16). The direct memory access controller (10, 20) according to claims 3 and 5, wherein the selected read pointer (PLS) is a memory space free read pointer for writing data, the working pointer (PT1, PT2) of each recipient (141, 142) is a read-read read pointer, and in which the write pointer (PE) is updated automatically by incrementing without an address jump at each write operation of a piece of data in the circular buffer (16). A direct memory access controller (10, 20) as claimed in claim 7, including memory space releasing means (30) in the circular memory buffer (16) adapted to free space for data writing. memory between the location of the old address pointed and the location before that of the new address pointed by the selected reading pointer (PLS), each update of the latter by the selection means (30). 9. A method of transferring data from at least one data source (12) to a plurality of recipients (141, ..., 14 ;, ..., 14n) of these data by a direct memory access controller (10). , 20) according to any one of claims 1 to 8, characterized in that, each data received from the source (12) being transmitted (106) by the controller (10, 20) to a buffer memory (16) and each data to be transmitted to one of the recipients (14;) being read (118i) in the buffer memory (16) by a read management module (30), it comprises, for each recipient (141, 142) a succession of steps of reading (118i) data and updating (120i) a read pointer (PLI, PL2) associated with this recipient, this succession of steps being executed by the read management module and defined in a firmware (401, 402) for reading and updating the read pointer (PLI, PL2) of this recipient (141, 142) according to a setting logic predetermined day to this recipient. Computer program downloadable from a communication network and / or recorded on a computer readable medium and / or executable by a direct memory access controller (10, 20), characterized in that it comprises instructions program code for performing the steps of a data transfer method according to claim 9 when said program is executed by a direct memory access controller.