FR2950503A1 - Circuit for detecting wavelength of e.g. visible ray, has derivation circuit derivating part of parasitic current, and auxiliary polarization circuit maintaining polarization voltage of photodetector in one of states of detection circuit - Google Patents

Abstract

The detection circuit comprises a photodetector 1 connected to a reading circuit 2. A coupling switch S4 is connected in series between the photodetector and the read circuit. The detection circuit is in a first state when the coupling switch S4 is closed and in a second state when the coupling switch is open. The reading circuit ensures, in the first state of the detection circuit, a polarization of the photodetector. The detection circuit comprises a bypass circuit 4 of the parasitic current of the photodetector 1 with an adjustable current source, a control circuit 5 'of the bypass circuit 4, and a polarization circuit 6 of the photodetector which maintains, in the second state , the same bias voltage of the photodetector 1 as that of the read circuit 2.

Description

Detection circuit with bypassing part of the current of a photodetector and operating method

Technical field of the invention

The invention relates to a detection circuit comprising a photodetector connected to a read circuit, the reading circuit imposing, in a first state of the detection circuit, a bias voltage of the photodetector. State of the art

Optical sensing circuits generally include a photodetector coupled to a readout circuit. The reading circuit has the role of converting and possibly amplifying the signal from the photodetector so that it can be processed.

Figure 1 shows an example of a detection circuit commonly used with photodetectors. The circuit comprises a photodetector 1 and a reading circuit 2. A terminal of the photodetector, the cathode in the example of FIG. 1, is connected to the reading circuit 2. The other terminal of the photodetector, the anode for example, is connected to the substrate potential of the photodetector VSUB. The read circuit 2 may be of the integrator type. It plays a dual role: on the one hand, it integrates the current II of the photodetector and thus converts the current into a usable voltage Vs, and on the other hand, it ensures the polarization of the photodetector 1. For example, the Read circuit 2 may be realized by a Capacitive Transimpedance Amplifier (CTIA) shown in FIG.

such integrator comprises an operational amplifier 3. The first input of the amplifier 3, the negative input for example, forms the input of the reading circuit 2 and the output of the amplifier 3 forms the output of the read circuit. The second input of the amplifier, the positive input on the example of Figure 1, receives a reference potential VREF. The read circuit 2 also comprises an integration capacitor C1 and a resetting switch S1 connected in parallel between the first input of the amplifier and the output of the amplifier.

Thus, the current Il pulled by the photodetector is integrated in the capacitor C1 and converted into a voltage ramp VS at the output of the read circuit 2. The integration time corresponds to an exposure time. The voltage Vs is used at the end of the integration phase, just before the discharge of the capacitor C1 by closing the switch S1 to start a new integration phase.

The CTIA assembly makes it possible to establish the polarization of the photodetector 1 while maintaining the voltage VPO of the photodetector terminal at the reference potential VREF. The voltage across the photodetector is then equal to VREF 'VSUB.

A reading circuit such as the capacitive transimpedance amplifier (CTIA) is advantageous because it provides a stable polarization of the photodetector, a low noise level, good accuracy and good linearity.

In the field of the infrared, the current II of the photodetector 1 consists of a thermal component, also called parasitic current, and a useful component, called photonic current. The thermal current component corresponds, for example, to the dark current and does not carry useful information. 3

A problem of such a detection circuit occurs during a reading of strong currents from the photodetector. Indeed, too much current leads to a saturation of the reading circuit and / or the impossibility of integrating the entire current. This problem is particularly constraining in infrared imaging, especially when detecting long wavelengths or when detected on a high emissive background. In such cases, the thermal current component is much greater than the useful current component and it becomes difficult to discriminate the useful current.

It is then necessary to correct the current of the photodetector by deriving the parasitic current.

Object of the invention

The aim of the invention is a parasitic current bypass detection circuit that can be used with an integrator readout circuit for polarizing the photodetector. The invention more particularly relates to a detection circuit capable of establishing a bypass current while maintaining the polarization of the photodetector when the photodetector is decoupled from the reading circuit during a phase of establishment of the bypass current. According to the invention, this object is achieved by the fact that the detection circuit comprises a photodetector connected to a read circuit, the reading circuit imposing, in a first state of the detection circuit, a bias voltage of the photodetector. The circuit comprises a coupling switch connected in series between the photodetector and the read circuit, the detection circuit being in the first state when the switch is depressed.

coupling is closed and in a second state when the coupling switch is open. The circuit also comprises a bypass circuit arranged to derive a portion of the current of the photodetector and an auxiliary polarization circuit arranged to maintain, in the second state, the bias voltage of the photodetector.

The invention also relates to a method of operating a photodetector, allowing the derivation of the parasitic current of the photodetector.

This is achieved by the fact that the method comprises an initialization phase and a shooting phase. The shooting phase comprises reading the signal from the photodetector by a reading circuit and the polarization of the photodetector by the read circuit. The initialization phase includes disconnecting the photodetector from the read circuit, establishing a bypass current, and maintaining the polarization of the photodetector by an auxiliary bias circuit. The shooting phase further comprises applying the bypass current to the photodetector.

20 Brief description of the drawings

Other advantages and features will emerge more clearly from the following description of particular embodiments of the invention given by way of non-limiting example and represented in the accompanying drawings, in which:

FIG. 1 represents a detection circuit according to the prior art, FIG. 2 represents a detection circuit said to be directly coupled with a bypass function, FIGS. 3 and 4 represent particular embodiments of a detection circuit. according to the invention,

FIGS. 5A to 5G and 6A to 6E show signal evolutions of the circuit of FIG. 4, FIGS. 7 and 8 show the circuit of FIG. 4 in two distinct states. Description of particular embodiments

A bypass or parasitic current compensation function can be performed by means of a circuit shown in FIG. 2 and described in the patent FR2634900. This detection system is used with a photodetector and a reading circuit coupled by direct injection. By direct injection coupling, it is meant that the electrons coming from the photodetector are directly injected into a transistor which ensures the polarization of the photodetector.

This system comprises a photodetector 1 connected to a read circuit that summarizes an integration capacitance Cl '. The reading circuit does not ensure the polarization of the photodetector. This is provided by a bias transistor T 1 connected between the photodetector 1 and the capacitor C 1 '. The system further comprises a bypass circuit 4 of the parasitic current of the photodetector.

This branch circuit 4 comprises an adjustable current source 25 constituted for example by a P-type MOS transistor T2 connected to a supply line VDD.

A control circuit 5 of the transistor T2 has a control capacitor C2 connected to the gate of the transistor T2 (point C). The control capacitance C2 is further connected to the capacitance Cl 'via a

switch S2 and to the VDD supply line via switch S2 and switch S3.

The operation of this circuit is divided into two phases: an initialization phase during which the photodetector receives a reference photon flux and a shooting phase during which it receives the radiation to be studied. During the initialization phase, the detector is for example placed in front of a cold screen, a black body or in front of the space for a spatial application. The reference photon flux corresponds for example to the ambient background.

In the initialization phase, the current Il pulled by the photodetector corresponds to the parasitic current. In this phase, a bypass current 13, or correction current, is established in the circuit 4, equal to the current h, which will cancel the parasitic current during the shooting phase.

At the beginning of the initialization phase, the bypass current 13 is zero, that is to say that the transistor T2 has not yet received a setpoint. The setting of the transistor T2 is carried out as follows: the switches S2 and S3 are both closed in order to charge the integration capacitance Cl 'and the control capacitor C2 to their initial value, corresponding to the supply potential V DD . Then, the switch S3 is open so that the integration capacitance Cl 'and the control capacitance C2 are discharged into the photodetector 1. The capacitors C1' and C2 are discharged by the current Il pulled by the photodetector. Thus, the voltage across the control capacitor C2, that is to say the potential at the point C, decreases, just like the voltage across the capacitor Cl '.

The voltage across the control capacitor C2, applied to the gate of the transistor T2, constitutes the regulation setpoint of the current source. The voltage across the control capacitor C2 reaching

a certain threshold, the transistor T2 becomes conductive and a bypass current 13 is established in the circuit 4.

As the voltage across the control capacitance C2 decreases below this threshold, the current 13 increases to provide all of the current 11 of the photodetector. Then, the current 12 from the capacitors Cl 'and C2 vanishes and the voltage at their terminals is stabilized. At the end of the initialization phase, the bypass current 13 in the circuit 4 is equal to the current II of the photodetector and therefore to the parasitic current to be compensated.

During the shooting phase, the switches S2 and S3 are open. The control capacitor C2 retains the set voltage to be applied to the transistor T2 while the capacitor C1 'is ready to play its role of integrator. The photodetector observes a useful scene and thus draws a current It composed of the photonic current and the parasitic current. The parasitic current is deflected by the bypass circuit 4, in the form of the current 13 established by the transistor T2, and only the photonic current, in the form of the current 12, is injected into the polarization transistor T1 and integrated by the capacitance. Cl 'integration.

This system allows to derive the parasitic current so that only the useful current is integrated. On the other hand, this circuit is not adapted to more efficient integrating reading circuits, of the type of FIG. 1. FIG. 3 represents a detection circuit embodiment capable of deriving the parasitic current while using a circuit of FIG. performance reading of the "CTIA" type.

The reading circuit 2 of FIG. 1 and the elements of the circuit of FIG. 2, designated by the same references, include the branch circuit 4 and a control circuit 5 'derived from the circuit 5 of FIG. both connected to the photodetector. The detection circuit shown in FIG. 3 further comprises a coupling switch S4 connected in series between the photodetector 1 and an input of the reading circuit 2, and an auxiliary bias circuit 6. Compared to the circuit of FIG. 2, the switch S3 is moved to the other side of the switch S2 and is designated S3 '. Indeed, the integration capacitance Cl, reported in the reading circuit CTIA 2, does not need to be preloaded as the capacitor C1 'in FIG. 2 and the switch S3' only serves to precharge the capacitance C2.

In the example of FIG. 3, the auxiliary bias circuit 6 comprises the biasing transistor Ti connected to the terminal of the photodetector 1 and a second adjustable current source. This second current source is, in this embodiment, constituted by a P type MOS transistor T3 connected to the supply line VDD. The transistor T3 is connected to the control circuit 5 'in the same manner as the transistor T2. Thus, the gate of the transistor T3 is also connected to the control capacitor C2 and the currents of the transistors T2 and T3 are regulated by the same setpoint supplied by the control circuit 5 '.

A second N-type MOS bias transistor T4 is diode-connected between the transistor T3 and a line at the reference potential VREF. The transistor T4 is connected to form a current mirror with the transistor T1 via a switch S5. The gates of the transistors Ti and T4 are therefore connected together via the switch S5. The bias circuit 6 also includes a switch S6, for connecting the gate of the transistor T1 to the supply line VDD.

In a preferred embodiment, the transistors T2 and T3 are identical.

Then, the current 14 in the transistor T3 is equal to the bypass current 13 in the transistor T2. In addition, the first bias transistor T 1 and the second bias transistor T 4 are identical.

In the embodiment of FIG. 3, the control circuit 5 'of the adjustable current sources formed by the transistors T2 and T3 comprises the control capacitor C2. A terminal of the capacitor C2 is connected to the photodetector via the switch S2 and to the supply line VDD via the switch S3 '.

In a preferred embodiment shown in FIG. 4, the branch circuit 4 is connected to the photodetector at a connection point A situated between the coupling switch S4 and the transistor Ti of the bias circuit 6. In this way, the Bypass current 13 passes through the transistor Ti at each instant. The current flowing through this transistor is not canceled during the various phases of operation of the circuit, described below, so that this transistor permanently ensures a polarization of the photodetector 1 during the initialization phase.

Two important states of the detection circuit are distinguished according to the state of the coupling switch S4.

In a first state, when the coupling switch S4 is closed and the switch S1 is open, the reading circuit 2 is connected to the photodetector 1. The reading circuit ensures the polarization of the photodetector by fixing the potential VPD of the terminal of the photodetector. This state corresponds to the shooting phase during which the useful current is integrated, in accordance with what has been described with reference to FIG.

In a second state, when the coupling switch S4 is open, the read circuit is disconnected and no longer provides polarization. The photodetector is then polarized by the polarization circuit 6 which takes the

relay. This state corresponds to the initialization phase during which the current 13 is established to derive the parasitic current. The switch Si is, for example, closed and ensures the reset of the read circuit 2.

The bias circuit 6 is arranged to maintain, in the second state, the polarization of the photodetector terminal at the same reference potential as that imposed by the read circuit 2 during the shooting phase. This reference potential corresponds to the reference of the reading circuit, that is to say the potential VREF applied to the positive input of the amplifier 3.

FIGS. 5A to 5G show, in a simplified manner, timing diagrams of the signals of the detection circuit of FIG. 4, in particular a clock CLK of the circuit and various logic signals controlling the switches S1 to S6. The low state (or logical level `0 ') represents, by way of example, the closed state of the switches.

Figures 6A to 6E, which will be described at the same time, represent voltages and currents at different points of the circuit. Between times t, and t2, the circuit is in an uninitialized state. The photodetector 1 is coupled to the reading circuit 2. The coupling switch S4 is closed (low state, Fig. 5E). The photodetector is then biased by the read circuit. The VPD potential of the photodetector terminal is therefore equal to the reference potential VREF (FIG. 6C).

The switch S3 'is closed (FIG. 5D) in order to load the control capacitor C2 at the supply potential V DD. Thus, the control capacitance C2 is charged to the supply potential VDD, as illustrated by the signal Vc in FIG. 6B. The branch circuit 4 generates no current 13 (13 = 0, Fig. 6D). The photodetector receives a reference flow. He 11

delivers a current I, corresponding to the parasitic current, denoted Is in FIG. 6D.

The bias circuit 6 is deactivated. Switch S5 is open while switch S6 is closed (Fig. 5F and 5G). The switches S5 and S6 are constantly in phase opposition since one controls the polarization of the photodetector by the bias circuit 6 and the second deactivates the circuit 6. The potential VPOL of the gate of the transistor Ti is therefore set at the potential of VDD supply (Fig.6A) via switch S6. 1 o The transistor T1 is then completely conducting, allowing the polarization of the photodetector 1 by the read circuit 2.

Then, the switch S3 'is open at a time t2. C2 ability retains its charge. The initialization step begins at a time t3. At this moment t3, the switch S2 (FIG. 5C) is closed, connecting the control capacitor C2 to the photodetector. The control capacitance C2 gradually discharges and thus the potential Vo decreases (FIG. 6B). At the same time (t3), the coupling switch S4 (FIG. 5E) is open, disconnecting the reading circuit 2. The switch S5 (FIG. 5F) is closed and the switch S6 is open (FIG. 5G). Thus, the polarization of the photodetector is ensured by the polarization circuit 6.

Between the instant t3 and a time t5, that is to say during the establishment phase of the bypass current 13 in the circuit 4, the detection circuit is equivalent to that shown in FIG. potential VPOL on the gate of the transistor Ti is then equal to the reference potential VREF plus the threshold voltage of the transistor T4 (VPOL = VREF + VT; FIG. 6A). The potential VPp 30 at the terminal of the photodetector 1 is then equal to VPOL minus the threshold voltage VT of the transistor Ti. The potential VPp is therefore substantially equal to the potential

VREF. Note in Figure 6C that the VPO potential differs slightly from VREF during this calibration phase. This variation is due to the lapse of time when the current 14 is established in the bias circuit 6. The current 14 is established at the same time as the current 13, since the transistors T2 and T3 are connected to the same setpoint provided by the control circuit 5 '. This period of time therefore corresponds to the time required for the potential on the terminal C of the control capacitor C2 to decrease to the threshold value VDD-V-r of the transistors T2 and T3 (between t3 and t4). During this time, the current 14 is not established and the bias circuit 6 is not yet operational. However, this small variation in the polarization of the photodetector does not significantly modify the current Il of the photodetector 1, which remains equal to the parasitic current Is (FIG. 6D).

At a time t4, the potential Vc has reached the threshold value. The bypass current 13 from the transistor T2 increases rapidly to provide the current 11 of the photodetector, equal to the dark current Is (Fig.6D). The potential Vc then stabilizes at this value (FIG. 6B) since the current II of the photodetector is no longer drawn from the capacitor C2, but is supplied by the bypass circuit 4. In addition, the current 14 is also established and the circuit 6 provides the polarization by precisely fixing the potential VPp to the reference potential (FIG. 6C)

At time t5, the switch S2 (FIG. 5C) is open, thus memorizing the potential Vc on the terminal C of the control capacitor C2, and thereby fixing the bypass current 13. The reading circuit 2 is reconnected to the photodetector 1 by closing the coupling switch S4 (FIG. 5E). The polarization is performed again by the reading circuit 2. The potential VPp of the photodetector terminal is always maintained at the reference potential VREF (FIG. 6C).

The bias circuit 6 is disconnected by rendering the transistor T 1 completely conducting. The potential VPOL of the gate of the transistor Ti is thus again fixed to the supply potential VDD (FIG. 6A) via the switch S6. The switch S6 is closed while the switch S5 is open (respectively Figs.5G and 5F).

The shooting phase starts at a moment ts. The photodetector is placed in front of a useful scene. The photodetector then delivers a current I equal to the parasitic current Is added to a useful current lPD (FIG. 6D). At this instant ts, the reset switch S1 is open (FIG. 5B) to carry out the integration of the useful current I 2 = 1 PD.

Thus, at instant ts, the detection circuit is equivalent to that of FIG. 8. The integrated current IINT takes the value of the useful current IPp (FIG. 6D). Indeed, the parasitic current 13 = IS is deflected by the branch circuit 4. The IPp current being integrated, the signal Vs at the output of the reading circuit 2 increases. This evolution is detected and then processed in another stage, not shown in FIG.

Many variations and modifications of the detection circuit described herein will be apparent to those skilled in the art. In particular, the invention is not limited to a particular type of photodetector. The device described above can be used with a photodiode, a phototransistor or any other type of photodetector, in the visible, infrared or X-ray fields. The nature and the direction of the transistors may be reversed and it is not possible to excluded to use separate power supplies for the various components of the circuit.

Claims (6)

Revendications1. Detection circuit comprising a photodetector (1) connected to a read circuit (2), the reading circuit (2) imposing, in a first state of the detection circuit, a bias voltage of the photodetector, circuit characterized in that it comprises: a coupling switch (S4) connected in series between the photodetector (1) and the read circuit (2), the detection circuit being in said first state when the coupling switch (S4) is closed and in a second state when the coupling switch is open, a bypass circuit (4) arranged to bypass a portion of the current of the photodetector, and an auxiliary bias circuit (6) arranged to maintain, in the second state, said voltage of polarization of the photodetector. 2. Circuit according to claim 1, characterized in that the auxiliary bias circuit (6) comprises a first bias transistor (Ti) connected to the photodetector (1), a second bias transistor (T4) connected to a terminal at a terminal. reference potential (VREF), the second bias transistor (T4) being connected in current mirror with the first bias transistor (Ti) through a bias switch (S5) in said second state. Circuit according to one of Claims 1 and 2, characterized in that the branch circuit (4) is connected to a connection point (A) between the coupling switch (S4) and the bias circuit (6). ). 4. Circuit according to any one of claims 1 to 3, characterized in that the branch circuit (4) comprises a first adjustable current source (T2) and in that the bias circuit (6) comprises a second source adjustable current (T3), the first and second adjustable current sources 14 receiving the same set of a control circuit (5 '). 5. Circuit according to claim 4, characterized in that said setpoint is formed by the voltage across a control capacitor (C2), a terminal of the control capacitor receiving a supply potential (VDD) by the intermediate of a first switch (S2) and being connected to the photodetector via a second switch (S3). 6. A method of operating a photodetector comprising an initialization phase and a shooting phase, the shooting phase comprising: reading the signal from the photodetector by a read circuit, the polarization of the photodetector by the reading circuit, characterized in that the initialization phase comprises: - the disconnection of the photodetector from the read circuit, the establishment of a bypass current, the maintenance of the polarization of the photodetector by an auxiliary polarization circuit; and in that the shooting phase further comprises applying the bypass current to the photodetector.