FR2948810A1 - Static RAM type memory device i.e. portless static RAM memory device, has control unit delivering control signal to gate of transistor of additional cell to place memory-cells in read mode and additional cell in write mode, or conversely - Google Patents

Abstract

The device has a memory plane (PM) comprising a column of static RAM memory cells (CEL). Supply voltage (Vdd) is supplied to bit lines (BLTP, BLFP). A control unit (MC1) sets controllable additional access units (PGT, PGN) in one of two states. Another control unit (MC2) delivers a control signal to a gate of a single access transistor of one of the memory cells of the column and another control signal to a gate of a single access transistor of an additional memory cell (CLS) in order to set the memory-cells in a read mode and the additional cell in a write mode, or conversely. The additional access unit is an N channel type metal-oxide-semiconductor transistor.

Description

13 Ls ... j R - CAS ALONGA & JOSSE Paris - Munich - Alicante - GrenobleTHE EUROPEAN PATENT AND TRADEMARK ATTORNEYS 8, avenue Percier 75008 PARIS Tel. : 33 (0) 1 45 61 94 64 Fax: 33 (0) 1 45 63 94 21 e-mail: paris@casalonga.com APPLICATION FOR PATENT B09-2438EN FZ / EVH 09-GR1-219

So-called limited company: STMicroelectronics SA

Static memory device with five transistors and method of operation Invention of: Lahcen HAMOUCHE Jean-Christophe LAFONT

The invention relates to integrated circuits, and more particularly to static memory devices, of the SRAM type (Static Random Access Memory), with five transistors, said without access port, still commonly known by those skilled in the art under the name of Anglo-Saxon portless SRAM. Memory cells of the SRAM type with five transistors without an access port are well known to those skilled in the art. We can cite in particular the article by Michael Wieckowski and Martin Margala entitled Portless SRAM - A High-Performance Alternative to the 6T Methodology, IEEE Journal of Solid-State Circuits, Volume 42, No. 11, November 2007, or the article of these same authors entitled A Portless SRAM Cell Using Stunted Wordline Drivers, IEEE 2008, pages 584-587. An SRAM-type memory cell without an access port is, as illustrated schematically in FIG. 1, based on the principle of two inverters INV1, INV2, cross-coupled and powered by two BLTP and BLFP bit lines without a port. access, such as for example NMOS transistors. In addition, the SRAM cell comprises a fifth transistor, called access transistor, AXS, connected as illustrated in FIG.

FIG. 2 illustrates a more detailed, but still schematic, representation of the cell of FIG. 1, in which the transistors of the inverters have been represented. More precisely, the CEL cell actually comprises five transistors, namely two pairs of PMOS and NMOS transistors forming the two inverters, as well as the fifth AXS transistor. It can be seen in FIG. 2 that the source of the PMOS transistor M1 is connected to the bit line BLTP, while the source of the PMOS transistor M3 is connected to the line BLFP. The drains of these two transistors Ml and M3 are respectively connected to the drains of the two NMOS transistors M2 and M4. The sources of these two transistors M2 and M4 are connected to ground. Moreover, the gates of the four transistors Ml-M4 are cross-coupled. Finally, the access transistor AXS, which is here an NMOS transistor, is connected between the gates of PMOS transistors Ml and M3. That being this AXS transistor could be a PMOS transistor. Data, formed of two complementary logic values 1.0 or 0.1, is stored between the two output nodes T and F of the two inverters. When the access transistor AXS is open (blocked), the cell CEL is stable and the data is held in this cell as long as the cell remains powered by the supply voltage. When the access transistor AXS is closed (passing), a current flows from the node T or F having the logic value 1 to the node F or T having the logic value 0. A five-transistor SRAM cell without an access port is therefore an alternative to conventional SRAM cells with six transistors, that is to say two inverters connected to the two bit lines by two access ports such as NMOS transistors. To write data in the CEL cell, the two bit lines are first precharged to the supply voltage, the AXS transistor is closed and the voltage of one of the bit lines is dropped depending on whether the it is desired to write a 1 or a 0, so as to cause a voltage difference between the nodes T and F of the cell. Once the data is written, the AXS transistor is reopened and the precharge which supplies the cell necessary for the conservation of the data is reactivated. To read the data in the CEL cell, the AXS transistor is closed. A current difference is then created between the two bit lines, the sign of which depends on the logical value of the stored data item. This current difference is amplified in a conventional manner in a current amplifier located at the bottom of the column of the memory plane containing the cell, and the data is thus read.

Such a conventional column of SRAM memory cells with five transistors without an access port has a number of disadvantages. More specifically, during a write operation, the voltage difference between the two bit lines must be large enough to allow the change of state of the cell to be written, without affecting the stability of the other cells of the same column since all the cells of the column are fed by these lines of bits.

Furthermore, during a read operation, the cell read must induce a current difference between the two bit lines sufficiently large so as to be outside the offset of the current amplifier at the bottom of the column. However, all these constraints are generally incompatible with advanced technologies in which the supply voltage is relatively low, for example 45-nanometer technologies in which the supply voltage is 1.1 volts. According to one embodiment, there is provided a memory device of the type SRAM five transistors without access port to overcome the use of a current amplifier at the bottom of the column. It is also proposed, in particular, a dynamic current memory device, so a lower consumption. It is also proposed, in particular, to perform the write and read operations in the cells by means of a current, which does not require the charges and discharges of the bit lines in the write operations. According to one aspect, there is provided a memory device of the SRAM type, comprising a memory plane having at least one SRAM-type memory cell column comprising two cross-coupled inverters and a single access transistor, each memory being connected between two bit lines without an access transistor.

According to a general characteristic of this aspect, each column of the memory plane further comprises an additional cell, of identical structure to the memory cells of said column, this additional cell being also connected to the two bit lines; the two bit lines are intended to be powered by a supply voltage and the memory device further comprises additional access means, for example NMOS transistors, controllable, connected to said additional cell and having a first state for prohibit access to said additional cell and a second state to allow access to said additional cell so as to store or retrieve data. The device also comprises first control means configured to place the additional access means in their first or in their second state; The memory device also comprises second control means configured for, when the additional access means are in their first state, delivering a first control signal to the gate of the access transistor of one of the memory cells of the column and a second control signal on the gate of the access transistor of the additional cell so as to place said memory cell in a read mode and the additional memory cell in a write mode, or vice versa. Thus, an additional cell located for example at the bottom of the column, identical to the cells of the column, makes it possible to perform both the read operations and the write operations in a selected memory cell of the column. Its role is simply reversed between a read operation and a write operation. More precisely, when a cell to be read, is placed in its reading mode, the additional cell is placed in its writing mode, which will make it possible to copy the opposite (the logical complement) of the data contained in the cell to read. On the other hand, when one has to write data in a cell of the column, the additional cell is then placed in the reading configuration, which will make it possible to copy the opposite of the data it contains in the cell of the column. column to be written. This makes it possible to overcome a current amplifier and thus offset problems related thereto. There is a low dynamic consumption since the read currents of the cell of the column to be read are used for writing in the additional cell. Finally, there is no need to perform bit line loading and unloading at each write operation in a cell of the column. According to one embodiment, the second control means are configured to deliver on the gate of the access transistor of the memory cell, a first voltage as the first control signal so as to turn this access transistor; the second control means are also configured to output a second voltage as a second control signal to the gate of the access transistor of the additional memory cell so as to turn on this access transistor; the first voltage is lower than the second voltage so as to place the memory cell in the read mode and the additional memory cell in the write mode; conversely, the first voltage is greater than the second voltage, so as to place the memory cell in the write mode and the additional memory cell in the read mode.

This difference between the two voltages applied to the access transistors of the memory cell of the selected column and of the additional memory cell makes it possible effectively to place one of the cells in read mode and the other in the first mode. write or vice versa, and thus avoid uncertainty in the behavior of each of the two cells. In order to correct the dispersions related to the technology, in particular vis-à-vis PMOS transistors faster or slower than NMOS transistors, and also to be able to deliver in a simple way the first and second control voltages of the transistors access, it is advantageously provided that the second control means comprise control modules respectively associated with the memory cells of the column and the additional memory cell; each control module comprises for example a gate connected between the supply voltage and the ground, the output of this gate being connected to the gate of the access transistor of the corresponding memory cell, and the gates of the two transistors of the gate being respectively controlled by a read logic signal and a write signal; the control module also comprises a charge pump connected between the supply voltage and the gate of the access transistor via an auxiliary transistor controlled on its gate by the logic write signal. Such an embodiment thus makes it possible, in a very simple way, to deliver to the gate of the access transistor of a memory cell, a voltage lower than the supply voltage when this cell must be in reading mode, and of supplying on the gate of this access transistor a voltage greater than the supply voltage when this cell must be in write mode.

Moreover, in order to further improve the operation of the memory device, and to have a differential large enough to allow the change of state of a cell during a write operation, it is advantageously provided that each inverter of a memory cell, and that each inverter of the additional memory cell, is connected between one of the two bit lines and another bit line intended to be connected to ground. According to another aspect, there is provided a method of reading a data contained in a memory cell of a memory device as defined above, the method comprising a connection of the two bit lines to said voltage of power supply, the placement of additional access means of the additional memory cell in their first state, the placement of the memory cell in its read mode, the placement of the additional memory cell in its write mode, the opposite of the data contained in said memory cell being written in the additional memory cell, placing the additional access means in their second state, and extracting said opposite data from said additional memory cell.

According to another aspect, there is provided a method of writing data in a memory cell of a device as defined above, comprising a connection of the two bit lines to said supply voltage, the placement additional access means of the additional memory cell in their second state, the storage of said data in the additional memory cell, the placement of the additional access means in their first state, the placement of the memory cell in its writing mode, the placement of the additional memory cell in its read mode, the opposite of the data contained in said additional memory cell being written in the memory cell. Other advantages and characteristics of the invention will become apparent on examining the detailed description of embodiments and implementation in no way limiting, and the accompanying drawings, in which: FIGS. 1 and 2, already described, illustrate schematically a memory cell SRAM five transistors without access port according to the prior art; FIG. 3 schematically illustrates an embodiment of a memory device according to the invention; FIGS. 4 and 5 respectively illustrate the main steps of implementation of a reading and writing of a data item in a memory cell of a memory plane column of a memory device according to the invention; and FIG. 6 schematically illustrates, but in more detail, a part of control means of a memory device according to the invention. In FIG. 3, a memory device DM comprises a memory plane PM comprising a matrix of memory cells CEL of the SRAM type with five transistors without an access port such as that illustrated for example in FIG. PM memory therefore comprises memory cell lines and COL columns of memory cells CEL. Only the column COLT is illustrated in detail, the structure of the other columns COLj, COLk being identical to that of column COLi.

As illustrated in FIG. 3, each CEL memory cell of column COLT is connected to the two bit lines BLTP and BLFP. These two bit lines are intended to be connected to the supply voltage Vdd via MPCH means comprising, in this example, two PMOS transistors whose gates are controlled by a logic signal VB. Furthermore, the sources of the transistors M2 and M4 of each of the CEL cells are respectively connected to two other lines of bits BLTN and BLFN intended to be connected to the mass also via the MPCH means, furthermore including, in this regard two NMOS transistors controlled by the logic signal VB. In addition to the GCEL group of CEL memory cells of the column, this column also includes an additional CLS memory cell of identical structure to a CEL memory cell of the GCEL group. This additional memory cell CLS is thus also a static memory cell with five transistors without an access port between the bit lines. In other words, as for the other memory cells, the sources of the PMOS transistors M10 and M30 of the additional cell CLS are directly connected to the two lines of BLTP bits and BLFP without port of access. Moreover, the sources of the NMOS transistors M20 and M40 of the additional cell CLS are also connected in this example to the other two BLTN BLFN bit lines.

Additional means PGT, PGN are provided connected to the two output nodes T and F of the two inverters of the additional cell CLS. These additional access means PGT and PGN here comprise two NMOS transistors respectively controlled on their gate by a control signal SC1. This control signal SC1, according to its value, will make it possible to pass or block the transistors PGT and PGN so as to be able to access the additional cell CLS to either store a datum or extract a datum. The control signal SC1 is delivered by first control means MC1 that can be produced in a conventional manner and known per se, for example by logic circuits. The access transistor AXS of each cell CEL of the memory cell group GCEL is controlled on the gate by a second control signal RWEC which is in fact a voltage delivered on the gate of this access transistor AXS. Similarly, the gate of the transistor AXS of the additional cell CLS receives as a second control signal a voltage RWES. Referring now more particularly to Figure 4, to describe an embodiment of a method of reading a data contained in a CEL memory cell COLi column. In the example described here and illustrated in FIG. 3, it is assumed that a logical 1 is stored in the CEL cell, characterized for example by the presence of a 1 on the node T and a 0 on the node F The CLS cell is isolated from the outside by the PGT and PGN transistors, which are blocked (step 40, FIG. The bit lines BLTP and NLFP are connected to the voltage Vdd via the MPCH means (logic signal VB = 1) while the other bit lines BLTN and BLFN are connected to the ground via the MPCH means ( logic signal VB = 1). The voltage RWEC, which is here a fraction of the supply voltage Vdd (for example a fraction between 70 and 85% of this supply voltage), is applied to the gate of the AXS transistor of the CEL cell (step 41 ). In parallel, a voltage RWES equal to or preferably greater than the voltage Vdd is applied to the gate of the transistor AXS of the CLS cell (step 42). As a result, the CLS cell is less stable than the CEL cell. In other words, the CLS cell is in a write mode while the CEL cell is in a read mode. As a result, as illustrated in FIG. 3, the direction of the current flowing in the transistor AXS (which is conducting) of the cell CEL is opposite to the direction of the current flowing through the transistor AXS of the cell CLS. As in the example illustrated, the node T of the cell CEL is the node high with respect to the node F which is the low node, a reading current Il flows in the cell CEL as illustrated in FIG.

As a result of this read operation, a current differential is created in the bit lines BLTP and BLFP. The CLS cell, less stable than the CEL cell, will therefore induce a current of opposite direction that will flow in the bit lines BLTN and BLFN so as to compensate for this current difference. And, the current I2 flowing in the CLS cell will allow to copy in the CLS cell, the opposite of the data that was stored in the CEL cell (step 43). In other words, the top node of the CLS cell is this time the node F while the bottom node is the node T. Then the PGT and PGN transistors are supplied on the gate with the signal SC1 so as to make these passing transistors (step 44) and extracting from the CLS cell the opposite data which is stored. This opposite datum is for example stored in conventional means and known per se, for example a latch-memory (latch, in English). To write a data in the CEL cell of the COLi column, the role of the CEL and CLS cells is reversed. This is illustrated in particular in FIG.

Firstly, the data intended to be written in the CEL cell is stored in the CLS cell. In this regard, the transistors PGT and PGN are passed through the control signals SC1, and the data is stored in the CLS cell. For example, it is assumed that one will store, as illustrated in FIG. 3, a 1 at the node F and a 0 at the node T. Then, the CLS cell is isolated from the outside by opening (blocking) the PGT transistors and PGN. Then, since the bit lines BLTP and BLFP are powered by the voltage Vdd and the grounded bit lines BLTN and BLFN, a voltage RWES is applied to the gate of the AXS transistor of the CLS cell in order to place this CLS cell. in its read mode, and a RWEC voltage is applied to the gate of the AXS transistor of the CEL cell so as to place it in its write mode.

In this configuration, the voltage RWES is this time lower than the voltage RWEC. The voltage RWES is thus a fraction of the voltage Vdd while the voltage RWEC is this time equal to or preferably greater than the voltage Vdd. This time, therefore, the CEL cell is the least stable.

The mechanism described above for writing in the CLS cell is this time the one used for writing in the CEL cell. At the end of the operation, the data opposite to that contained in the CLS cell is copied (written) into the CEL cell (step 54).

The fact that, internally, there is a logical change in value between the copied data of a CEL cell in the additional cell CLS and vice versa is irrelevant. In fact, in the end, we will find the right data. Indeed, if we want to write a 1 in the CEL cell, we will store a 1 in the CLS cell.

Then, a 0 will be copied into the CEL cell. However, when the cell CEL is read, a cell 1 will in fact be copied to the cell CLS which will then be extracted from this cell CLS by the additional access means PGT and PGN. And we find in the end the value 1 that we wanted to store.

It can thus be seen that the read and write operations are performed with the same circuit, ie the additional cell CLS, without the need to use a current amplifier, which solves the problem of offsets.

On the other hand, the read current of a cell is used to write to the additional cell and vice versa, which leads to a lower dynamic consumption. Finally, there is no charge or discharge of bit lines at each write operation. In the example which has just been described, two other bit lines BLTN and BLFN which are grounded have been used preferentially. However, it would be possible not to use these additional bit lines and simply connect the transistors M2 and M4 of each of the CEL cells and the transistors M20 and M40 of the additional cell to ground.

Nevertheless, the use of additional bit lines BLTN and BLFN makes it possible to further promote the change of state of the CLS cell or of the CEL cell in the write mode. It has been seen above that it was preferable to apply a voltage lower than the supply voltage Vdd, for example a fraction of this supply voltage, to the gate of the transistor AXS of a cell when one wanted this cell to be in reading mode, while it was preferable to apply on the gate of the transistor AXS of this cell a higher voltage, for example a voltage equal to or greater than the supply voltage Vdd, when the it is desired that this cell be in write mode. Under these conditions, it is advantageous to use for each of the CEL or CLS cells, a control module MDCi such as that illustrated in FIG. 6. The set of modules MDCi forms the second control means MC2.

This control module MDCi comprises a gate connected between the supply voltage Vdd and the ground, and comprising a PMOS transistor T7 and an NMOS transistor T8. The output of this gate is connected to the gate of the AXS transistor of the corresponding cell.

The gate of the PMOS transistor T7 is controlled by a read logic signal R while the gate of the NMOS transistor T8 is controlled by a write logic signal W. The module MDCi further comprises, in this example, a charge pump circuit CP, of conventional structure and known per se, connected between the supply voltage Vdd and the gate of the access transistor AXS of the corresponding cell by the intermediate of a PMOS transistor T9 controlled on its gate by the logic signal W. Thus, when we want to read the cell, we assign the logic value 1 to the signal R and the logic value 0 to the signal W. The transistors T7 and T8 are therefore on, the transistor T9 is blocked, and therefore results that the RWEC or RWES voltage is lower than the voltage Vdd. When it is desired to write to the cell, the logical value 1 is assigned to the signal W and the logic value 0 to the signal R, which turns on the transistor T9, blocks the transistors T7 and T8, and provides a higher RWEC or RWES voltage. at the voltage Vdd. Furthermore, the gate T7, T8 makes it possible to compensate for the technological dispersions related to the manufacture of the AXS transistors.

Indeed, it is well known that some transistors can be faster than others. And the gate thus makes it possible to compensate for the fast or slow character of these transistors in reading mode. More precisely if one is in a technological configuration in which the NMOS transistors are fast and the PMOS transistors are slow, the RWEC or RWES voltage delivered at the output of the gate will fall more sharply than if the NMOS and PMOS transistors had the same speed. because transistor T8 is faster than transistor T7. But as the AXS transistor is a NMOS transistor, so fast, this speed is offset by the aforementioned voltage drop. On the other hand, if one is in a technological configuration in which the NMOS transistors are slow and the PMOS fast transistors, the RWEC or RWES voltage delivered at the output of the gate will fall less sharply than if the NMOS and PMOS transistors presented the same speed because transistor T7 is faster than transistor T8. But as the AXS transistor is a NMOS transistor, so slow, this slowness is compensated by the aforementioned voltage drop.

Claims (7)

REVENDICATIONS1. An SRAM type memory device comprising a memory array (PM) having at least one SRAM-type memory cell (COL) column (CEL) having two cross-coupled inverters and a single access transistor, each memory (CEL) being connected between two bit lines (BLTP, BLFP) without access transistors, characterized in that each column of the memory array further comprises an additional cell (CLS), of identical structure to the memory cells ( CEL) of said column, connected to the two bit lines, in that the two bit lines (BLTP, BLFP) are intended to be powered by a supply voltage (Vdd), and in that the device further comprises additional controllable access means (PGT, PGN) connected to said supplementary cell (CLS) and having a first state to prohibit access to said additional cell and a second state to allow access to said cell further for storing or retrieving data therefrom, first control means (MC1) configured to place said additional access means in their first or second state, and second control means (MC2) configured to when the additional access means are in their first state, supplying a first control signal on the gate of the access transistor of one of the memory cells of the column and a second control signal on the gate of the transistor accessing the additional cell to place said memory cell in a read mode and the additional memory cell in a write mode, or vice versa. 2. Device according to claim 1, wherein the second control means (MC2) are configured to deliver on the gate of the access transistor (AXS) of said memory cell (CEL), a first voltage (RWEC) as a that first control signal so as to turn this access transistor, and to deliver on the gate of the access transistor (AXS) of said additional memory cell (CLS), a second voltage (RWES) as second control signal so as to turn on this access transistor, the first voltage being lower than the second voltage so as to place the memory cell in the read mode and the additional memory cell in the write mode, and the first voltage being greater than the second voltage so as to place the memory cell in the write mode and the additional memory cell in the read mode. 3. Device according to claim 1 or 2, wherein the second control means (MC2) comprise control modules (MDCi) respectively associated with the memory cells of the column and the additional memory cell, each control module comprising a gate (T7, T8) connected between the supply voltage and ground and comprising a PMOS transistor and a NMOS transistor connected in series, the output of the gate being connected to the gate of the access transistor (AXS) of the corresponding memory cell, and the gates of the two transistors of the gate are respectively controlled by a read logic signal (R) and a write logic signal (W), and a charge pump (CP) connected between the voltage of d and supplying the gate of said access transistor via an auxiliary transistor (T9) controlled on its gate by the write logic signal (ùW). 4. Device according to one of the preceding claims, wherein each inverter of a memory cell and the additional memory cell is connected between one of the two bit lines and another bit line (BLTN, BLFN). intended to be connected to the ground. 5. Device according to one of claims 1 to 4, wherein the memory plane (PM) comprises several columns. 6. A method of reading a data contained in a memory cell of a device according to one of claims 1 to 5, comprising a connection of the two bit lines to said supply voltage, the placement (40) of additional access means of the additional memory cell in their first state, the placement (41) of the memory cell in its read mode, the location (42) of the additional memory cell in its write mode, the opposite of the data contained in said memory cell being written (43) in the additional memory cell, the placement (44) of the additional access means in their second state, and the extraction (45) of said opposite datum of said cell additional memory. 7. A method of writing data in a memory cell of a device according to one of claims 1 to 5, comprising a connection of the two bit lines to said supply voltage, the placement of the means of additional accesses of the additional memory cell in their second state, the storage (50) of said data in the additional memory cell, the placement (51) of the additional access means in their first state, the placement (CLS) of the memory cell in its write mode, the placement (53) of the additional memory cell in its read mode, the opposite of the data contained in said additional memory cell being written in the memory cell.