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FR2859030B1 - Procede de realisation d'une multiplication modulaire et procede de realisation d'une multiplication euclidienne sur des nombres de 2n bits - Google Patents

Procede de realisation d'une multiplication modulaire et procede de realisation d'une multiplication euclidienne sur des nombres de 2n bits

Info

Publication number
FR2859030B1
FR2859030B1 FR0310060A FR0310060A FR2859030B1 FR 2859030 B1 FR2859030 B1 FR 2859030B1 FR 0310060 A FR0310060 A FR 0310060A FR 0310060 A FR0310060 A FR 0310060A FR 2859030 B1 FR2859030 B1 FR 2859030B1
Authority
FR
France
Prior art keywords
multiplication
euclidian
bits
numbers
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0310060A
Other languages
English (en)
Other versions
FR2859030A1 (fr
Inventor
Marc Joye
Pascal Paillier
Mames Benoit Chevallier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Priority to FR0310060A priority Critical patent/FR2859030B1/fr
Priority to CNA2004800305697A priority patent/CN1867890A/zh
Priority to US10/568,749 priority patent/US20080063184A1/en
Priority to JP2006523661A priority patent/JP2007503036A/ja
Priority to PCT/FR2004/050387 priority patent/WO2005022378A1/fr
Priority to EP04786385A priority patent/EP1656611A1/fr
Publication of FR2859030A1 publication Critical patent/FR2859030A1/fr
Application granted granted Critical
Publication of FR2859030B1 publication Critical patent/FR2859030B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Complex Calculations (AREA)
FR0310060A 2003-08-21 2003-08-21 Procede de realisation d'une multiplication modulaire et procede de realisation d'une multiplication euclidienne sur des nombres de 2n bits Expired - Fee Related FR2859030B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR0310060A FR2859030B1 (fr) 2003-08-21 2003-08-21 Procede de realisation d'une multiplication modulaire et procede de realisation d'une multiplication euclidienne sur des nombres de 2n bits
CNA2004800305697A CN1867890A (zh) 2003-08-21 2004-08-20 执行模乘的方法和用2n位的数执行欧几里德乘法的方法
US10/568,749 US20080063184A1 (en) 2003-08-21 2004-08-20 Method of Performing a Modular Multiplication and Method of Performing a Euclidean Multiplication Using Numbers with 2N Bits
JP2006523661A JP2007503036A (ja) 2003-08-21 2004-08-20 モジュラ乗算を行うための方法、および２ｎビットの数を使用してユークリッド乗算を行うための方法
PCT/FR2004/050387 WO2005022378A1 (fr) 2003-08-21 2004-08-20 Procede de realisation d'une multiplication modulaire et procede de realisation d'une multiplication euclidienne sur des nombres de 2n bits
EP04786385A EP1656611A1 (fr) 2003-08-21 2004-08-20 Procede de realisation d une multiplication modulaire et pro cede de realisation d une multiplication euclidienne sur des nombres de 2n bits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0310060A FR2859030B1 (fr) 2003-08-21 2003-08-21 Procede de realisation d'une multiplication modulaire et procede de realisation d'une multiplication euclidienne sur des nombres de 2n bits

Publications (2)

Publication Number Publication Date
FR2859030A1 FR2859030A1 (fr) 2005-02-25
FR2859030B1 true FR2859030B1 (fr) 2005-11-04

Family

ID=34112838

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0310060A Expired - Fee Related FR2859030B1 (fr) 2003-08-21 2003-08-21 Procede de realisation d'une multiplication modulaire et procede de realisation d'une multiplication euclidienne sur des nombres de 2n bits

Country Status (6)

Country Link
US (1) US20080063184A1 (fr)
EP (1) EP1656611A1 (fr)
JP (1) JP2007503036A (fr)
CN (1) CN1867890A (fr)
FR (1) FR2859030B1 (fr)
WO (1) WO2005022378A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10341803A1 (de) 2003-09-10 2005-04-21 Giesecke & Devrient Gmbh Modulare Multiplikation
JP5027422B2 (ja) * 2006-02-09 2012-09-19 ルネサスエレクトロニクス株式会社 剰余演算処理装置
FR2897964B1 (fr) * 2006-02-28 2017-01-13 Atmel Corp Procede de calcul numerique incluant la division euclidienne
JP2011007820A (ja) * 2007-09-14 2011-01-13 Hitachi Ltd 剰余乗算処理装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5073870A (en) * 1989-01-30 1991-12-17 Nippon Telegraph And Telephone Corporation Modular multiplication method and the system for processing data
US6795553B1 (en) * 1997-11-04 2004-09-21 Nippon Telegraph And Telephone Corporation Method and apparatus for modular inversion for information security and recording medium with a program for implementing the method
DE10107376A1 (de) * 2001-02-16 2002-08-29 Infineon Technologies Ag Verfahren und Vorrichtung zum modularen Multiplizieren und Rechenwerk zum modularen Multiplizieren
US6973470B2 (en) * 2001-06-13 2005-12-06 Corrent Corporation Circuit and method for performing multiple modulo mathematic operations
US7958374B2 (en) * 2002-03-19 2011-06-07 Shansun Technology Company Digital information protecting method and apparatus, and computer accessible recording medium
DE10219161A1 (de) * 2002-04-29 2003-11-20 Infineon Technologies Ag Vorrichtung und Verfahren zum Umrechnen eines Terms
DE10219158B4 (de) * 2002-04-29 2004-12-09 Infineon Technologies Ag Vorrichtung und Verfahren zum Berechnen eines Ergebnisses einer modularen Multiplikation
US7558817B2 (en) * 2002-04-29 2009-07-07 Infineon Technologies Ag Apparatus and method for calculating a result of a modular multiplication
US7461115B2 (en) * 2002-05-01 2008-12-02 Sun Microsystems, Inc. Modular multiplier

Also Published As

Publication number Publication date
JP2007503036A (ja) 2007-02-15
CN1867890A (zh) 2006-11-22
EP1656611A1 (fr) 2006-05-17
WO2005022378A1 (fr) 2005-03-10
US20080063184A1 (en) 2008-03-13
FR2859030A1 (fr) 2005-02-25

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090430