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FR2853425B1 - Sequence de multiplication efficace pour operandes a grands nombres entiers plus larges que le materiel multiplicateur - Google Patents

Sequence de multiplication efficace pour operandes a grands nombres entiers plus larges que le materiel multiplicateur

Info

Publication number
FR2853425B1
FR2853425B1 FR0304299A FR0304299A FR2853425B1 FR 2853425 B1 FR2853425 B1 FR 2853425B1 FR 0304299 A FR0304299 A FR 0304299A FR 0304299 A FR0304299 A FR 0304299A FR 2853425 B1 FR2853425 B1 FR 2853425B1
Authority
FR
France
Prior art keywords
operands
multiplication sequence
larger whole
efficient multiplication
whole entire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0304299A
Other languages
English (en)
Other versions
FR2853425A1 (fr
Inventor
Vincent Dupaquis
Laurent Paris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to FR0304299A priority Critical patent/FR2853425B1/fr
Priority to US10/615,475 priority patent/US7392276B2/en
Priority to EP04759716A priority patent/EP1614027B1/fr
Priority to PCT/US2004/008715 priority patent/WO2004095234A2/fr
Priority to CNB2004800091607A priority patent/CN100489764C/zh
Priority to DE602004023067T priority patent/DE602004023067D1/de
Priority to TW093109455A priority patent/TWI338858B/zh
Publication of FR2853425A1 publication Critical patent/FR2853425A1/fr
Application granted granted Critical
Publication of FR2853425B1 publication Critical patent/FR2853425B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
FR0304299A 2003-04-07 2003-04-07 Sequence de multiplication efficace pour operandes a grands nombres entiers plus larges que le materiel multiplicateur Expired - Fee Related FR2853425B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0304299A FR2853425B1 (fr) 2003-04-07 2003-04-07 Sequence de multiplication efficace pour operandes a grands nombres entiers plus larges que le materiel multiplicateur
US10/615,475 US7392276B2 (en) 2003-04-07 2003-07-07 Efficient multiplication sequence for large integer operands wider than the multiplier hardware
PCT/US2004/008715 WO2004095234A2 (fr) 2003-04-07 2004-03-22 Sequence de multiplication efficace pour de grands operandes entiers de longueur superieure au materiel multiplicateur
CNB2004800091607A CN100489764C (zh) 2003-04-07 2004-03-22 用于比乘法器硬件的位数宽的大整数操作数的有效的乘法序列
EP04759716A EP1614027B1 (fr) 2003-04-07 2004-03-22 Séquence de multiplication efficace pour de grands opérandes entiers de longueur supérieure au matériel multiplicateur
DE602004023067T DE602004023067D1 (de) 2003-04-07 2004-03-22 Effiziente multiplikationssequenz für grosse ganzzahlige operanden, die breiter als die multipliziererhardware sind
TW093109455A TWI338858B (en) 2003-04-07 2004-04-06 Efficient multiplication sequence for large integer operands wider than the multiplier hardware

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0304299A FR2853425B1 (fr) 2003-04-07 2003-04-07 Sequence de multiplication efficace pour operandes a grands nombres entiers plus larges que le materiel multiplicateur

Publications (2)

Publication Number Publication Date
FR2853425A1 FR2853425A1 (fr) 2004-10-08
FR2853425B1 true FR2853425B1 (fr) 2006-01-13

Family

ID=32982290

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0304299A Expired - Fee Related FR2853425B1 (fr) 2003-04-07 2003-04-07 Sequence de multiplication efficace pour operandes a grands nombres entiers plus larges que le materiel multiplicateur

Country Status (7)

Country Link
US (1) US7392276B2 (fr)
EP (1) EP1614027B1 (fr)
CN (1) CN100489764C (fr)
DE (1) DE602004023067D1 (fr)
FR (1) FR2853425B1 (fr)
TW (1) TWI338858B (fr)
WO (1) WO2004095234A2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8538015B2 (en) * 2007-03-28 2013-09-17 Intel Corporation Flexible architecture and instruction for advanced encryption standard (AES)
US8028015B2 (en) * 2007-08-10 2011-09-27 Inside Contactless S.A. Method and system for large number multiplication
CN101271570B (zh) * 2008-05-07 2011-08-17 威盛电子股份有限公司 用于绘图处理单元中的大整数乘法运算的装置和方法
US20110106872A1 (en) * 2008-06-06 2011-05-05 William Hasenplaugh Method and apparatus for providing an area-efficient large unsigned integer multiplier
CN101562594B (zh) * 2009-05-25 2011-09-07 哈尔滨工业大学 基于流水线操作的相位因子结合电路
US8495125B2 (en) * 2009-05-27 2013-07-23 Microchip Technology Incorporated DSP engine with implicit mixed sign operands
EP2365659B1 (fr) * 2010-03-01 2017-04-12 Inside Secure Procédé de test de la résistance d'un circuit intégré à une analyse par canal auxiliaire
EP2761430B1 (fr) 2011-09-27 2015-07-29 Technische Universität Graz Multiplication de grands opérandes
CN106371808B (zh) * 2015-07-22 2019-07-12 华为技术有限公司 一种并行计算的方法及终端
CN115480730A (zh) 2016-10-20 2022-12-16 英特尔公司 用于经融合的乘加的系统、装置和方法
US11599334B2 (en) * 2020-06-09 2023-03-07 VeriSilicon Microelectronics Enhanced multiply accumulate device for neural networks

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240144A (en) 1979-01-02 1980-12-16 Honeywell Information Systems Inc. Long operand alignment and merge operation
JPH061438B2 (ja) * 1984-04-26 1994-01-05 日本電気株式会社 倍精度乗算器
US4809212A (en) 1985-06-19 1989-02-28 Advanced Micro Devices, Inc. High throughput extended-precision multiplier
US4754421A (en) 1985-09-06 1988-06-28 Texas Instruments Incorporated Multiple precision multiplication device
US4876660A (en) 1987-03-20 1989-10-24 Bipolar Integrated Technology, Inc. Fixed-point multiplier-accumulator architecture
US4893268A (en) 1988-04-15 1990-01-09 Motorola, Inc. Circuit and method for accumulating partial products of a single, double or mixed precision multiplication
US5121431A (en) 1990-07-02 1992-06-09 Northern Telecom Limited Processor method of multiplying large numbers
JPH0612229A (ja) 1992-06-10 1994-01-21 Nec Corp 乗累算回路
US5606677A (en) 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
EP0654733B1 (fr) 1993-11-23 2000-05-24 Hewlett-Packard Company Traitement de données en parallèle dans un processeur unique
US5446651A (en) 1993-11-30 1995-08-29 Texas Instruments Incorporated Split multiply operation
US6295599B1 (en) 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
US5953241A (en) 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US6385634B1 (en) 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US5862067A (en) 1995-12-29 1999-01-19 Intel Corporation Method and apparatus for providing high numerical accuracy with packed multiply-add or multiply-subtract operations
DE19637369C2 (de) 1996-09-13 2001-11-15 Micronas Gmbh Digitaler Signalprozessor mit Multipliziereinrichtung und -Verfahren
US5996066A (en) 1996-10-10 1999-11-30 Sun Microsystems, Inc. Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions
US5943250A (en) 1996-10-21 1999-08-24 Samsung Electronics Co., Ltd. Parallel multiplier that supports multiple numbers with different bit lengths
KR100222032B1 (ko) * 1996-12-24 1999-10-01 윤종용 디지탈 신호 처리기에서의 2배 정밀도 곱셈연산 수행방법
US6233597B1 (en) 1997-07-09 2001-05-15 Matsushita Electric Industrial Co., Ltd. Computing apparatus for double-precision multiplication
US6026421A (en) 1997-11-26 2000-02-15 Atmel Corporation Apparatus for multiprecision integer arithmetic
US6202077B1 (en) 1998-02-24 2001-03-13 Motorola, Inc. SIMD data processing extended precision arithmetic operand format
US6055554A (en) 1998-03-04 2000-04-25 Internatinal Business Machines Corporation Floating point binary quad word format multiply instruction unit
US6523055B1 (en) * 1999-01-20 2003-02-18 Lsi Logic Corporation Circuit and method for multiplying and accumulating the sum of two products in a single cycle

Also Published As

Publication number Publication date
CN100489764C (zh) 2009-05-20
CN1809805A (zh) 2006-07-26
TW200504593A (en) 2005-02-01
TWI338858B (en) 2011-03-11
EP1614027B1 (fr) 2009-09-09
WO2004095234A2 (fr) 2004-11-04
US7392276B2 (en) 2008-06-24
EP1614027A4 (fr) 2006-06-21
US20040199562A1 (en) 2004-10-07
DE602004023067D1 (de) 2009-10-22
EP1614027A2 (fr) 2006-01-11
WO2004095234A3 (fr) 2005-11-03
FR2853425A1 (fr) 2004-10-08

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