FR2828332A1 - METHOD FOR ELECTRICAL INSULATION OF CHIPS COMPRISING INTEGRATED CIRCUITS BY DEPOSITING AN INSULATING LAYER - Google Patents
METHOD FOR ELECTRICAL INSULATION OF CHIPS COMPRISING INTEGRATED CIRCUITS BY DEPOSITING AN INSULATING LAYER Download PDFInfo
- Publication number
- FR2828332A1 FR2828332A1 FR0008230A FR0008230A FR2828332A1 FR 2828332 A1 FR2828332 A1 FR 2828332A1 FR 0008230 A FR0008230 A FR 0008230A FR 0008230 A FR0008230 A FR 0008230A FR 2828332 A1 FR2828332 A1 FR 2828332A1
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- Prior art keywords
- chips
- insulating layer
- silica
- mol
- solution
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000000151 deposition Methods 0.000 title claims abstract description 19
- 238000010292 electrical insulation Methods 0.000 title claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000000853 adhesive Substances 0.000 claims abstract description 37
- 230000001070 adhesive effect Effects 0.000 claims abstract description 37
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 28
- 239000007788 liquid Substances 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000002253 acid Substances 0.000 claims abstract description 16
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 12
- 238000005520 cutting process Methods 0.000 claims abstract description 9
- 229920006395 saturated elastomer Polymers 0.000 claims abstract description 7
- 239000012071 phase Substances 0.000 claims description 24
- 239000004327 boric acid Substances 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 11
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 10
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 claims description 9
- 238000007654 immersion Methods 0.000 claims description 7
- 239000007791 liquid phase Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- 238000003756 stirring Methods 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000012298 atmosphere Substances 0.000 claims description 2
- 239000000470 constituent Substances 0.000 claims description 2
- 230000007717 exclusion Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000011093 chipboard Substances 0.000 claims 1
- 239000012530 fluid Substances 0.000 claims 1
- 239000000243 solution Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 7
- 229920001940 conductive polymer Polymers 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 125000005619 boric acid group Chemical group 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 229910003638 H2SiF6 Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000004064 dysfunction Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000006213 oxygenation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 125000005624 silicic acid group Chemical group 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- ZEFWRWWINDLIIV-UHFFFAOYSA-N tetrafluorosilane;dihydrofluoride Chemical compound F.F.F[Si](F)(F)F ZEFWRWWINDLIIV-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
L'invention concerne un procédé d'isolation électrique par le dépôt d'une couche isolante de silice sur les faces latérales de puces comportant circuit (s) intégré (s), faces latérales générées par leur découpe dans une plaque de silicium, elle-même associée à un support adhésif en plastique, qui maintient lesdites puces en position après cette découpe, qui se caractérise en ce que : a - on prépare une phase liquide de traitement formée d'une solution d'acide fluosilicique saturée en silice à e température comprise entre 15 degreC et 35 degreC. b - on immerge les puces disposées sur leur support plastique adhésif dans la phase liquide de traitement. c - on ajoute un agent de provocation de la sursaturation en silice de la phase liquide de traitement. d - on maintient lesdites puces dans le milieu de traitement au plus pendant 10 heures à une température comprise entre environ 15 degreC et environ 50 degreC.The invention relates to a method of electrical insulation by depositing an insulating layer of silica on the lateral faces of chips comprising integrated circuit (s), lateral faces generated by their cutting from a silicon wafer, even associated with an adhesive plastic support, which maintains said chips in position after this cutting, which is characterized in that: a - a liquid treatment phase is prepared formed from a solution of fluosilicic acid saturated with silica at e temperature between 15 degC and 35 degC. b - the chips placed on their adhesive plastic support are immersed in the liquid treatment phase. c - an agent for causing the supersaturation of silica in the liquid treatment phase is added. d - said chips are kept in the treatment medium for at most 10 hours at a temperature of between approximately 15 ° C. and approximately 50 ° C.
Description
transistor MOS.MOS transistor.
: -::: ':: ': -::- -:: ' --: ' -- -:'::: -: : - ::: '::': - :: - - :: '-:' - -: '::: -:
Procédé d' isolation électrique de puces comportant des circuits intégrés par le dépôt d'une couche isolante La présente invention concerne le domaine des puces The present invention relates to the field of chips
S comportant des circuit(s) intégré(s). S with integrated circuit (s).
-- L'invention concerne, plus particulièrement, un procédé d' isolation électrique des faces latérales des plaquettes de silicium sur lesquelles sont disposées des puces comportant des circuit(s) intégré(s), ci-après dénommées "puces", afin que lesdites faces soient isolées lors de - The invention relates, more particularly, to a method of electrical insulation of the lateral faces of the silicon wafers on which chips are arranged comprising integrated circuit (s), hereinafter called "chips", so that said faces are isolated during
l'étape d'assemblage.the assembly stage.
La connexion des dites puces avec un bornier de connexion d'une carte par exemple, peut être réalisée par câblage filaire traditionnel ou par d'autres techniques utilisant des composés polymères conducteurs en contact avec les The connection of said chips with a connection terminal of a card for example, can be carried out by traditional wire wiring or by other techniques using conductive polymer compounds in contact with the
plots de connexion de la puce.chip connection pads.
Mais, les techniques de connexion de puces par des polymères conducteurs établissant un contact entre les plots de connexion de la puce et les pistes de liaison du bornier de connexion sont de plus en plus souvent utilisées, notamment dans le but de diminuer le coût de fabrication des matériaux de circuits intégrés, par rapport à la technologie traditionnelle du câblage filaire qui s'avère coûteuse parce qu'elle nécessite d'une part un appareillage de haute précision pour réaliser les However, techniques for connecting chips with conductive polymers establishing contact between the connection pads of the chip and the connection tracks of the connection terminal block are more and more often used, in particular with the aim of reducing the manufacturing cost. integrated circuit materials, compared to traditional wired cabling technology, which is expensive because it requires on the one hand high-precision equipment to perform the
- -<,.......- - <, .......
-:-- connexions et qu'elle ralentit d'autre part les cadences -: - connections and that it slows down the rates
de fabrication.Manufacturing.
Une première méthode utilisant un composé polymère conducteur pour connecter la puce aux pistes de liaison A first method using a conductive polymer compound to connect the chip to the binding tracks
est illustrée.is illustrated.
Dans un tel cas, les pistes de liaison sont amenées à proximité de l 'emplacement prévu pour la puce. Cette dernière est collée par la face arrière, sur les - pistes de liaison du bornier de connexion, en utilisant une colle isolante électriquement. Cette colle peut être, par exemple, un adhéaif réticulant sous l'effet In such a case, the connecting tracks are brought close to the location provided for the chip. The latter is glued by the rear face, on the - connection tracks of the connection terminal block, using an electrically insulating adhesive. This adhesive can be, for example, a cross-linking adhesive under the effect
d'une exposition à un rayonnement ultra-violet. from exposure to ultraviolet radiation.
Les connexions électriques entre les plots de connexion de la puce et les pistes de liaison sont ensuite réalisées par dépôt d'une résine conductrice qui recouvre les plots de connexion de la puce et les pistes de liaison de la carte. Cette résine conductrice peut être, par exemple, une colle polymérisable chargée en particules conductrices telles The electrical connections between the connection pads of the chip and the connection tracks are then made by depositing a conductive resin which covers the connection pads of the chip and the connection tracks of the card. This conductive resin can be, for example, a polymerizable adhesive loaded with conductive particles such
que des particules d'argent.only silver particles.
Une seconde méthode utilisant un composé polymère conducteur pour connecter la puce aux pistes de liaison est illustrée sur la figure Cette méthode consiste à reporter la puce selon un montage bien connu de type "flip chip". Dans un montage de type "flip chip", la puce est retournée face active avec les plots de connexion, vers le bas. La puce est alors connectée en plagant les plots de connexion sur les pistes de liaison A second method using a conductive polymer compound to connect the chip to the bonding tracks is illustrated in the figure. This method consists in transferring the chip according to a well-known "flip chip" arrangement. In a "flip chip" type assembly, the chip is turned upside down with the connection pads facing down. The chip is then connected by plating the connection pads on the connecting tracks
imprimées à l 'emplacement prévu pour la puce. printed in the space provided for the chip.
Selon cette méthode, la puce est connectée aux pistes de liaison au moyen d'une colle à conduction According to this method, the chip is connected to the connecting tracks by means of a conduction adhesive.
électrique anisotropique bien connue. well-known anisotropic electric.
Ces techniques de connexion de puces par des polymères conducteurs, pour efficaces et performantes qu'elles soient, manifestent toutefois un inconvénient lorsque le substrat utilisé présente une face latérale de faible These techniques for connecting chips with conductive polymers, however effective and efficient they may be, manifest a drawback when the substrate used has a weak side face.
3s résistivité (conducteur).3s resistivity (conductor).
On voit clairement que la résine conductrice couvre les faces latérales de la puce Or, il a été établi que, dans certains cas, une conductivité sur la face latérale de la puce peut entraîner des dysfonctionnements électriques du circuit intégré. En effet, selon les types de substrat utilisé, la S face latérale de la puce est de forte ou de faible résistivité (isolant ou conducteur). Si la face latérale est de forte résistivité, il n'y a aucun problème à ce que It is clearly seen that the conductive resin covers the lateral faces of the chip. However, it has been established that, in certain cases, a conductivity on the lateral face of the chip can cause electrical dysfunctions of the integrated circuit. Indeed, depending on the types of substrate used, the S side face of the chip is of high or low resistivity (insulator or conductor). If the side face is of high resistivity, there is no problem that
la résine conductrice soit en contact avec la tranche. the conductive resin is in contact with the wafer.
Par contre, si le substrat utilisé pour la fabrication de la puce, comportant des circuit(s) intégré(s), présente une face latérale de faible résistivité, cette technique On the other hand, if the substrate used for the manufacture of the chip, comprising integrated circuit (s), has a lateral face of low resistivity, this technique
n'est pas utilisable.cannot be used.
La solution utilisée jusqutà présent consistait tout simplement à ne pas utiliser ce type de technique de connexion avec des puces présentant des flancs conducteurs. Cette solution n'est cependant pas satisfaisante car elle limite fortement -les possibilités de l'assembleur en l'obligeant à utiliser certains The solution used up to now has consisted quite simply in not using this type of connection technique with chips having conductive sides. This solution is however not satisfactory because it greatly limits the possibilities of the assembler by obliging it to use certain
produits avec certaines techniques de montage. products with certain mounting techniques.
En effet, la conductivité du silicium est directement liée au procédé de fabrication des plaquettes et diffère selon les fabricants et les lignes de production. Un utilisateur désirant spécifier une conductivité particulière du substrat se verra alors lié à un fournisseur donné et même à une gamme de produit donné, ce qui entraîne automatiquement un surcoût et une limitation des produits Indeed, the conductivity of silicon is directly linked to the wafer manufacturing process and differs according to the manufacturers and production lines. A user wishing to specify a particular conductivity of the substrate will then be linked to a given supplier and even to a given product range, which automatically results in additional costs and a limitation of the products.
utilisables.usable.
Dès lors, l'objet de la présente invention est de supprimer les inconvénients liés à la connexion des puces comportant circuit(s) intégré(s) par des technologies Therefore, the object of the present invention is to eliminate the drawbacks associated with the connection of chips comprising integrated circuit (s) by technologies
utilisant des polymères conducteurs. using conductive polymers.
C'est pourquoi, l 'invention a pour but de recouvrir les faces latérales desdites puces constituées de silicium, au -4 moyen d'une couche électriquement isolante, par un procédé de dépôt en phase liquide (DPL), et permettre ainsi, par la suite, de réaliser le long et sur ces faces, les connexions électriques entre les plots de connexion de la puce et les pistes de liaison du bornier de connexion. A cet effet, il convient de préciser que, pour que l' isolation des faces latérales des puces puisse être effectuée dans des conditions économiques viables, il est impératif de traiter collectivement ces dites puces alors This is why, the invention aims to cover the lateral faces of said chips made of silicon, by means of an electrically insulating layer, by a liquid phase deposition (DPL) process, and thus allow, by thereafter, to make along and on these faces, the electrical connections between the connection pads of the chip and the connection tracks of the connection terminal block. To this end, it should be specified that, for the insulation of the lateral faces of the chips to be carried out under viable economic conditions, it is imperative to collectively treat these so-called chips.
qu'elles sont disposées sur un support plastique adhésif. that they are arranged on an adhesive plastic support.
A cet égard, il convient de rappeler que les puces comportant des circuits intégrés, sont obtenues par la In this regard, it should be recalled that chips comprising integrated circuits are obtained by
découpe (à la scie diamantée par exemple) d'une plaque- cutting (with a diamond saw for example) of a plate-
substrat (en silicium) les contenant, cette plaque étant substrate (in silicon) containing them, this plate being
solidaire d'un support plastique adbésif. secured to a plastic adhesive support.
Ainsi, les puces, une fois découpées, restent solidaires du support adhésif en plastique et, dès lors, peuvent être Thus, the chips, once cut, remain integral with the plastic adhesive support and, therefore, can be
traitées collectivement.processed collectively.
La nature de la couche isolante est choisie d'une part, de façon à assurer une tension de claquage préférentiellement supérieure ou égale à 20 volts, pour une épaisseur de ladite couche égale ou inférieure à 1 micromètre et, d'autre part, pour permettre une extraction aisée des puces de leur support adhésif après dépôt de la couche isolante. Cette dernière opération est facilitée quand la couche isolante présente une fragilité mécanique convenable au niveau du raccordement des faces verticales The nature of the insulating layer is chosen on the one hand, so as to ensure a breakdown voltage preferably greater than or equal to 20 volts, for a thickness of said layer equal to or less than 1 micrometer and, on the other hand, to allow easy extraction of the chips from their adhesive support after deposition of the insulating layer. This latter operation is facilitated when the insulating layer has suitable mechanical fragility at the connection of the vertical faces.
des puces contigues et du support en plastique. adjoining chips and plastic backing.
Ainsi, l' isolation des faces latérales des puces collées sur leur support plastique doit être réalisée dans des conditions qui, non seulement, respectent l'intégrité des puces, mais aussi, celle du film plastique support, de manière à maintenir la stabilité dimensionnelle de ce - 5 substrat et la qualité du contact adhésif existant entre les puces et leur substrat. Ces deux conditions sont, en effet, nécessaires pour permettre d'une part, un assujettissement précis en position des puces au cours des opérations de dépôt de l'isolant, en garantissant un espace suffisant entre deux puces voisines, et d'autre part, un transfert thermique suffisant entre les puces et, via le support plastique, le porte-substrat, de manière à Thus, the insulation of the lateral faces of the chips bonded to their plastic support must be carried out under conditions which not only respect the integrity of the chips, but also that of the plastic support film, so as to maintain the dimensional stability of ce - 5 substrate and the quality of the adhesive contact existing between the chips and their substrate. These two conditions are, in fact, necessary to allow on the one hand, precise subjection in position of the chips during the operations of depositing the insulator, by guaranteeing a sufficient space between two neighboring chips, and on the other hand, sufficient heat transfer between the chips and, via the plastic support, the substrate holder, so that
éviter tout échauffement indésirable pendant le dépôt. avoid unwanted heating during deposition.
Pour ces différentes raisons, les opérations de dépôt de la couche isolante seront effectuées à une température qui For these various reasons, the operations of depositing the insulating layer will be carried out at a temperature which
ne doit pas dépasser 50 C environ.should not exceed approximately 50 C.
C'est pourquoi, selon l 'invention, le procédé d' isolation électrique par le dépôt d'une couche isolante sur les faces latérales de puces comportant circuit(s) intégré(s), faces latérales générées par leurs découpes dans une plaque de silicium associée à un support adhésif en plastique qui maintient lesdites puces en position après cette découpe, se caractérise en ce que: a - on prépare une phase liquide de traitement formée d'une solution d'acide fluosilicique saturée en silice à This is why, according to the invention, the method of electrical insulation by depositing an insulating layer on the lateral faces of chips comprising integrated circuit (s), lateral faces generated by their cutouts in a plate of silicon associated with a plastic adhesive support which maintains said chips in position after this cutting, is characterized in that: a - a liquid treatment phase is prepared formed from a solution of fluosilicic acid saturated with silica to
une température comprise entre 15 C et 35 C. a temperature between 15 C and 35 C.
2s b - on immerge les puces disposées sur leur support 2s b - immerse the chips placed on their support
plastique adhésif dans la phase liquide de traitement. adhesive plastic in the liquid processing phase.
c - on ajoute un agent de provocation de la sursaturation c - a supersaturation provoking agent is added
en silice de la phase liquide de traitement. in silica from the liquid treatment phase.
d - on maintient les dites puces dans le milieu de traitement au plus pendant 10 heures à une température d - said chips are kept in the treatment medium at most for 10 hours at a temperature
comprise entre environ 15 C et environ 50 C. between about 15 C and about 50 C.
Selon l' invention, la première étape "a" de ce procédé consiste en une saturation en silice de la solution 3s d'acide fluosilicique. La phase liquide de traitement, utilisée comme phase liquide de départ, peut être obtenue par l'ajout, à une solution d'acide fluosilicique (H2SiF6), d'acide silicique (SiO2xH2O) ou de silice (SiO2), à une According to the invention, the first step "a" of this process consists in saturation in silica of the 3s solution of fluosilicic acid. The liquid treatment phase, used as the starting liquid phase, can be obtained by adding, to a solution of fluosilicic acid (H2SiF6), silicic acid (SiO2xH2O) or silica (SiO2)
température d' au plus 35 C.temperature not more than 35 C.
Selon un mode d'exécution particulier de l'invention, la formation de la phase liquide de traitement par aout d'acide silicique ou de silice en quantité appropriée à la solution d'acide fluosilicique s'effectue sous agitation du mélange pendant un temps déterminé à une température souhaitablement comprise entre 15 C et 35 C, suivie d'une filtration, afin d'enlever la silice non dissoute: la solution d'acide fluosilicique saturée en silice est ainsi obtenue. Les conditions de préparation de la phase liquide de traitement peuvent cependant différer selon que l'on ajoute de l'acide silicique ou de la silice à la solution According to a particular embodiment of the invention, the formation of the liquid treatment phase by addition of silicic acid or silica in an amount suitable for the fluosilicic acid solution is carried out with stirring of the mixture for a determined time. at a temperature desirably between 15 ° C. and 35 ° C., followed by filtration, in order to remove the undissolved silica: the solution of fluosilicic acid saturated with silica is thus obtained. The conditions for preparing the liquid treatment phase may, however, differ depending on whether silicic acid or silica is added to the solution.
d'acide fluosilicique.fluosilicic acid.
Quand l'aout est de l'acide silicique, le mélange en préparation est maintenu sous agitation pendant un temps d'au plus 6 heures, mais préférentiellement pendant un temps compris entre 3 et 6 heures, et à une température d'au plus 35 C, mais préférentiellement à une température When the asset is silicic acid, the mixture in preparation is kept under stirring for a time of at most 6 hours, but preferably for a time of between 3 and 6 hours, and at a temperature of at most 35 C, but preferably at a temperature
comprise entre 25 C et 30 C.between 25 C and 30 C.
Quand l'a]out est de la silice, le mélange en préparation est maintenu sous agitation pendant un temps d'au plus 20 heures, mais préférentiellement pendant un temps compris entre 10 et 18 heures, et à une température d' au plus 35OC, mais préférentiellement à une température comprise When the a] out is silica, the mixture in preparation is kept under stirring for a time of at most 20 hours, but preferably for a time of between 10 and 18 hours, and at a temperature of at most 35 ° C. , but preferably at a temperature comprised
entre 23 C et 30 C.between 23 C and 30 C.
Selon l 'invention, l'étape "b" du procédé consiste à immerger, dans la phase liquide de traitement, les puces disposoes sur leur support plastique adhésif, de telle manière que le traitement isolant des faces latérales des According to the invention, step "b" of the method consists in immersing, in the liquid phase of treatment, the chips disposed on their adhesive plastic support, in such a way that the insulating treatment of the lateral faces of the
puces, résultant de leur découpe, se fasse collectivement. chips, resulting from their cutting, is done collectively.
Selon l 'invention, l'étape "c" du procédé consiste à ajouter à la phase liquide du traitement un agent According to the invention, step "c" of the process consists in adding an agent to the liquid phase of the treatment.
provoquant la sursaturation en silice de ladite phase. causing the supersaturation in silica of said phase.
L' introduction de l' agent provoquant la sursaturation en silice de la phase liquide de traitement peut se faire tout au long de l'étape de traitement d'une manière continue et réqulière: cette introduction se fait alors The introduction of the agent causing the supersaturation in silica of the liquid treatment phase can be done throughout the treatment step in a continuous and regular manner: this introduction is then done
en présence des puces préalablement immergées. in the presence of previously immersed fleas.
Mais, l' introduction de l' agent provoquant la sursaturation en silice de la phase liquide de traitement peut se faire en discontinu, par exemple par un seul aj out: cette introduction en un seul aj out peut, soit se faire en présence des puces déjà immergées, soit se faire avant l 'immersion des puces disposées sur leur support However, the introduction of the agent causing the supersaturation in silica of the liquid treatment phase can be carried out batchwise, for example by a single addition: this introduction in a single addition can either be carried out in the presence of the chips already immersed, either before immersion of the chips placed on their support
plastique adbésif dans la phase liquide de traitement. adhesive plastic in the liquid treatment phase.
En tant qu' agent pour provoquer la sureaturation en silice de la phase liquide de traitement, on peut utiliser notamment un réactif choisi dans le groupe constitué par l'acide borique, l'eau ou un métal tel que, par exemple, l'aluminium, mais cet agent est préférentiellement l'acide borique. Lorsque l' agent choisi pour provoquer la sursaturation en silice de la phase liquide de traitement est l'acide borique, on utilise préférentiellement une solution aqueuse d'acide borique de concentration d' environ 0,1 mol/l. Cette solution d'acide borique peut, selon l'invention, être ajoutée gouLte à goutte ou en une seule étape à la phase liquide de traitement. Elle peut par exemple être introduite en une seule étape avant l 'immersion des puces disposées sur leur support plastique As an agent for causing the supereaturation in silica of the liquid treatment phase, use may in particular be made of a reagent chosen from the group consisting of boric acid, water or a metal such as, for example, aluminum , but this agent is preferably boric acid. When the agent chosen to cause the supersaturation in silica of the liquid treatment phase is boric acid, an aqueous solution of boric acid with a concentration of approximately 0.1 mol / l is preferably used. This boric acid solution can, according to the invention, be added dropwise or in a single step to the liquid phase of treatment. It can for example be introduced in a single step before the immersion of the chips placed on their plastic support.
adhésif dans la dite phase liquide. adhesive in the said liquid phase.
La solution d'acide borique est ajoutée de façon à obtenir la concentration en acide borique dans le milieu de traitement nocessaire pour provoquer la sursaturation en silice de la phase liquide de traitement, comprise entre The boric acid solution is added so as to obtain the boric acid concentration in the nocessary treatment medium to cause the supersaturation in silica of the liquid treatment phase, between
0, 01 mol/1 et 0, 02 mol/1.0.01 mol / 1 and 0.02 mol / 1.
Selon l'invention, il est également possible d'ajouter une solution d'acide chlorhydrique dans la phase liquide de traitement, jusqu'à obtenir une concentration de cet acide comprise entre 101 et 10-5 mol/1 dans le milieu de traitement et préférentiellement, une concentration du milieu de traitement en acide chlorhydrique de l'ordre de -3 à 10-4 mol/1. I1 a été, en effet, constaté que l' introduction d'une solution d'acide chlorhydrique dans le milieu de traitement, après l'addition de l' agent provoquant la sureaturation en silice de la phase liquide de traitement permet une augmentation intéressante de la tension de claquage mais également une amélioration de la qualité de la couche isolante déposée se traduisant According to the invention, it is also possible to add a hydrochloric acid solution in the liquid treatment phase, until a concentration of this acid of between 101 and 10-5 mol / 1 is obtained in the treatment medium and preferably, a concentration of the hydrochloric acid treatment medium of the order of -3 to 10-4 mol / 1. It has in fact been found that the introduction of a hydrochloric acid solution into the treatment medium, after the addition of the agent causing the supereaturation in silica of the liquid treatment phase allows an advantageous increase in the breakdown voltage but also an improvement in the quality of the insulating layer deposited resulting in
notamment par une diminution de perte de courant. in particular by a reduction in current loss.
Selon l'étape "d" du procédé de l'invention, on maintient les puces disposées sur leur support plastique adhésif dans le milieu de traitement au plus pendant 10 heures, à une température comprise entre 15 C et 50 C. La vitesse de dépôt de la couche isolante sur les faces latérales des puces selon l' invention dépendant de la température du milieu de traitement. Mais, selon un mode d'exécution préférentiel de l'étape "d" du procédé de l' invention, on maintient le milieu de traitement à une température According to step "d" of the process of the invention, the chips placed on their adhesive plastic support are kept in the treatment medium at most for 10 hours, at a temperature between 15 C and 50 C. The deposition rate of the insulating layer on the lateral faces of the chips according to the invention depending on the temperature of the treatment medium. However, according to a preferred embodiment of step "d" of the process of the invention, the treatment medium is maintained at a temperature
comprise entre 25 C et 50 C.between 25 C and 50 C.
Plus particulièrement et afin d'obtenir une couche isolante suffisante, le temps d' immersion, dans le milieu de traitement, des puces comportant circuit(s) intégré(s), disposées sur leur support plastique adbésif est More particularly and in order to obtain a sufficient insulating layer, the time of immersion, in the treatment medium, of the chips comprising integrated circuit (s), disposed on their adhesive plastic support is
préférentiellement compris entre 1 et 6 heures. preferably between 1 and 6 hours.
Ainsi, au cours du traitement selon le procédé de l 'invention, les faces latérales des puces sont Thus, during the treatment according to the method of the invention, the lateral faces of the chips are
2828332 '2828332 '
recouvertes par une couche électriquement isolante qui est covered by an electrically insulating layer which is
constituée par de l'oxyde de silicium. consisting of silicon oxide.
Selon un mode préférentiel d'exéaution du procédé de s l 'invention, le dépôt de la couche électriquement isolante sur les puces, en particulier sur leurs faces latérales, est contrôlé de façon à obtenir une couche dont l'épaisseur est inférieure ou égale à 1 m. I1 convient toutefois de noter que l'épaisseur de la dite couche est d'au moins de 0,1 m. Préférentiellement, l'épaisseur de la couche isolante déposée selon le procédé de l 'invention According to a preferred mode of emergency of the process of the invention, the deposition of the electrically insulating layer on the chips, in particular on their lateral faces, is controlled so as to obtain a layer whose thickness is less than or equal to 1 m. It should however be noted that the thickness of said layer is at least 0.1 m. Preferably, the thickness of the insulating layer deposited according to the method of the invention
est comprise entre 0,1 et 0,5 m.is between 0.1 and 0.5 m.
Comme explicité précédemment, les puces comportant des circuit(s) intégré(s) possèdent une face avant sur laquelle sont disposés les plots de connexion des puces et une face arrière opposée sur laquelle est disposé le support plastique adhésif. Selon l'invention, les puces peuvent être immergées face avant ou face arrière exposées au milieu de traitement. Selon un mode d'exécution du procédé selon l'invention, les puces découpées dans la plaque de silicium sont en position telle sur leur support plastique adhésif que les faces avant desdites puces sont exposées au milieu de traitement. Cette disposition est possible, à condition que les éléments constitutifs desdites faces avants: soient réalisés en des matériaux inattaquables par le milieu; ou bien, soient protégés dudit milieu par des As explained above, the chips comprising integrated circuit (s) have a front face on which the connection pads of the chips are arranged and an opposite rear face on which the adhesive plastic support is arranged. According to the invention, the chips can be immersed on the front or rear face exposed to the treatment medium. According to one embodiment of the method according to the invention, the chips cut from the silicon wafer are in such a position on their adhesive plastic support that the front faces of said chips are exposed to the treatment medium. This arrangement is possible, provided that the constituent elements of said front faces: are made of materials which cannot be attacked by the medium; or be protected from said environment by
revêtements inattaquables.unassailable coatings.
Selon ce mode d'exéaution particulier du procédé de l'invention, les plots de connexion des puces, très généralement réalisés en alliage à base d'aluminium, peuvent être protégés par un revêtement approprié, tel que par exemple par un revêtement d'or (l'or étant déposé -10 selon des techniques de dépôt bien connues de l'homme du métier) à la condition qu'après le dépôt de ce revêtement protecteur particulier (or), l 'exposition au milieu de traitement des puces selon l' invention soit réalisée sous atmosphère inerte (sous azote par exemple). Dans ces divers cas, le mode d'exéaution du dépôt d' isolation utilise l'intéressante propriété de sélectivité du procédé: l'isolant est déposé sur les faces latérales de la puce à l 'exclusion de tout dépôt sur According to this particular mode of caution of the method of the invention, the connection pads of the chips, very generally made of aluminum-based alloy, can be protected by an appropriate coating, such as for example by a coating of gold (the gold being deposited -10 according to deposition techniques well known to those skilled in the art) on the condition that after the deposition of this particular protective coating (gold), the exposure to the flea treatment medium according to the The invention is carried out under an inert atmosphere (under nitrogen for example). In these various cases, the mode of exéaution of the deposit of insulation uses the interesting property of selectivity of the process: the insulator is deposited on the lateral faces of the chip to the exclusion of any deposit on
les plots de connexion de la face avant. the connection pads on the front panel.
Selon un mode d'exécution du procédé de l 'invention, les puces découpées dans la plaque de silicium et encore disposces sur leur support plastique adhésif sont en position retournée, faces arrières accessibles lors du According to one embodiment of the method of the invention, the chips cut from the silicon wafer and still disposed on their adhesive plastic support are in the inverted position, rear faces accessible during
dépôt de la couche isolante.deposition of the insulating layer.
Cette position retournée des dites plaquettes-puces peut s'effectuer selon la technique décrite ci-dessous La face arrière de la plaque de silicium, opposée à la face avant sur laquelle sont disposés les plots de connexion des puces, est placée sur un support plastique adhésif dégradable aux ultraviolets par exemple. La plaque de silicium est alors découpée selon des méthodes classiques connues et les puces désolidarisées sont maintenues ensemble par l'adhésif Le support plastique adhésif dégradable est alors exposé à un rayonnement ultraviolet, afin de réduire sa This inverted position of said chip cards can be carried out according to the technique described below. The rear face of the silicon plate, opposite to the front face on which the connection pads of the chips are arranged, is placed on a plastic support. adhesive degradable to ultraviolet for example. The silicon wafer is then cut according to known conventional methods and the dissociated chips are held together by the adhesive. The degradable adhesive plastic support is then exposed to ultraviolet radiation, in order to reduce its
force d'adhésion.strength of adhesion.
3s Puis, les plaquettes-puces maintenues par le support plastique adhésif sont placées, face active en contact avec le support, sur un support -. Ce support a essentiellement pour fonction de maintenir les puces de : circuit en cohésion et de permettre leur manipulation 3s Then, the chips-chips maintained by the adhesive plastic support are placed, active face in contact with the support, on a support -. This support essentially has the function of keeping the chips of: circuit in cohesion and of allowing their manipulation
pour l'étape de protection qui suit. for the next protection step.
Le support adhésif de la face arrière, déjà dégradé par le rayonnement ultraviolet, est retiré par pelage par exemple afin de laisser nues les faces arrières des puces. Selon un mode de réalisation préférentiel, le support The adhesive support of the rear face, already degraded by ultraviolet radiation, is removed by peeling for example in order to leave bare the rear faces of the chips. According to a preferred embodiment, the support
est constitué par un autre adhésif dogradable. consists of another dogradable adhesive.
Le support a, en outre, pour fonction de protéger la face active de la puce lors de l' application de The support also has the function of protecting the active face of the chip during the application of
matière isolante.insulating material.
Selon l'invention, le procédé permet de déposer une couche électriquement isolante, sous forme de couche mince, sur les faces latérales et la face arrière des puces placées sur le support Selon un mode de réalisation du procédé de l'invention, préalablement à leur immersion dans le milieu de traitement les puces disposoes sur leur support plastique adhésif peuvent subir un traitement d'oxydation de leur surface afin d' augmenter la réactivité de la surface de plaque de silicium prédécoupée. En effet, il a été constaté que la présence d'oxyde natif à la surface du silicium permettait d'accroître la vitesse de dépôt de la couche isolante. En fait, après découpe des puces, le silicium des faces latérales, en particulier, est le siège de l' apparition d'oxyde natif. Il est possible d' augmenter la réactivité du silicium prédécoupé par des procédés connus tel que l'oxygénation, le plasma oxydant, l' ozone According to the invention, the method makes it possible to deposit an electrically insulating layer, in the form of a thin layer, on the lateral faces and the rear face of the chips placed on the support. According to one embodiment of the method of the invention, prior to their immersion in the treatment medium the chips disposed on their adhesive plastic support can undergo an oxidation treatment of their surface in order to increase the reactivity of the surface of the precut silicon wafer. In fact, it has been observed that the presence of native oxide on the surface of the silicon makes it possible to increase the rate of deposition of the insulating layer. In fact, after cutting the chips, the silicon of the lateral faces, in particular, is the seat of the appearance of native oxide. It is possible to increase the reactivity of the precut silicon by known methods such as oxygenation, oxidizing plasma, ozone
généré ou apporté par lampe ultra-violette. generated or brought by ultraviolet lamp.
En fin de traitement, les puces sont retirées du bain de traitement, puis sont soumises à un rinçage et enfin At the end of treatment, the chips are removed from the treatment bath, then are rinsed and finally
séchées, selon les moyens connus.dried, according to known means.
Les plaquettes-puces traitées selon le procédé de l 'invention possèdent, dès lore, une couche électriquement isolante, qui recouvre ses faces latérales et peut également recouvrir la face arrière. Cette couche isolante selon le procédé de l 'invention est constitute d'oxyde de silicium et son épaisseur est comprise entrè 0,1 Am et 1 m, mais préférentiellement comprise entre 0,1 Am et 0,5 m. -13 The chip cards treated according to the method of the invention have, from lore, an electrically insulating layer, which covers its lateral faces and can also cover the rear face. This insulating layer according to the process of the invention consists of silicon oxide and its thickness is between 0.1 Am and 1 m, but preferably between 0.1 Am and 0.5 m. -13
Claims (21)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0008230A FR2828332A1 (en) | 2000-06-23 | 2000-06-23 | METHOD FOR ELECTRICAL INSULATION OF CHIPS COMPRISING INTEGRATED CIRCUITS BY DEPOSITING AN INSULATING LAYER |
| FR0014753A FR2828333B1 (en) | 2000-06-23 | 2000-11-10 | METHOD FOR ELECTRICAL INSULATION OF CHIPS COMPRISING INTEGRATED CIRCUITS BY DEPOSITING AN INSULATING LAYER |
| AU69235/01A AU6923501A (en) | 2000-06-23 | 2001-06-22 | Electrical insulation of chip wafers by liquid phase sio2 deposition |
| PCT/FR2001/001967 WO2001099172A1 (en) | 2000-06-23 | 2001-06-22 | Electrical insulation of chip wafers by liquid phase sio2 deposition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0008230A FR2828332A1 (en) | 2000-06-23 | 2000-06-23 | METHOD FOR ELECTRICAL INSULATION OF CHIPS COMPRISING INTEGRATED CIRCUITS BY DEPOSITING AN INSULATING LAYER |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2828332A1 true FR2828332A1 (en) | 2003-02-07 |
Family
ID=8851730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0008230A Pending FR2828332A1 (en) | 2000-06-23 | 2000-06-23 | METHOD FOR ELECTRICAL INSULATION OF CHIPS COMPRISING INTEGRATED CIRCUITS BY DEPOSITING AN INSULATING LAYER |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU6923501A (en) |
| FR (1) | FR2828332A1 (en) |
| WO (1) | WO2001099172A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW460604B (en) * | 1998-10-13 | 2001-10-21 | Winbond Electronics Corp | A one-sided and mass production method of liquid phase deposition |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0382139A (en) * | 1989-08-25 | 1991-04-08 | Nec Corp | Element dielectric isolation of semiconductor device |
| CA2131668C (en) * | 1993-12-23 | 1999-03-02 | Carol Galli | Isolation structure using liquid phase oxide deposition |
-
2000
- 2000-06-23 FR FR0008230A patent/FR2828332A1/en active Pending
-
2001
- 2001-06-22 AU AU69235/01A patent/AU6923501A/en not_active Abandoned
- 2001-06-22 WO PCT/FR2001/001967 patent/WO2001099172A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| AU6923501A (en) | 2002-01-02 |
| WO2001099172A1 (en) | 2001-12-27 |
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