FR2826779A1 - ANTISTATIC CONTACT FOR POLYCRYSTALLINE SILICON LINE - Google Patents

Abstract

The present invention relates to an integrated circuit (20) on a silicon substrate (1) comprising at least one polysilicon line (4) and at least one antistatic contact connecting the polysilicon line to the silicon substrate. According to the invention, the antistatic contact (21) comprises a thin oxide layer (22) between the polysilicon line and the silicon substrate. The thin oxide layer is of a thickness sufficiently small for a current to pass through it by tunnel effect when the polysilicon line is brought relative to the substrate to a voltage (V1) greater or less than a determined threshold (Vc1, Vc2 ).

Description

alignment technique by welding.

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  ANTISTATIC CONTACT FOR SILICON LINE

POLYCRI STALL IN

  The present invention relates to integrated circuits and more particularly integrated circuits comprising conductive polysilicon lines.

(polycrystalline silicon).

  In CMOS integrated circuits, polysilicon is used both to make grids of MOS transistors and to create interconnection lines of MOS transistors. Thus, for example, the various conductive lines connecting the floating gate transistors of an electrically erasable and programmable memory, in particular the word lines and grid control lines (memories

  EEPROM), are generally made of polysilicon.

  To make such polysilicon lines, a layer of polysilicon is deposited on the surface of a silicon wafer with the interposition of an oxide layer, and is then etched according to the desired topography ("layout"). Since the polysilicon lines are electrically isolated from the silicon substrate by the oxide layer, they each form the equivalent of a capacitor armature, the other armature of which is

formed by the substrate.

  However, the methods of manufacturing integrated circuits include steps which induce electrostatic charges in the polysilicon lines, in particular steps requiring the use of plasma such as plasma etching steps and dopant implantation steps. Thus, polysilicon lines are often found brought to a high electrical potential due to an accumulation of electrostatic charges, which can reach several tens of Volts. Such electrical potential induces a

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  strong electric field in the regions where the oxide layer is the thinnest, in particular of the gate oxide regions of the MOS transistors. This phenomenon can lead to a degradation of the performance of the MOS transistors or even to the breakdown of the gate oxide. To solve this problem, it is known to protect the polysilicon lines against the accumulation of electrostatic charges by the provision of antistatic contacts. “Antistatic contact” means any means offering a preferred conduction path for the evacuation of these charges, in the form of a weak current which can flow in the polysilicon direction towards the substrate or vice versa without affecting

  the operation of an integrated circuit.

  Figure 1 is a partial sectional view of an integrated circuit 10 during manufacture, and shows a conventional antistatic contact structure 11, also called buried contact. There is a silicon substrate 1, here of type P. on which were formed field oxide fields 2 which respectively delimit an active region A, intended to receive MOS transistor gates, and a non-active region B. The assembly is covered by an oxide layer 3 forming in the active region a gate oxide 3-1, and by a layer of polysilicon 4 forming in the active region a gate material 4-1. Before the deposition of the oxide layer 3, an N + doped region 5 was implanted in the substrate at the level of the zone B. Before the deposition of the polysilicon layer 4, an opening 6 was made in the layer of oxide 3, above the doped region 5. Thus, when the polysilicon layer 4 is deposited, it is in contact with the region 5 via the opening 6, which forms an antistatic contact 11. The region 5 being N + doped, the polysilicon layer 4 is electrically connected to the potential of the substrate 1 by

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  via an NP junction forming a diode. This NP junction prevents the polysilicon from being negatively charged relative to the substrate and, in the case of a positive charge, allows a leakage current to pass which is sufficient to avoid breakdown of the oxide layer in the active region. When the integrated circuit 10 is finished and operational, the polysilicon layer 4 receives a positive voltage, the substrate being brought to ground, the NP junction is reverse biased and its presence does not harm the operation of the integrated circuit. Of course, a PN junction can be provided in place of the NP junction if the polysilicon layer is intended to receive a nagative voltage relative to the substrate when the circuit

1S integrated is operational.

  Although the combination of such an antistatic contact 11 and an NP or PN junction is entirely satisfactory as regards the evacuation of electrostatic charges, the provision of such an antistatic contact in an integrated circuit leads to various

  technological constraints or disadvantages.

  A first disadvantage is that the polysilicon layer 4 must have doping of the same type as region 5, so as not to form with region 5 a parasitic PN junction. It is therefore not possible to provide for doping of another type, even when such

doping is desired.

  Another disadvantage is that the dopants present in the polysilicon layer 4 diffuse in the substrate during annealing phases, and are added to the dopants present in the region 5. There thus occurs a sort of pollution of the substrate by diffusion of dopants in the vicinity of the antistatic contact 11. In practice, this means that the space to be reserved for an antistatic contact must take account of the diffusion of dopants in the vicinity of the antistatic contact, and that the effective size of the contact

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  antistatic in terms of reserved silicon surface

is not negligible.

  Finally, in the context of producing an integrated circuit comprising floating gate transistors, obtaining direct contact between the polysilicon and the substrate (at the doped region 5) requires various processing steps which are add to those of standard manufacturing processes. The purpose of these processing steps is to remove, at the bottom of the opening 6, a layer of tunnel oxide formed on the integrated circuit before the realization of the floating gate transistors. The tunnel oxide layer being formed by oxide growth, it is inevitably found at the bottom of the opening 6 because the growth process

  is not selective, and should therefore be removed thereafter.

  This removal step is complex because a resin mask cannot be deposited directly on the tunnel oxide layer. We must first deposit a layer of polysilicon, etch the layer of polysilicon then use the layer of etched polysilicon as an etching mask for the tunnel oxide present at the bottom of

opening 6.

  Thus, an objective of the present invention is to provide an antistatic contact structure which does not

  not have the disadvantages mentioned above.

  More particularly, the present invention relates to an antistatic contact the production of which requires less processing steps than that of a conventional antistatic contact, in particular in the context of the production of an integrated circuit comprising

floating gate transistors.

  This objective is achieved by providing an integrated circuit on silicon substrate comprising at least one line of polysilicon and at least one antistatic contact connecting the line of polysilicon to the silicon substrate, in which the antistatic contact comprises an oxide layer. end arranged

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  between the polysilicon line and the silicon substrate, the thin oxide layer being of a thickness sufficiently small for a current to pass through it by tunnel effect when the polysilicon line is brought relative to the substrate to a higher voltage or

  below a certain threshold.

  According to one embodiment, the antistatic contact is arranged above a doped region

  forming with the substrate an NP or PN junction.

  According to one embodiment, the thin oxide layer has a thickness of between 0.002 and 0.015 microns. According to one embodiment, the integrated circuit

  includes at least one floating gate transistor.

  According to one embodiment, the floating gate is isolated from the substrate by a layer of tunnel oxide also forming the thin oxide layer of the antistatic contact. According to one embodiment, the integrated circuit forms an electrically erasable and programmable memory. The present invention also relates to a method for manufacturing an integrated circuit, including the manufacture of at least one antistatic contact between a polysilicon line and a silicon substrate, comprising the steps of: growing a first oxide layer on the silicon substrate, make at least one opening in the first oxide layer, grow a second oxide layer at the bottom of the opening, deposit a layer of polysilicon which penetrates into the opening, and etch the layer of polysilicon so as to obtain at least one line of polysilicon extending above the opening, process in which the layer of polysilicon is deposited without prior removal of the second layer of oxide present at the bottom of the opening, the second oxide layer being of a sufficiently small thickness

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  so that a current passes through it by tunnel effect when the polysilicon line is brought relative to the substrate to a voltage higher or lower than a

determined threshold.

  According to one embodiment, the method comprises a step of etching the polysilicon layer so as to simultaneously obtain at least one line of polysilicon extending above the opening and at least one floating gate of a transistor with wire rack

floLtante.

  According to one embodiment, the method comprises a step of implanting dopants in the substrate, in a region lying opposite the opening made in the first oxide layer, to form

  an NP or PN junction relative to the substrate.

  According to one embodiment, the integrated circuit is an erasable and electrically programmable memory. These objects, characteristics and advantages of the present invention will be explained in more detail in the

  following description of an exemplary embodiment of a

  antistatic contact according to the invention and a method for manufacturing such an antistatic contact, made in relation to the attached figures among which: - Figure 1 previously described is a partial sectional view of an integrated circuit comprising a contact conventional antistatic, - Figure 2 is a partial sectional view of an integrated circuit comprising an ant i static contact according to the invention, - Figure 3 is the electrical diagram of the combination of an antistatic contact according to the invention and d an NP junction, FIGS. 4, 5 and 6 represent current-voltage curves which illustrate the electrical properties of an antistatic contact according to the invention, and

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  - Figure 7 is a top view of an integrated circuit comprising an antistatic contact according to the invention, - Figures 8A to 8E illustrate steps of a method

  for manufacturing an integrated circuit according to the invention.

  Figure 2 is a partial sectional view of an integrated circuit 20 comprising an antistatic contact 21 according to the invention. The integrated circuit part shown here is identical to that of FIG. 1, the same elements being designated by the same references. A P-type substrate 1 is found there. Field oxide zones 2 separating an active region A and a non-active region B. an oxide layer 3 deposited on the substrate 1, a polysilicon layer 4 deposited on the oxide layer 3, the oxide layer 3 forming gate oxide 3-1 and the polysilicon layer forming gate material 4-1 in the active area A. The antistatic contact 21 according to the invention, produced in the area B. conventionally comprises an opening 6 formed in the oxide layer 3, into which the polysilicon 4 penetrates. According to the invention, the polysilicon 4 is not in contact with the substrate 1 because the antistatic contact 22 comprises a layer of fine oxide 22 arranged at the bottom of the opening 6, which separates the polysilicon 4 from the substrate 1. Below the oxide layer 22 is conventionally an N + doped region 5

  forming an NP junction with the rest of the substrate.

  According to the invention, the thin oxide layer 22 provides good electrical insulation of the layer of polys i l hereum 4 re laterally to the subst rat 1 when the polysilicon layer 4 receives an electrical voltage of a few volts. However, when the voltage increases following the accumulation of electrostatic charges in the polysilicon layer 4, the thin oxide layer 22 allows a discharge current Ic to pass. Such a current Ic appears by tunnel effect (Fowler-Nordheim effect) and responds to the following relationship:

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  (1) Ic = A Eox2 e (-B / EOx) in which A and B are constants and Eox the field

electric in fine oxide 22.

  S The provision for a conventional NP or PN junction under the antistatic contact 21 according to the invention appears to be essential protection in the event of breakdown of the thin oxide layer 22. If such breakdown occurs, an ohmic contact appears between the polysilicon line 4 and the N + doped region 5 of the substrate 1. The NP or PN junction is reverse biased when the integrated circuit is operational and prevents the appearance of a short circuit between the polysilicon line 4 and the potential of the substrate 1. Ultimately, an antistatic contact according to the invention in which the fine oxide 22 has broken down has substantially the same electrical properties as a conventional antistatic contact. Such an antistatic contact 21 has various advantages. On the one hand, it is not necessary for the polysilicon layer 4 to have the same doping as the region 5 because it is isolated from the latter by the thin oxide layer 22. On the other hand, always thanks to at the fine oxide layer 22, the dopants present in the polysilicon layer 4 do not diffuse in the substrate during annealing phases, and do not add to the dopants present in the region 5. In other words, the localized "pollution" of the substrate by diffusion of dopants in the vicinity of the antistatic contact 21 is lower than in the prior art. The space to reserve for the antistatic contact 21 is therefore lower

than in the prior art.

  Finally, as will be seen below by way of an example, another advantage of such an antistatic contact is that it is simple to obtain in the context of the manufacture of an integrated circuit comprising floating gate transistors, the tunnel oxide layer

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  floating grids that can be used as

thin oxide layer 22.

  Before describing this technological advantage, we will first demonstrate that the combination of the antistatic contact 21 according to the invention and the NP (or PN) junction formed between region 5 and the substrate allows the flow of a current Ic when the polysilicon line 4 is subjected to a high electrostatic voltage. Figure 3 is the electrical diagram of the combination of an antistatic contact according to the invention and an NP junction. The antistatic contact is shown diagrammatically by a tunnel capacitor Ct in series with a diode Dj representing the NP junction. The capacitance Ct receives on its anode a voltage V1, which is considered here as an electrostatic voltage which can appear on a polysilicon line during the manufacture of an integrated circuit. The diode Dj is reverse biased, the cathode of the diode being connected to the cathode of the capacitance Ct. Its anode being to ground (potential of the substrate). The voltage across the capacitor Ct is designated Vc and the voltage across the diode Dj is designated Vd. The sum of the voltages Vc and Vd being equal to the voltage V1 since the two elements

  in series form a voltage divider bridge.

  FIG. 4 represents the current / voltage curve F1 of the tunnel capacitance Ct. Which corresponds to the relation (1) mentioned above, and also represents the current / voltage curve F2 of the diode Djo The curve F1 comprises a half-curve Fll for positive voltages and a half curve F12 for negative voltages. It can be seen that a current begins to flow through the tunnel capacitor Ct when the voltage Vc at its terminals is greater than a positive threshold voltage Vcl or is less than a negative threshold voltage Vc2. Furthermore, the curve F2 of the diode Dj comprises a half-curve F21 for the positive voltages o 2826779 (current curve / conventional voltage of a diode reverse biased) and a half-curve F22 for the negative voltages (current curve / conventional voltage of a diode

polarized in the passing direction).

  To verify that an electrostatic discharge current will flow in the assembly formed by the tunnel capacitance Ct and the diode Dj, let us first consider that a positive voltage V1 greater than Vcl appears in the polysilicon line. For a current to flow, there must be a common operating point between the tunnel capacity Ct and the diode Dj. To verify the existence of such an operating point, the two half-curves F11 and F21 are plotted on the same graph, illustrated in FIG. 5, 1 5 corresponding to the dial of the tensions and positive currents of the figure. 4. In accordance with the rules of the art, the half-curve Fll is transferred to this dial by rotating it 180 around the axis of the currents I (V = O) and then shifting it on the axis of the voltages d 'a value equal to V1. It appears that the half-curves F11 and F21 intersect at an operating point WP1 corresponding to a current Icl. The existence of such an operating point guarantees the flow of electrostatic charges. If the voltage V1 decreases (for example due to the evacuation of the electrostatic charges) the curve Fll moves to the left of the diagram as represented by an arrow and the current Icl remains constant due to the flat shape of the curve F21 ( leakage current in a reverse biased diode). If the voltage V1 continues to decrease, the curve Fll is outside the dial and no longer crosses the curve F21, so that the current of

discharge Ic no longer exists.

  A similar verification can be made by considering that a negative voltage V1 lower than Vc2 appears in the polysilicon line. To ensure that there is a common operating point, the two half curves F12 and F22 are plotted on the same graph, represented in FIG. 6, corresponding to the dial of the negative voltages and currents of FIG. 4. Half-curve F12 is transferred by rotating it 180 around the axis of the currents I (V = 0) then by shifting it on the axis of the voltages by a value

  equal to -V1. Here also, it appears that the half

  curves F11 and F21 have a common operating point WP2 where they intersect, corresponding to a negative current Ic2, which guarantees the flow of electrostatic charges. As the voltage V1 increases and approaches zero (for example due to the evacuation of electrostatic charges), the half-curve F12 disappears towards the right of the dial and

  the current Ic2 decreases until it becomes zero.

  Ultimately, the combination of an antistatic contact according to the invention and an NP or PN junction ensures sufficient flow of electrostatic charges when the voltage V1 appearing in the polysilicon line exceeds a certain threshold Vcl, Vc2. Furthermore, as indicated above, the hypothesis of a possible breakdown of the fine oxide of the antistatic contact does not constitute a drawback since the antistatic contact according to 1 r invent ion then becomes the equivalent a classic antistatic contact. FIG. 7 illustrates an application of the present invention to the protection of polysilicon lines present in the erasable and electrically programmable memories. FIG. 7 very schematically represents, by a top view, the topography of a word line WLi of rank i of an electrically erasable and programmable memory MEM. The word line WLi comprises a plurality of floating gate transistors FGTl-FGTn, ... FGTj-FGT (j + n), ... arranged in columns COL1, ... COLk, ... Each column includes n

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  FGT transistors and each FGT transistor includes a floating gate FG made of polysilicon and a control gate CG. The control grid CG extends above the floating grid FG and is separated from the latter by a layer of grid oxide GOX. The floating grid FG extends over a BLK silicon substrate and is

  separated from it by a TOX tunnel oxide layer.

  The GOX and TOX oxides are marked by hatched lines in the figure but are actually found under

  the control grid CG and under the floating grid FG.

  The CG control grid is a section of a CGL grid control line which passes over the floating grids of all the FGT transistors in the same column. Each transistor FGT is connected to a bit line BL of corresponding rank (BLl-BLn ... BLj-BL (j + n) ...) via an access transistor TA (TA1 TAn .. .TAj-TA (j + n)). The access transistor TA comprises two doped regions D1, D2 forming drain and source regions, extending on either side of a gate GTA made of polysilicon. Between the GTA grid and the substrate

  BLK is a GOX gate oxide.

  In such a memory, the grids GTA of the access transistors TA belonging to the same word line WLi are connected to a common line WLSLi (word line selection line). The WLSLi line is made of polysilicon and passes between regions D1 and D2, o

  it forms the GTA gates of the access transistors TA.

  Such a line WLSLi is of great length relative to the other polysilicon lines because it crosses the entire memory plane horizontally for

  interconnect the GTA grids of the access transistors.

  It behaves like an "antenna" in the presence of electric charges and must be protected against the accumulation of charges which can damage oxides

  of gate GOX of access transistors TA.

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  We thus plan, at one end of the line

  WLSLi, an antistatic contact 21 according to the invention.

  This comprises the doped region 5 described above, implanted in the substrate BLK, and the thin oxide layer 22 extending under the line WLSLi. FIGS. 8A to 8E are sectional views illustrating steps of a method of manufacturing an integrated circuit 50 comprising the joint production of an antistatic contact according to the invention and of a transistor gate with floating gate. Each figure has a left part and a right part - corresponding to different cutting axes, for example an axis Cl-Cl 'represented in figure 7 for the left part of each figure and a cutting axis C2-C2' for the part right of each figure. The thicknesses of the various layers of material are not shown to scale for the sake of readability.

these figures.

  As illustrated in FIG. 8A, regions A1, A2, A3 are first of all delimited on the surface of a silicon substrate 30, here of type P. by virtue of isolation barriers 31 produced by means of a method insulation standard (thick oxide, LOCOS, STI ...). N + doped regions 32-1, 32-2, 32-3 are then implanted in the substrate, respectively in each of the regions A1, A2, A3. Regions 32-2 and 32-3 are shown in dashed lines because they are not in the section plane (such as region D1 or D2 in Figure 7). A gate oxide layer 33 is then formed over the entire substrate by oxide growth. For the sake of clarity of the figure, the oxide 33 located on the isolation barriers 31 is not

not shown.

  In the step illustrated in FIG. 8B, openings 34-1 and 34-3 are made in the oxide layer 33, in the regions A1 and A3, by etching of the oxide layer. A tunnel oxide layer 35 is then formed on the entire substrate, by growth of oxide. The tunnel oxide layer 35 is typically of a thickness of the order of 0.002 to 0.015 microns depending on the manufacturing technology used and the supply voltage that the integrated circuit is intended to receive. The gate oxide layer 33 is of a significantly greater thickness, generally of the order

  a few hundredths of a micrometer.

  For the sake of clarity of the figure, the tunnel oxide 35 formed on the isolation barriers 31 and on the gate oxide layer 33 is not shown, its thickness being negligible, only the tunnel oxide 35 formed at the bottom of the openings 34-1 and 34-3 being shown. At the stage illustrated in FIG. 8C, a layer of polysilicon 36 is deposited on the entire substrate, then is etched to reveal interconnection lines, grids of MOS transistors and floating grids of FGT transistors. In particular, a polysilicon line 36-1 is formed in regions A1 and A2 and a floating grid 36-3 is formed in region A3. The polysilicon line 36-1 extends into the opening 34-1 where it comes into contact with the tunnel oxide 35 extending above the doped trégion substrate 32-1), the assembly thus forming a contact antistatic 21 according to the invention. Thus, during the etching of the polysilicon line 36-1 and the subsequent stages of the manufacturing process, the polysilicon line 36-1 is protected against the accumulation of

electrostatic charges.

  In the step illustrated in FIG. 8D, an insulating layer 37 is formed on the whole of the substrate, by growth or deposition of oxide or an insulator of the ONO (Oxide-Nitride-Oxide) type. An opening 38 is then made in the insulating layer 37, above the

  polysilicon line 36-1, by etching layer 37.

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  In the step illustrated in FIG. 8E, a layer of polysilicon 39 is deposited on the insulating layer 37, then is etched to reveal interconnection lines and control gates of transistors with a floating FGT gate transistor. In particular, a control grid 39-3 is produced above the

  flobLante grid 36-3 and a line 39-1 is carried out

  above line 36-1. Line 39-1 is in contact with line 36-1 through the opening 38 made in the insulating layer 37, and is thus connected to the substrate by means of the antistatic contact 21, which also protects it against accumulation of electrostatic charges. Lines 36-1 and 39-1 form, for example, a word line selection line WLSLi of the type described above (FIG. 7). Line 36-1 also forms, in region A2 and opposite the doped region 32-2, an access transistor gate TA. Ultimately, the manufacture of an antistatic contact according to the invention does not include any step of removing the tunnel oxide and is perfectly integrated into the process of manufacturing an integrated circuit, without requiring any additional treatment step, it being noted that the opening 34-1 in the oxide layer 33 is produced at the same time as the opening 34-3 and other openings of the same type intended to receive the floating gates of the FGT transistors. On the other hand, the realization of a conventional antistatic contact would require the removal of the tunnel oxide 35 located at the bottom of the opening 34-1. To this end, since an etching mask cannot be deposited directly on the tunnel oxide, a layer of polysilicon should first of all be deposited on the tunnel oxide. The polysilicon layer should then be etched so as to obtain, opposite the opening 34-1, another opening forming a mask.

tunnel oxide etching.

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Claims (10)

  1. Integrated circuit (20, 50) on silicon substrate (1, 30) comprising at least one polysilicon line (4, 36-1, 39-1) and at least one antistatic contact connecting the polysilicon line to the substrate silicon, characterized in that the antistatic contact (21) comprises a thin oxide layer (22,) arranged between the polysilicon line and the silicon substrate, the thin oxide layer being of a sufficiently small thickness so that a current (Ic, Icl, Ic2) crosses it by tunnel effect when the polysilicon line (4, 36-1, 39-1) is brought relative to the substrate at a voltage (V1) higher or lower than a determined threshold (Vcl, Vc2) o 2. Integrated circuit according to claim 1, in which the antistatic contact is arranged above a doped region (5, 32-1) forming with the substrate. an NP or PN junction.   3. Integrated circuit according to one of claims 1   and 2, in which the thin oxide layer has a   thickness between 0.002 and 0.015 micrometer.   4. Integrated circuit according to claim 3, comprising at least one gate transistor (FGT) floating (36-3).   5. Integrated circuit according to claim 4, in which the floating grid (36-3) is isolated from the substrate (30) by a tunnel oxide layer (35) forming   also the thin oxide layer of the antistatic contact.   6. Integrated circuit according to one of claims 1   to 5, forming an erasable and programmable memory electrically (MEM). 17 2826779   7. Method for manufacturing an integrated circuit (50), including manufacturing at least one antistatic contact between a polysilicon line (36-1) and a silicon substrate (30), comprising the steps consisting in: - growing a first oxide layer (33) on the silicon substrate (30), - making at least one opening (34-1) in the first oxide layer (33), - growing a second layer of oxide (35) at the bottom of the opening (34-l), - deposit a layer of polysilicon (36) which penetrates into the opening (34-l), and - etch the layer of polysilicon so as to obtain   at least one polysilicon line (36-l) extending over the   above the opening (34-l), characterized in that the polysilicon layer (36) is deposited without prior removal of the second oxide layer (35) present at the bottom of the opening (34-l), and in that the second oxide layer (35) is of a thickness sufficiently small for a current (Ic, Icl, Ic2) to pass through it by tunnel effect when the polysilicon line (36-l) is carried relatively to the substrate at a voltage (Vl) greater than or less than a determined threshold (Vcl, Vc2).   8. The method of claim 7, comprising a step of etching the polysilicon layer so as to simultaneously obtain at least one line of polysilicon (36-l) extending above the opening (34-l) and at least one floating grid (36-3) of one floating gate transistor.   9. Method according to one of claims 7 and 8,   comprising a step of implanting dopants in the substrate, in a region (32-l) lying opposite 1R 2826779   of the opening (34-1) made in the first oxide layer (33), to form a DIP or Pa junction relative to the subsLarL.   10. Proceeds salon one of the claims 7 9, in which the inL6grA (50) circuit is a cabinet