FR2818845A1 - INTEGRATED CIRCUIT COMPRISING A INTERFERENCE CIRCUIT OF DATA RECORDED IN A VOLATILE MEMORY AREA - Google Patents

Abstract

The invention relates to an integrated circuit (MP2) comprising a volatile memory area (DTMEM) whose content has a determined value after a reset of the integrated circuit, the volatile memory area being connected to a data bus (DTB) via the '' intermediary of a scrambling circuit (JMCT) ensuring the coding of the data recorded in the memory area and the decoding of the data read in the memory area, the coding of the data being at least a function of a key (Ks) applied to the circuit jamming. According to the invention, the key applied to the scrambling circuit is a random key delivered by a random signal generator (RGEN) arranged to change the value of the key at least each time the integrated circuit is reset to zero.

Description

l 2818845

  INTEGRATED CIRCUIT COMPRISING AN INTERFERENCE CIRCUIT OF

  DATA STORED IN A VOLATILE MEMORY AREA

  The present invention relates to an integrated circuit comprising a volatile memory area, the content of which has a determined value after resetting the integrated circuit, the volatile memory area being connected to a data bus by means of a scrambling circuit ensuring the coding of the data recorded in the memory zone and the decoding of the data read in the memory zone, the coding of the data being at least

  function of a key applied to the jamming circuit.

  FIG. 1 diagrammatically represents an integrated circuit of the aforementioned type, here forming a microprocessor MP1 (or microcontroller). The integrated circuit comprises a central processing unit CPU, a PMEM program memory, for example an electrically erasable programmable FLASH memory, and a volatile DTMEM memory, generally a RAM type memory, provided for

  save temporary data during a session.

  These elements are connected by a common DTB data bus. A JMCT scrambling circuit is arranged between the DTB data bus and the data input / output of the DTMEM memory. This scrambling circuit comprises a WJM part which ensures the coding of data when they are written to the DTMEM memory, and an RJM part which ensures the decoding of the data when they are read from the DTMEM memory and their application on the data bus. To code data DTin to be recorded in the memory DTMEM, the circuit JMCT receives a fixed key Ks as well as, preferably, additional data DTsup taken at various points of the integrated circuit MP1 (at the choice of the designer). The coded data DTout delivered by the JMCT circuit are of the type:

2 2818845

  DTout = F (DTin, Ks, DTsup) F being the scrambling function performed by the JMCT circuit. The fixed key Ks has a determined number of bits, for example 8, 16 or 32 bits. The scrambling circuit is generally a wired logic circuit of a fairly simple structure, comprising for example Exclusive OR gates arranged to mix the bits of the DTin data with the bits of the key Ks and the bits of the

DTsup data.

  Such an interference circuit generally offers good security against fraudulent reading of data.

  stored in DTMEM memory during a session.

  However, such a jamming circuit has a weakness in terms of security, which appears when the integrated circuit MP1 starts, after a RESET reset signal has been applied to the CPU and to the DTMEM memory. In this case, the entire content of the DTMEM memory is erased and each memory cell

  has an identical value, for example the value "0".

  Thus, there is a risk that a fraudster will take control of the CPU unit at the beginning of an assignment, after the reset of the microprocessor, and proceed to a complete reading of all the contents of the memory. The content of the memory being known after a reset, the RJM part of the scrambling circuit delivers on the data bus DTB decoded data DTout 'which are equal to the transformation of the constant data by the inverse function of the scrambling function . If for example the constant data is equal to "0", the data DTout 'is of the following form: DTout' = F-1 (0, Ks, DTsup) In this case, reading the data DTout 'can make it possible to discover the inverse function F-1 of the

3 2818845

  scrambling function F and therefore discover the scrambling function itself and the key

secret Ks.

  A known solution to overcome this drawback consists in modifying the structure of the memory cells of the DTMEM memory so that they have different content, one relative to the other, after application of the reset signal. So some

  cells are found at "1" and others at "0".

  However, this solution makes the memory architecture more complex due to the differentiation of each memory cell. In addition, despite the differentiation of the default values in the memory cells after reset, the content of the memory is always the same after each reset.

  invention aims to overcome this drawback.

  More particularly, the present invention relates to a means of protection against piracy of an interference circuit associated with a volatile memory area having

  constant content after each reset.

  This objective is achieved by providing an integrated circuit comprising a volatile memory area whose content has a determined value after resetting the integrated circuit, the volatile memory area being connected to a data bus by means of a scrambling circuit ensuring the coding of the data recorded in the memory area and the decoding of the data read in the memory area, the coding of the data being at least a function applied to a key applied to the scrambling circuit, in which the key applied to the circuit jamming is a random key issued by a random signal generator arranged to change the value of the key at least every

  new reset of the integrated circuit.

  According to one embodiment, the random key delivered by the random signal generator is stored in a register via the bus.

4 2818845

  data, register output being applied to the circuit

interference.

  According to one embodiment, the output of the random signal generator is connected directly to the scrambling circuit, so that the random key is applied to the scrambling circuit without

go through the data bus.

  According to one embodiment, the memory area

volatile is RAM memory.

  According to one embodiment, the memory area

  volatile is a bank of registers.

  According to one embodiment, the integrated circuit comprises a RAM memory, a register bank, a first scrambling circuit arranged between the RAM memory and the data bus, and a second scrambling circuit

  arranged between the register bank and the data bus.

  According to one embodiment, the first random signal generator at its output directly connected to the first scrambling circuit without passing through the data bus, and the second random signal generator at its output directly connected to the second scrambling circuit

without going through the data bus.

  According to one embodiment, the integrated circuit comprises a central processing unit and forms a

microprocessor.

  According to one embodiment, the integrated circuit is arranged on a potable support to form a smart card or any other equivalent portable electronic object. These and other objects, features and advantages of the present invention will be explained in more detail.

  detail in the following description of examples of

  realization of an integrated circuit according to the invention, made in relation to the attached figures among which: - FIG. 1 previously described represents an integrated circuit comprising a conventional jamming circuit arranged at the input of a volatile memory area,

2818845

  FIG. 2 schematically represents an exemplary embodiment of an integrated circuit according to the invention comprising a jamming circuit protected against piracy, FIG. 3 represents another exemplary embodiment of an integrated circuit according to the invention, and - Figure 4 shows another embodiment

  of an integrated circuit according to the invention.

  FIG. 2 diagrammatically represents an integrated circuit according to the invention, here a microprocessor MP2 comprising a program memory of the ROM or FLASH type and a DTMEM data memory of the RAM type connected to a

DTB data bus.

  The volatile memory DTMEM is connected to the data bus via a conventional jamming circuit JMCT, comprising a coding part WJM for writing into the memory and a decoding part RJM for reading the memory. The WJM encoder part is active when a WRITE write signal is applied to the memory and the RJM decoder part is active when a READ read signal is applied to the memory. The jamming circuit JMCT receives on an input a jamming key Ks. Optionally but advantageously, the jamming circuit JMCT also receives additional jamming data DTsup

  taken at various points on the microprocessor.

  According to the invention, the jamming key Ks is delivered by a random signal generator RGEN, the output of which is connected to the data bus. After each start of the microprocessor, when an internal or external RESET reset signal has been applied to the CPU unit and to the DTMEM memory, the CPU unit applies to the generator RGEN a signal LTCH causing the emission, at the output of the generator RGEN, of a new key Ks. The new key Ks is stored in a register KREG accessible in writing from the data bus, whose

6 2818845

  output is directly connected to the JMCT jamming circuit. Thus, if a fraudster takes control of the CPU unit by means of a fraudulent program after resetting the microprocessor to zero, reads the entire content of the DTMEM memory and manages to decode the key Ks, this key will not be usable by the following. In fact, when the fraudster will restart a new session by means of an application program provided in the PMEM memory and will seek to decode the data stored in the DTMEM memory by the application program, the key Ks will not be

more the same.

  FIG. 3 represents an embodiment of an MP3 microprocessor according to the invention offering a higher degree of security. Here, the output of the RGEN generator is connected directly to the JMCT jamming circuit, without passing through the DTB data bus. Thus, the new key Ks issued at each new session does not circulate

  in clear on the DTB data bus.

  The signal LTCH applied to the generator RGEN to trigger the emission of a new key Ks, is preferably generated in a hardware manner by the CPU unit so that it cannot be inhibited by manipulation of the operating system of the CPU unit . A specific hardware circuit can also be provided to trigger the

  RGEN circuit after resetting the microprocessor.

  In the embodiment represented in FIG. 4, a microprocessor MP4 according to the invention further comprises a bank of registers RBANK connected to the data bus DTB. This register bank is also formed by volatile memory cells and is equipped with its own JMCT 'jamming circuit arranged between the data bus and its input / output. The key Ks' applied to the second jamming circuit JMCT 'is generated by a second random signal generator RGEN' whose output is here connected directly to the jamming circuit, without passing through the data bus. So,

7 2818845

  each jamming circuit JMCT, JMCT 'has its own secret key Ks, Ks' which changes value each time

new session.

  It will be clear to those skilled in the art that the present invention is capable of various variant embodiments. In particular, in FIG. 4, a random signal generator common to the two scrambling circuits could be provided. Furthermore, other scrambling circuits can be provided at other points of the microprocessor, for example between the data bus and

PMEM program memory.

  The present invention is also susceptible of various applications. The main application aimed here consists in the production of a secure microprocessor intended to be incorporated into a portable object such as a plastic card, to form a smart card or any other portable electronic secure object, for example an electronic label, a badge access control electronics, etc. However, the present invention is generally applicable to any type of secure integrated circuit provided with a volatile memory area capable of containing data, the

  confidentiality must be preserved.

8 2818845

Claims (9)

  1. Integrated circuit (MP2, MP3, MP4) comprising a volatile memory area (DTMEM, REGBANK) whose content has a determined value after resetting the integrated circuit, the volatile memory area being connected to a data bus (DTB ) by means of a scrambling circuit (JMCT, JMCT ') ensuring the coding of the data recorded in the memory zone and the decoding of the data read in the memory zone, the coding of the data being at least a function of a key (Ks, Ks ') applied to the jamming circuit, characterized in that the key applied to the jamming circuit is a random key delivered by a random signal generator (RGEN, RGEN') arranged to change the value of the key at least with each news   reset the integrated circuit.   2. The integrated circuit as claimed in claim 1, in which the random key delivered by the random signal generator is stored in a register (KREG) via the data bus (DTB), the output of the   register being applied to the jamming circuit.   3. The integrated circuit of claim 1, wherein the output of the random signal generator is directly connected to the scrambling circuit, such that the random key is applied to the circuit of   interference without going through the data bus.   4. Integrated circuit according to one of claims 1   to 3, in which the volatile memory area is a memory RAM (DTMEM).   5. Integrated circuit according to one of claims 1   to 3, in which the volatile memory zone is a bank of registers (RBANK). 9 2818845   6. Integrated circuit according to one of claims 4   and 5, comprising a RAM memory (DTMEM), a register bank (RBANK), a first scrambling circuit (JMCT) arranged between the RAM memory and the data bus, and a second scrambling circuit (JMCT ') arranged between   the register bank and the data bus.   7. The integrated circuit as claimed in claim 6, in which the first random signal generator has its output directly connected to the first scrambling circuit without passing through the data bus, and the second random signal generator has its output directly connected to the second circuit interference without passing by the data bus.   8. Integrated circuit according to one of claims 1   to 7, comprising a central processing unit (CPU) and forming a microprocessor.   9. Integrated circuit according to one of claims 1   to 8, arranged on a potable support to form a smart card or any other equivalent electronic portable object.