FR2802684A1 - DISPOSABLE INTEGRATED CIRCUIT CHIP DEVICE AND METHOD FOR MANUFACTURING SUCH A METHOD - Google Patents
DISPOSABLE INTEGRATED CIRCUIT CHIP DEVICE AND METHOD FOR MANUFACTURING SUCH A METHOD Download PDFInfo
- Publication number
- FR2802684A1 FR2802684A1 FR9916026A FR9916026A FR2802684A1 FR 2802684 A1 FR2802684 A1 FR 2802684A1 FR 9916026 A FR9916026 A FR 9916026A FR 9916026 A FR9916026 A FR 9916026A FR 2802684 A1 FR2802684 A1 FR 2802684A1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- chip
- cavity
- circuit chip
- support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
- H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/24998—Reinforcing structures, e.g. ramp-like support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Credit Cards Or The Like (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
Abstract
L'invention concerne un dispositif à puce de circuit intégré comportant un support (14) présentant un plan général (15) et dans lequel débouche un rebord (19) d'une cavité (16), une interface de communication (13) à antenne et/ ou à plages de contact portée par ledit plan, au moins une puce de circuit intégré (11) disposée dans ladite cavité face active vers l'extérieur et connectée à ladite interface par des éléments d'interconnexion (9), ladite puce présentant une face active (20) munie de plots de connexion (21) et délimitée par une arête périphérique (24).Il se distingue en ce que ladite arête périphérique (24) de puce est distante dudit rebord de cavité (19) et en ce que chaque élément d'interconnexion est constituée par un cordon continu (9) de matière électriquement conductrice s'étendant des plots (21) de la puce jusqu'au plan du support.L'invention concerne également un procédé de fabrication du dispositif.The invention relates to an integrated circuit chip device comprising a support (14) having a general plane (15) and into which opens a rim (19) of a cavity (16), a communication interface (13) with antenna. and / or with contact pads carried by said plane, at least one integrated circuit chip (11) arranged in said cavity with the active face outward and connected to said interface by interconnection elements (9), said chip having an active face (20) provided with connection pads (21) and delimited by a peripheral edge (24). It is distinguished in that said peripheral edge (24) of the chip is distant from said cavity rim (19) and in that that each interconnection element is constituted by a continuous bead (9) of electrically conductive material extending from the pads (21) of the chip to the plane of the support. The invention also relates to a method of manufacturing the device.
Description
DISPOSITIF A PUCE DE CIRCUIT INTEGRE JETABLE ETDISPOSABLE INTEGRATED CIRCUIT CHIP DEVICE AND
PROCEDE DE FABRICATION D'UN TEL DISPOSITIF. PROCESS FOR MANUFACTURING SUCH A DEVICE.
La présente invention concerne un dispositif à puce de circuit intégré comportant un support portant une interface de communication à antenne et/ou à plages de contact reliée à une puce de circuit intégré par des The present invention relates to an integrated circuit chip device comprising a support carrying a communication interface with antenna and / or contact pads connected to an integrated circuit chip by
éléments de connexion et un procédé de fabrication d'un tel dispositif. connection elements and a method of manufacturing such a device.
Il vise particulièrement un dispositif bas coût, jetable dont le nombre d'utilisation peut être limité à quelques transactions voire une seule, tql qu'un ticket de transport. Son support pourrait être en une matière de faible résistance mécanique en matière polymère ou non comme une matière It is particularly aimed at a low cost, disposable device, the number of uses of which can be limited to a few transactions or even just one, such as a transport ticket. Its support could be made of a material of low mechanical resistance in polymeric material or not like a material
comportant des fibres naturelles, le papier par exemple. containing natural fibers, paper for example.
Les dispositifs à puce de circuit intégré regroupent généralement les cartes à puce, les étiquettes électroniques, les tickets et peuvent avoir un fonctionnement à contact et/ou à distance par l'intermédiaire d'une interface de communication notamment à antenne ou à capacité. Les dimensions du dispositif peuvent être diverses et variées, supérieures au format carte à puces défini dans la norme ISO 7810 ou inférieures comme le format "Edmundson". Ces dispositifs sont utilisés dans diverses applications notamment des applications de transaction bancaire, d'identification, d'authentification, de fidélité, de porte-monnaie électronique, de téléphonie, de transport ou d'accès etc. L'art antérieur contient la demande de brevet FR 2 736 452 qui concerne un dispositif à bas prix de revient pour un usage unique. Elle décrit une carte intelligente comprenant un corps en matière fibreuse munie Integrated circuit chip devices generally group together smart cards, electronic labels, tickets and can have contact and / or remote operation via a communication interface, in particular with antenna or capacity. The dimensions of the device can be diverse and varied, greater than the smart card format defined in the ISO 7810 standard or smaller like the "Edmundson" format. These devices are used in various applications including banking transaction, identification, authentication, loyalty, electronic wallet, telephony, transport or access etc. applications. The prior art contains patent application FR 2 736 452 which relates to a low cost device for single use. It describes a smart card comprising a body of fibrous material provided
d'une cavité définissant une paroi latérale sur laquelle font saillie des fibres. a cavity defining a side wall on which fibers project.
La cavité est de dimensions appropriées pour retenir une puce de circuit intégré par les fibres. La puce est montée avec sa face active vers l'extérieur de la cavité; des plages de contact et des éléments d'interconnection reliant les plages de contact aux plots de la puce sont réalisées par impression et un vernis protecteur recouvre le circuit intégré The cavity is of appropriate dimensions to retain an integrated circuit chip by the fibers. The chip is mounted with its active face towards the outside of the cavity; contact pads and interconnection elements connecting the contact pads to the studs of the chip are produced by printing and a protective varnish covers the integrated circuit
et les éléments d'interconnexion.and interconnection elements.
Une telle construction a l'inconvénient de présenter des risques de rupture des éléments d'interconnexion lors de la manipulation du dispositif notamment par flexion ou par pression sur le vernis compte tenu de la faible résistance mécanique du support en fibres et du faible maintien de la Such a construction has the disadvantage of presenting risks of rupture of the interconnection elements during the manipulation of the device, in particular by bending or by pressure on the varnish, taking into account the low mechanical resistance of the fiber support and the low retention of the
puce par les fibres.chip by fibers.
La demande de brevet EP-A-0 803 839 concerne un dispositif qui vise également a abaisser le coût de fabrication. Il décrit une carte à circuit intégré comportant un corps polymère dans lequel une puce de circuit intégré est fixée par enfoncement à chaud de manière que ses plots de contact affleurent la surface de la carte. Des spires d'antenne sont déposées notamment par sérigraphie et une couche de résine de protection recouvre la puce et au moins une partie du corps de carte Patent application EP-A-0 803 839 relates to a device which also aims to lower the manufacturing cost. It describes an integrated circuit card comprising a polymer body in which an integrated circuit chip is fixed by hot pressing so that its contact pads are flush with the surface of the card. Antenna turns are deposited in particular by screen printing and a layer of protective resin covers the chip and at least part of the card body
immédiatement adjacente à la puce. immediately adjacent to the chip.
Le procédé décrit ne permet pas des cadences de production élevées qui pourraient conduire à abaisser significativement le coût du dispositif. The method described does not allow high production rates which could lead to significantly lowering the cost of the device.
La présente invention vise à résoudre les problèmes exposés ci- The present invention aims to solve the problems set out above.
dessus. L'objectif de la présente invention est de proposer une structure de dispositif fiable qui puisse être fabriquée par des technologies aptes à reporter et interconnecter des puces à l'interface de communication de manière très précise et à très haute cadence sur un substrat bas coût ou above. The objective of the present invention is to provide a reliable device structure which can be manufactured by technologies capable of transferring and interconnecting chips to the communication interface very precisely and at very high speed on a low cost substrate or
faiblement résistant mécaniquement comme le papier. weak mechanical resistance like paper.
A cet effet, la présente invention a pour objet un dispositif à puce de circuit intégré comportant un support présentant un plan général et dans lequel débouche un rebord d'une cavité, une interface de communication à antenne et/ou à plages de contact portée par ledit plan, au moins une puce de circuit intégré disposée dans ladite cavité face active vers l'extérieur et connectée à ladite interface par des éléments d'interconnexion, ladite puce présentant une face active munie de plots de connexion et délimitée par To this end, the subject of the present invention is an integrated circuit chip device comprising a support having a general plane and into which opens a rim of a cavity, a communication interface with antenna and / or with contact pads carried by said plane, at least one integrated circuit chip disposed in said active face cavity towards the outside and connected to said interface by interconnection elements, said chip having an active face provided with connection pads and delimited by
une arête périphérique.a peripheral edge.
Il se distingue en ce que ladite arête périphérique de puce est distante dudit rebord de cavité et en ce que chaque élément d'interconnexion est constituée par un cordon continu de matière électriquement conductrice s'étendant des plots de la puce jusqu'au plan du support. io Selon un premier mode de réalisation, ladite face active est disposée It is distinguished in that said peripheral edge of the chip is distant from said cavity edge and in that each interconnection element is constituted by a continuous cord of electrically conductive material extending from the studs of the chip to the plane of the support . io According to a first embodiment, said active face is arranged
en dessous du plan général du support. below the general support plane.
Selon un deuxième mode de réalisation, ou une caractéristique According to a second embodiment, or a characteristic
supplémentaire, le dispositif présente un espace autour de la puce. additional, the device has a space around the chip.
Selon d'autres caractéristiques: - la puce est recouverte de matière de protection; - ledit espace comporte de la matière de protection; - ladite matière de protection est comprise dans la cavité; - I'antenne et les éléments de connexions sont réalisées par une même matière homogène électriquement conductrice; - des points de connexion de l'interface sont placés aux abords de la cavité; - la puce est fixée dans la cavité par une matière adhésive isolante électriquement; - ladite matière adhésive s'étend sur le fond de la cavité et comble au moins partiellement l'espace autour de la puce; - le support comporte de la matière fibreuse; La présente invention a également pour objet un procédé de fabrication d'un dispositif à puce de circuit intégré comportant une puce de circuit intégré reliée à une interface de communication à contact et/ou à antenne. Il se distingue en ce qu'il comprend les étapes suivantes selon lesquelles: - on réalise une cavité dans le support de manière que le volume disponible de la cavité soit nettement supérieur à l'encombrement de la puce, - on reporte la puce dans la cavité, de manière que l'arête de sa face active soit distante du plan support; - on dépose des cordons de matière conductrice de la puce au plan du support pour former des éléments d'interconnexion avec According to other characteristics: - the chip is covered with protective material; - said space includes protective material; - said protective material is included in the cavity; - The antenna and the connection elements are made of the same homogeneous electrically conductive material; - interface connection points are placed around the cavity; - The chip is fixed in the cavity by an electrically insulating adhesive material; - Said adhesive material extends over the bottom of the cavity and at least partially fills the space around the chip; - The support comprises fibrous material; The present invention also relates to a method for manufacturing an integrated circuit chip device comprising an integrated circuit chip connected to a contact and / or antenna communication interface. It is distinguished in that it comprises the following stages according to which: - a cavity is produced in the support so that the available volume of the cavity is clearly greater than the size of the chip, - the chip is transferred to the cavity, so that the edge of its active face is distant from the support plane; cords of conductive material of the chip are deposited on the plane of the support to form interconnection elements with
l'interface.the interface.
D'autres particularités et avantages de la présente invention Other features and advantages of the present invention
apparaîtront au cours de la description qui suit, donnée à titre d'exemple will appear during the description which follows, given by way of example
illustratif et non limitatif en référence aux figures dans lesquelles: La figure 1, est un schéma en coupe de l'invention selon un premier mode de réalisation; - La figure 2, représente une coupe du corps support et de la puce; - La figure 3, est un schéma en coupe de l'invention selon un deuxième mode de réalisation; - La figure 4, est un schéma en coupe de l'invention selon illustrative and not limiting with reference to the figures in which: FIG. 1 is a sectional diagram of the invention according to a first embodiment; - Figure 2 shows a section of the support body and the chip; - Figure 3 is a sectional diagram of the invention according to a second embodiment; - Figure 4 is a sectional diagram of the invention according to
un troisième mode de réalisation.a third embodiment.
A la figure 1 et 2, un dispositif 10 à puce de circuit intégré comporte In FIGS. 1 and 2, an integrated circuit chip device 10 comprises
une puce de circuit intégré 11 reliée à une interface de communication 13. an integrated circuit chip 11 connected to a communication interface 13.
Le dispositif peut être quelconque selon l'application, notamment une The device can be any according to the application, in particular a
étiquette électronique ou une carte à puce ou un ticket de transport. electronic label or smart card or transport ticket.
Il comporte un support 14 définissant un plan général 15 dans lequel débouche une cavité 16. La cavité présente un fond 17 et une paroi latérale 18 et une arête périphérique 19 résultant de l'intersection entre le plan général et ladite paroi latérale. Dans l'exemple, le dispositif est un ticket de transport genre ticket de métro en papier ou comportant des fibres en cellulose ou en polymère. Son épaisseur est de l'ordre de 1 mm. La cavité présente une profondeur de 0,6 mm et une largeur de 1,5 mm. Elle peut It comprises a support 14 defining a general plane 15 into which opens a cavity 16. The cavity has a bottom 17 and a side wall 18 and a peripheral edge 19 resulting from the intersection between the general plane and said side wall. In the example, the device is a transport ticket such as a metro ticket made of paper or comprising cellulose or polymer fibers. Its thickness is of the order of 1 mm. The cavity has a depth of 0.6 mm and a width of 1.5 mm. She can
être ronde, ovale, carrée...be round, oval, square ...
La puce 11 (figure 3) présente généralement une face active 20 munie de plots de connexion 21, une face arrière 22 et une tranche 23. La face active est délimitée par une arête périphérique 24 résultant de l'intersection de la tranche avec la face active. Elle est par exemple de l'ordre de 0,5 mm de côté avec une épaisseur pouvant aller notamment de The chip 11 (FIG. 3) generally has an active face 20 provided with connection pads 21, a rear face 22 and a wafer 23. The active face is delimited by a peripheral edge 24 resulting from the intersection of the wafer with the face active. It is for example of the order of 0.5 mm on a side with a thickness which can range in particular from
O 10 pm à 400 pm.O 10 pm to 400 pm.
Comme on l'a compris, le volume offert par la cavité doit être nettement supérieur à l'encombrement de la puce contrairement à l'art As we have understood, the volume offered by the cavity must be significantly greater than the size of the chip, unlike art
antérieur, par exemple supérieur à 1,10 de préférence 1,25 fois. anterior, for example greater than 1.10, preferably 1.25 times.
L'interface de communication 13 est disposée sur le plan 15 de son support 14 pour communiquer avec un lecteur approprié par contact ohmique ou par ondes électromagnétiques. L'interface peut donc être notamment une antenne et/ou un bornier de contact de carte à puce ou The communication interface 13 is arranged on the plane 15 of its support 14 to communicate with an appropriate reader by ohmic contact or by electromagnetic waves. The interface can therefore be in particular an antenna and / or a smart card contact terminal or
une capacité.a capacity.
Selon l'invention, comme visible à la figure 1, la puce est disposée dans la cavité face active vers l'extérieur, c'est-à-dire dirigée à l'opposé du fond de la cavité. En l'occurrence dans l'exemple, la puce est fixée au fond According to the invention, as visible in FIG. 1, the chip is placed in the cavity with the active face outward, that is to say directed opposite the bottom of the cavity. In this case in the example, the chip is fixed to the bottom
de la cavité par sa face arrière à l'aide d'une matière adhésive isolante 12. of the cavity by its rear face using an insulating adhesive material 12.
Selon l'invention encore, ladite arête périphérique de puce 24 est distante dudit rebord de cavité. La signification de distante est illustrée successivement en référence aux exemples et ultérieurement en référence According to the invention also, said peripheral edge of chip 24 is distant from said cavity edge. The meaning of remote is illustrated successively with reference to the examples and later with reference
au procédé.to the process.
Dans l'exemple, l'arête 24 est distante parce qu'elle est disposée en dessous du plan général du support. La différence de niveau est In the example, the edge 24 is distant because it is arranged below the general plane of the support. The difference in level is
notamment de l'ordre de 0,25 mm.in particular of the order of 0.25 mm.
Ainsi, la puce est à l'abri d'une éventuelle pression d'un doigt qui pourrait être exercée sur la surface de la puce provoquant son Thus, the chip is protected from a possible pressure of a finger which could be exerted on the surface of the chip causing its
déplacement et endommageant ses connexions. moving and damaging its connections.
En alternative, ou cumulativement comme dans l'exemple de la figure 3, le dispositif peut présenter un espace 25 autour de la puce entre la tranche de celle-ci et la paroi de la cavité. Cet espace est libre au moins partiellement de fibres éventuelles dans le cas o le support serait en As an alternative, or cumulatively as in the example in FIG. 3, the device can have a space around the chip between the edge thereof and the wall of the cavity. This space is at least partially free of any fibers in the case where the support is in
matière fibreuse comme dans l'art antérieur cité. fibrous material as in the cited prior art.
Contrairement à l'art antérieur, dans l'invention, de telles fibres o0 éventuelles n'atteindraient pas la tranche de la puce et ne la Unlike the prior art, in the invention, such fibers o0, if any, would not reach the edge of the chip and would not
maintiendraient pas en place dans la cavité. not hold in place in the cavity.
Selon l'invention, les plots de la puce sont connectés à l'interface par des éléments d'interconnexion constitués chacun d'un cordon de matière 9 électriquement conductrice. La matière du cordon est homogène dans le sens o c'est le même cordon continu en une même matière qui s'étend des plots de la puce jusqu'au rebord de la cavité voire au-delà sur le plan du support jusqu'à rencontrer des points de connexion de l'interface placés aux abords de la cavité ou jusqu'à former l'interface de communication sur According to the invention, the studs of the chip are connected to the interface by interconnection elements each consisting of a cord of electrically conductive material 9. The cord material is homogeneous in the sense that it is the same continuous cord in the same material which extends from the studs of the chip to the edge of the cavity or even beyond on the plane of the support until it meets interface connection points placed around the cavity or to form the communication interface on
le plan 15.plan 15.
Pour une meilleure protection, la puce peut être recouverte de matière de protection 26, par exemple une résine d'enrobage couramment utilisée dans le domaine de la carte à puce. La matière de protection a pour effet de renforcer l'ensemble constitué par la puce et l'interconnexion aux For better protection, the chip can be covered with protective material 26, for example a coating resin commonly used in the field of the smart card. The protective material has the effect of reinforcing the assembly constituted by the chip and the interconnection to
plots à l'intérieur de la cavité. studs inside the cavity.
La matière de protection peut également ou alternativement à la The protective material can also or alternatively to the
fonction ci-dessus remplir ou venir compléter l'espace 25 autour de la puce. above function fill or complete the space 25 around the chip.
La matière peut adhérer à la paroi 18 de la cavité et avoir ainsi notamment pour fonction d'accrocher à la paroi et d'empêcher un déplacement de la puce dans la cavité quand elle est soumise à une force résultant d'une éventuelle pression transversale au plan 15. Cette fonction ci-dessus peut être, le cas échéant, réalisée totalement ou partiellement par la matière adhésive isolante 12 qui comblerait l'espace 25 au moins en partie en remontant vers le plan sous l'effet de la pression de report et de collage de The material can adhere to the wall 18 of the cavity and thus have in particular the function of hanging on the wall and of preventing a displacement of the chip in the cavity when it is subjected to a force resulting from a possible transverse pressure at the plane 15. This above function can be, if necessary, carried out totally or partially by the insulating adhesive material 12 which would fill the space 25 at least in part by going up towards the plane under the effect of the transfer pressure and collage
la puce.the chip.
On remarque dans l'exemple, que ladite matière 12, 26 est de préférence comprise dans la cavité, c'est-à-dire qu'elle ne déborde pas sur le plan du support ni sur les extrémités d'antenne; sa hauteur est de préférence maintenue en deçà du niveau supérieur de l'interface, l'avantage étant d'éviter d'avoir des surépaisseurs inutiles qui pourraient It will be noted in the example, that said material 12, 26 is preferably included in the cavity, that is to say that it does not extend beyond the plane of the support nor onto the antenna ends; its height is preferably kept below the upper level of the interface, the advantage being to avoid having unnecessary extra thicknesses which could
gêner l'introduction des dispositifs dans des lecteurs. hinder the introduction of devices into readers.
A la figure 3, le dispositif selon le deuxième mode de réalisation comporte une puce de circuit intégré 11 dont la surface active 20 se situe In FIG. 3, the device according to the second embodiment comprises an integrated circuit chip 11 whose active surface 20 is located
sensiblement au même niveau que le plan 15 du support. substantially at the same level as the plane 15 of the support.
Selon l'invention, ladite arête périphérique 24 de la puce est distante dudit rebord de cavité du fait de l'espace ménagé autour de la puce. Dans l'exemple, I'espace est de l'ordre de 0,25 mm. L'avantage d'un tel espace est de favoriser le report de la puce par une opération classique de report de puce dite "die attach". La cadence du report est d'autant plus importante que la tolérance de positionnement et/ou d'indexation des puces par rapport à la cavité est peu contraignante. L'avantage est également de faciliter l'introduction d'une matière dans l'espace non occupé La puce comporte comme précédemment une matière adhésive au fond de la cavité pour fixer la puce. La matière remplie également en grande partie l'espace autour de la puce ce qui favorise son accrochage à According to the invention, said peripheral edge 24 of the chip is distant from said cavity rim due to the space provided around the chip. In the example, the space is of the order of 0.25 mm. The advantage of such a space is to promote the transfer of the chip by a conventional chip transfer operation called "die attach". The rate of the transfer is all the more important as the tolerance of positioning and / or indexing of the chips relative to the cavity is not very restrictive. The advantage is also to facilitate the introduction of a material into the unoccupied space. The chip comprises, as before, an adhesive material at the bottom of the cavity for fixing the chip. The material also largely fills the space around the chip which favors its attachment to
la paroi de la cavité.the wall of the cavity.
Une matière de protection, facultative couvre de préférence la face active de la puce et sur les cordons d'interconnexion aux plots 21 tout en An optional protective material preferably covers the active face of the chip and on the interconnection cords to the pads 21 while
restant de préférence dans le périmètre formées par l'arête 19 de la cavité. preferably remaining within the perimeter formed by the edge 19 of the cavity.
Ce produit jetable, décrit précédemment, peut si nécessaire avoir une faible épaisseur de I 'ordre de 200 à 400pm. L 'utilisation de substrats This disposable product, described above, can if necessary have a thin thickness of the order of 200 to 400 μm. The use of substrates
bas coût est ici envisageable.low cost is possible here.
A la figure 4, selon un troisième mode de réalisation, la puce possède sensiblement la largeur de la cavité. Elle est distante du rebord de la cavité du fait que sa face active est située à un niveau inférieur à celui du plan du support. Bien que facultatif, la puce est fixée au fond par un adhésif et est protégée par de la matière d'enrobage. Dans cet exemple, les éléments d'interconnexion 9 s'étendent des plots jusqu'au plan o ils sont In FIG. 4, according to a third embodiment, the chip has substantially the width of the cavity. It is distant from the edge of the cavity because its active face is located at a level below that of the plane of the support. Although optional, the chip is attached to the bottom by an adhesive and is protected by coating material. In this example, the interconnection elements 9 extend from the pads to the plane where they are
prolongés par une interface de communication à antenne. extended by an antenna communication interface.
Le procédé de fabrication du dispositif peut être mis en oeuvre de la manière ci-après. Selon l'invention, le procédé comporte une étape selon laquelle, on réalise une cavité dans le support de manière que le volume disponible soit nettement supérieur à l'encombrement de la puce; Cela peut signifier d'avoir une cavité beaucoup plus large que les dimensions de la puce, par exemple 1,5 à 4 fois plus large, et/ou plus profonde de manière à offrir un dénivelé en la face active de la puce et le plan du support The device manufacturing process can be implemented in the following manner. According to the invention, the method comprises a step according to which a cavity is produced in the support so that the available volume is significantly greater than the size of the chip; This can mean having a much wider cavity than the dimensions of the chip, for example 1.5 to 4 times wider, and / or deeper so as to provide a difference in level on the active face of the chip and the plane support
supérieur à 50 pm, de préférence égal à environ 100 pm. greater than 50 µm, preferably equal to about 100 µm.
Puis, on reporte la puce dans la cavité, de manière que l'arête de sa face active soit distante du plan support; Plusieurs cas présentés aux figures et décrits précédemment peuvent se produire: Un premier cas extrême de la figure 4, o la puce est très en deçà du niveau du support, les parois latérales étant quasiment contre celles de la puce, présente l'avantage d'être très résistant à l'encontre des forces de pression qui seraient exercées par un doigt compte tenu de l'inaccessibilité de la puce. Ce cas peut toutefois présenter un handicap de requérir une Then, the chip is transferred into the cavity, so that the edge of its active face is distant from the support plane; Several cases presented in the figures and described above can occur: A first extreme case of Figure 4, where the chip is very below the level of the support, the side walls being almost against those of the chip, has the advantage of be very resistant against the pressure forces which would be exerted by a finger given the inaccessibility of the chip. However, this case may present a handicap in requiring a
précision de report élevée pouvant réduire la cadence de fabrication. high transfer precision which can reduce the production rate.
Un second cas également extrême de la figure 3, o les parois de la puce sont éloignés de celles de la cavité, présente l'avantage de permettre des cadences de report élevées. Néanmoins, il convient d'avoir une matière remplissant l'espace entre la puce et la cavité, pour assurer le maintien de A second case, also extreme in FIG. 3, where the walls of the chip are distant from those of the cavity, has the advantage of allowing high transfer rates. Nevertheless, it is advisable to have a material filling the space between the chip and the cavity, to ensure the maintenance of
la puce dans le support à l'encontre d'une éventuelle pression de doigt. the chip in the holder against possible finger pressure.
Un troisième cas préféré, illustré à la figure 1, correspondant à une configuration intermédiaire entre les variantes ci-dessus offre un bon compromis. Ces variantes de construction présentent également l'avantage de permettre l'utilisation de puces possédant les tranches légèrement conductrices dans la mesure o elles ne rentrent pas en court-circuit avec les éléments d'interconnexion, de la matière isolante (résine d'enrobage ou A third preferred case, illustrated in FIG. 1, corresponding to an intermediate configuration between the above variants offers a good compromise. These construction variants also have the advantage of allowing the use of chips having slightly conductive wafers insofar as they do not short-circuit with the interconnection elements, of the insulating material (coating resin or
adhésif)recouvrant la tranche de la puce. adhesive) covering the edge of the chip.
Le support peut être réalisé par lamination de feuilles, la feuille supérieure étant perforée. La cavité peut être également réalisée par embossage, usinage, découpage ou obtenue directement par injection du support si celui-ci est en matière polymère. X 5 Le procédé comporte une étape de réalisation d'interfaces de communication sur le plan du support. L'interface peut être obtenue de toute manière connue comme par exemple impression d'encre électriquement conductrice, par dépôt d'une substance électriquement conductrice, par lamination d'une grille prédécoupée et contre-collée sur le The support can be produced by laminating sheets, the upper sheet being perforated. The cavity can also be produced by embossing, machining, cutting or obtained directly by injection of the support if the latter is made of polymeric material. X 5 The method includes a step of producing communication interfaces on the support plane. The interface can be obtained in any known manner such as, for example, printing of electrically conductive ink, by depositing an electrically conductive substance, by lamination of a precut grid and laminated to the
support ou par gravure chimique si la nature du support le permet. support or by chemical etching if the nature of the support allows.
Dans l'exemple, I'interface est obtenue par impression en ayant ses In the example, the interface is obtained by printing by having its
extrémités ou point de connexion à proximité du bord de la cavité. ends or connection point near the edge of the cavity.
Ensuite, selon le procédé de l'invention, on dépose des cordons de matière conductrice entre la puce et le plan du support pour former un Then, according to the method of the invention, beads of conductive material are deposited between the chip and the plane of the support to form a
élément d'interconnexion avec l'interface. interconnection element with the interface.
Le procédé de dépôt utilisé consiste en une distribution de la matière ou résine conductrice conformément au procédé décrit dans la demande de brevet français n0 2 761 497 ou bien par jet de matière conductrice. Cette résine conductrice peut être par exemple une colle polymérisable chargée The deposition process used consists in distributing the conductive material or resin in accordance with the process described in French patent application No. 2 761 497 or else by jet of conductive material. This conductive resin may for example be a polymerizable adhesive charged
en particules conductrices telles que des particules d'argent. into conductive particles such as silver particles.
Ces techniques de connexion de puce par des polymères conducteurs sont très efficaces et performantes. Elles permettent de réduire le nombre d'opérations de fabrication et de diminuer nettement le These chip connection techniques using conductive polymers are very effective and efficient. They reduce the number of manufacturing operations and significantly reduce the
coût de fabrication des matériaux des circuits intégrés. cost of manufacturing materials for integrated circuits.
Ces procédés sont particulièrement intéressants pour des connexions de points situés à différents niveaux ou séparés d'une tranchée; d'autre part, ils permettent de s'affranchir d'une opération These methods are particularly advantageous for connecting points located at different levels or separated from a trench; on the other hand, they make it possible to get rid of an operation
d'enrobage si besoin.coating if necessary.
Il est également possible d'effectuer une impression sérigraphie o0 dans le cas o la face active de la puce est sensiblement au même niveau que le plan du support et o l'espace autour de la puce est rempli par de la It is also possible to carry out a screen printing o0 in the case where the active face of the chip is substantially at the same level as the plane of the support and o the space around the chip is filled with
matière isolante (enrobage ou adhésif de fixation). insulating material (coating or fixing adhesive).
Ensuite, on peut effectuer une protection de l'ensemble ainsi réalisé, Then, we can perform a protection of the assembly thus produced,
par dépôt d'une substance dans la cavité cette opération étant facultative. by depositing a substance in the cavity this operation being optional.
La réalisation de l'interface de communication et la connexion électrique peut être effectuée en une seule étape de dépôt de matière par The production of the communication interface and the electrical connection can be carried out in a single material deposition step by
les procédés mentionnés précédemment. the previously mentioned processes.
Le dispositif peut comporter le cas échéant une seconde puce supplémentaire. Elle pourrait être connectée en parallèle à la première par d'autres éléments d'interconnexion. Cette seconde puce pourrait porter par exemple une capacité d'accord d'un circuit résonnant du dispositif constitué The device can optionally include a second additional chip. It could be connected in parallel to the first by other interconnection elements. This second chip could for example carry a tuning capacity of a resonant circuit of the device constituted
de la première puce et de l'antenne. of the first chip and the antenna.
lh l 2802684lh l 2802684
Claims (12)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9916026A FR2802684B1 (en) | 1999-12-15 | 1999-12-15 | DISPOSABLE INTEGRATED CIRCUIT CHIP DEVICE AND METHOD FOR MANUFACTURING SUCH A METHOD |
PCT/FR2000/003513 WO2001045040A2 (en) | 1999-12-15 | 2000-12-13 | Disposable smart card |
AU21852/01A AU2185201A (en) | 1999-12-15 | 2000-12-13 | Disposable integrated circuit chip device and method for making same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9916026A FR2802684B1 (en) | 1999-12-15 | 1999-12-15 | DISPOSABLE INTEGRATED CIRCUIT CHIP DEVICE AND METHOD FOR MANUFACTURING SUCH A METHOD |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2802684A1 true FR2802684A1 (en) | 2001-06-22 |
FR2802684B1 FR2802684B1 (en) | 2003-11-28 |
Family
ID=9553449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9916026A Expired - Fee Related FR2802684B1 (en) | 1999-12-15 | 1999-12-15 | DISPOSABLE INTEGRATED CIRCUIT CHIP DEVICE AND METHOD FOR MANUFACTURING SUCH A METHOD |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU2185201A (en) |
FR (1) | FR2802684B1 (en) |
WO (1) | WO2001045040A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6777829B2 (en) * | 2002-03-13 | 2004-08-17 | Celis Semiconductor Corporation | Rectifier utilizing a grounded antenna |
FR2868987B1 (en) | 2004-04-14 | 2007-02-16 | Arjo Wiggins Secutity Sas Soc | STRUCTURE COMPRISING AN ELECTRONIC DEVICE, IN PARTICULAR FOR THE MANUFACTURE OF A SECURITY OR VALUE DOCUMENT |
FR2877462B1 (en) * | 2004-10-29 | 2007-01-26 | Arjowiggins Security Soc Par A | STRUCTURE COMPRISING AN ELECTRONIC DEVICE FOR THE MANUFACTURE OF A SAFETY DOCUMENT. |
FR2959581B1 (en) * | 2010-04-28 | 2012-08-17 | Arjowiggins Security | FIBROUS INSERT CONSISTS OF A SINGLE LAYER AND EQUIPPED WITH AN ELECTRONIC DEVICE WITH CONTACTLESS COMMUNICATION. |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19539181A1 (en) * | 1995-10-20 | 1997-04-24 | Ods Gmbh & Co Kg | Chip-card module with manufacturing method |
EP0810547A1 (en) * | 1996-05-24 | 1997-12-03 | Giesecke & Devrient GmbH | Method for manufacturing a datacarrier in cardform |
US5786626A (en) * | 1996-03-25 | 1998-07-28 | Ibm Corporation | Thin radio frequency transponder with leadframe antenna structure |
FR2761497A1 (en) * | 1997-03-27 | 1998-10-02 | Gemplus Card Int | METHOD FOR MANUFACTURING A CHIP CARD OR THE LIKE |
US5856662A (en) * | 1995-06-29 | 1999-01-05 | Hitachi Maxell, Ltd. | Information carrier and process for producing same |
-
1999
- 1999-12-15 FR FR9916026A patent/FR2802684B1/en not_active Expired - Fee Related
-
2000
- 2000-12-13 WO PCT/FR2000/003513 patent/WO2001045040A2/en active Application Filing
- 2000-12-13 AU AU21852/01A patent/AU2185201A/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5856662A (en) * | 1995-06-29 | 1999-01-05 | Hitachi Maxell, Ltd. | Information carrier and process for producing same |
DE19539181A1 (en) * | 1995-10-20 | 1997-04-24 | Ods Gmbh & Co Kg | Chip-card module with manufacturing method |
US5786626A (en) * | 1996-03-25 | 1998-07-28 | Ibm Corporation | Thin radio frequency transponder with leadframe antenna structure |
EP0810547A1 (en) * | 1996-05-24 | 1997-12-03 | Giesecke & Devrient GmbH | Method for manufacturing a datacarrier in cardform |
FR2761497A1 (en) * | 1997-03-27 | 1998-10-02 | Gemplus Card Int | METHOD FOR MANUFACTURING A CHIP CARD OR THE LIKE |
Also Published As
Publication number | Publication date |
---|---|
WO2001045040A3 (en) | 2001-11-08 |
WO2001045040B1 (en) | 2002-06-06 |
FR2802684B1 (en) | 2003-11-28 |
AU2185201A (en) | 2001-06-25 |
WO2001045040A2 (en) | 2001-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1060457B1 (en) | Electronic device with disposable chip and method for making same | |
FR2775533A1 (en) | ELECTRONIC DEVICE WITH CONTACTLESS ELECTRONIC MEMORY, AND METHOD FOR MANUFACTURING SUCH A DEVICE | |
WO2006120309A2 (en) | Silicon chips provided with inclined contact pads and an electronic module comprising said silicon chip | |
EP1946253A1 (en) | Smart card producing method and a smart card in particular provided with a magnetic antenna | |
FR2721733A1 (en) | Method for manufacturing a contactless card by overmolding and contactless card obtained by such a method. | |
FR2765010A1 (en) | ELECTRONIC MICROMODULE, ESPECIALLY FOR CHIP CARDS | |
FR2741191A1 (en) | PROCESS FOR MANUFACTURING A MICROMODULE, PARTICULARLY FOR CHIP CARDS | |
EP0954021B1 (en) | Method for making an electronic component | |
EP1724712A1 (en) | Micromodule, specifically for a smart card | |
FR2802684A1 (en) | DISPOSABLE INTEGRATED CIRCUIT CHIP DEVICE AND METHOD FOR MANUFACTURING SUCH A METHOD | |
WO2020126573A1 (en) | Method for producing a radiofrequency chip card insert comprising a metal plate | |
FR2779255A1 (en) | METHOD FOR MANUFACTURING A PORTABLE ELECTRONIC DEVICE COMPRISING AT LEAST ONE INTEGRATED CIRCUIT CHIP | |
WO2020126571A1 (en) | Method for producing a metal radio-frequency chip card with improved electromagnetic permittivity | |
WO2000030032A1 (en) | Method for making a hybrid smart card by double face printing | |
WO2020114753A1 (en) | Method for manufacturing a metal or non-metal chip card with relay antenna | |
WO2020114747A1 (en) | Method for manufacturing a chip card with interconnection of modules | |
EP2089836B1 (en) | Microcircuit board with offset antenna | |
WO2024149641A1 (en) | Reinforced chip-card module and process for manufacturing such a chip card | |
FR2769108A1 (en) | Flexible smart card for storage and transmission of data | |
WO2000011749A1 (en) | Method for making an antenna for a medium comprising an electronic circuit | |
EP3671562A1 (en) | Method for manufacturing a metal radiofrequency smart card with improved permittivity with extended perforations | |
EP4028945A1 (en) | Method for manufacturing a metal chip card with mini relay antenna | |
WO2001004988A1 (en) | Antenna for contactless cards, hybrid cards and electronic labels | |
WO2000048250A1 (en) | Method for the production of a chip-card type portable storage medium | |
EP2341472A1 (en) | Method for manufacturing by transfer of an electronic device comprising a communication interface |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20090831 |