FR2802659A1 - Method, for digital signal processing, of simultaneously carrying out several operations with a single operator, using separation bits chosen to ensure in all cases the integrity of the result - Google Patents

Abstract

The method has the following stages; (a) form similar partitions in each input register (31,32) to produce different zones (33,34), each zone in each register corresponds to a data input of with a single operation;insert between two consecutive zones a separator bit (35) which ensures the independence of the result (37,38) of each of the simultaneously effected operations. Method to carry out several operations with a single operator (30) admitting operands memorized in different input registers (31,32). A supplementary stage is added which partitions a results register (36) designed to receive results of the different operations. The partition is similar to the input register partitions. The different results are transferred to distinct output registers. The separation bits are specific for each operator. For a given operator, the different separation bits inserted between two consecutive zones are identical.

Description

A method for simultaneously performing multiple operations with a single operator The invention relates to a method for simultaneously performing several operations with a single operator. More particularly, the invention relates to a method that makes it possible to use an operator originally intended to perform an operation with numbers encoded on n bits to perform in parallel several operations with numbers encoded on a number of bits less than n.

The method according to the invention is particularly advantageous in the case where operators called variable arithmetic are implemented. Such operators can perform operations from operands whose number of bits can vary. For example, an adder that can perform additions between 16-bit coded operands or between 24-bit coded operands is called double arithmetic: it is both compatible with 16-bit arithmetic and with 24-bit arithmetic.

The field of application of the invention is that of digital signal processing. Specific processors called DSP (for Digital Signal Processing in the English literature) are specifically designed for digital signal processing. The are more particularly used for particular functions specific to the processing of digital signals, such as filtering or comparing signals. In some data processing systems, a DSP may be associated with a more powerful host processor to perform complex signal processing operations. Some applications of DSP require attention, a particular precision especially for performing arithmetic operations. For example, the rendering of a so-called high fidelity sound may require calculations involving numbers coded on a larger number of bits for the calculations necessary for simple voice transmissions. Increasing the number of bits to code the numbers involved in the calculations provides a higher degree of accuracy.

Conversely, there are other applications involving operations that require calculations involving numbers encoded on a specific number of bits; for this type of operation, the possibility of working with numbers ensuring a better accuracy thanks to a larger number of bits is not retained. Sometimes this possibility is even excluded for these operations. For example, there are communication standards in cellular telecommunication systems, such as the GSM standard in Europe, which impose numbers coded only on 16 bits and which do not admit numbers coded on more than 16 bits even if this allows to achieve a higher degree of accuracy. against many recent multimedia applications dedicated to digital signal processing now require a high degree of accuracy, including the return of audio signals, while having the ability to comply with the GSM standard to receive telecommunications that obey this standard .

problem therefore arises: powerful operators, that is to say working with numbers encoded a large number of bits, and less powerful operators, which must work with code numbers on a number of bits imposed by certain standards, must coexist. To make a choice between these two types of operators, and therefore between two different arithmetic, is no longer conceivable. The solution would be to make two groups of distinct operators coexist within the DSPs, each of the two groups operating with a different arithmetic. But this solution is penalizing in terms of cost and space required.

There are now operators capable of performing operations according to different arithmetic, the arithmetic in question can range from 1 bit to n bits, where n is the maximum number of bits of an operand. In most of these situations, n is the size of the input registers of the operator. As a result, operators that can perform operations on both a large number of bits and a smaller number of bits do not operate permanently at their maximum capacity. Thus, for example, a 48-bit adder performing an addition between two 24-bit numbers is not used optimally.

Furthermore, to perform operations within the same system, for example on 48 bits or on 24 bits, it is possible to use two distinct 24-bit operators which can then either each carry out a 24-bit operation, the two operations on 24 bits can then be simultaneously executed, or perform a 48-bit operation by chaining the two 24-bit operators, the chaining of the two operators to allow to recover a possible outgoing retention.

Figures la and lb give an example of these possibilities. In FIG. 1a, a first 24-bit adder 1 and a second 24-bit adder 2 are used to respectively add a first 24-bit number A with a second 24-bit number and a third 24-bit number C with a fourth number of 24 bits D. The result of the first addition, respectively the second addition, is decomposed into a number of 24 bits (A + B), respectively (C + D), and a possible outgoing restraint rs (A + B) respectively rs (C + D). Two 24-bit operations were thus carried out in parallel.

In Fig. 1b, the first 24-bit adder 1 and the second 24-bit adder 2 are chained together to perform a 48-bit addition. The 24 most significant bits of a first 48-bit number X and a second 48-bit number Y are added using the first 24-bit adder 1. The 24 least significant bits of the first number X and the second number Y are added by means of the second adder 2. The notation X (k: 1) means that we consider only the bits k to 1 of the binary number X (k is in this case the most significant bit and 1 is the least significant bit). A connection 3 between the two 24-bit adders 1 and 2 ensures the propagation of a possible outgoing carry coming from the addition of the least significant bits of the two numbers X and Y. A first intermediate result 4 on 24 bits is obtained as output of the first adder 1. A second intermediate result of 24 bits is obtained at the output of the second adder 2. The intermediate results 4 and 5 are concatenated to obtain a final result of 48 bits. A possible outgoing restraint rs (X + Y) can be obtained at the output of the first 24-bit adder 1.

If the methods which have just been described are capable of being implemented to carry out 24-bit or 48-bit operations, they nevertheless pose a problem in terms of the execution time of the operation. Indeed, the average time that an operator now takes to execute an operation is approximately proportional to the base 2 logarithm of n, denoted 1092 (n), where n is the number of bits of the operands. Thus, in the example which has just been presented, the propagation time necessary to carry out the operation of FIG. 1b is a proportionality coefficient k equal to 2 1092 (24), ie logz (242). This execution time is much more important than the execution time of a 48-bit adder which would have been equal to logz (48), with a k-value close to it.

The method according to the invention makes it possible to overcome the various defects and disadvantages which have just been described. The method according to the invention implements means for simultaneously performing several operations with a single operator without being confronted with execution time problems of the type encountered during the chaining of two operators, and with optimal use of the capacities. the only operator.

In addition, in the method according to the invention, the different input registers of the single operator undergo a partition in a number of zones equal to the number of operations to be performed simultaneously. All input registers undergo similar partitions. Two consecutive zones of the same register are separated by a separation bit whose function is to avoid a possible propagation of restraint between different zones of a result register. The result register also undergoes a partition which is similar to that of the input registers containing the different operands. Each number contained in the different areas of the result register corresponds to a result of one of the operations performed simultaneously. The separation bits thus ensure the independence of data between the different operands.

The invention therefore relates to a method for performing simultaneously several operations with a single operator admitting operands stored in different input registers, characterized in that it comprises the steps of: performing similar partitions of each input register to obtain different zones each of the areas of each input register corresponding to an input data of a single operation; - Insert between two consecutive zones a separator bit to ensure the independence of the result of each of the operations performed simultaneously.

Preferably, a partition similar to the partitions of the input registers is performed in a result register intended to receive the results of the various operations. Moreover, the different results of the different operations can be extracted from the result register to be stored in separate output registers. The separation bits that are chosen to ensure the independence of the results of each of the operations performed simultaneously by preventing the propagation of a possible hold between the different areas of the register result 7 specific to each operator. However, for a given operator, and in order to avoid carry propagation, all the separation bits adopt the same value.

The various aspects and advantages of the present invention will be better understood on reading the following description with reference to the figures which are given only as an indication and in no way limitative and which are now introduced - FIGS. 1a and 1b, already described. , illustrate the use of several operators to perform operations on a variable bit number - figure 2 shows a possible structure of a partition of an input register containing an operand for use by an operator according to the method of invention; and FIGS. 3a and 3b illustrate an example of implementation of the method according to the invention with the aid of an adder.

In Figure 2, an input register 0 of any operator is shown. By way of example, the register 20 has a size of 49 bits numbered 0 to 48. However, it is obvious that registers of all sizes can be considered for the implementation of the method according to the invention. A partition of the register 20 into three distinct areas is shown. A first zone 21, which corresponds for example to the first 24 bits of the input register 20, is separated from a second zone 22, which corresponds to the 24 most significant bits of the input register 20, by a third zone 23, said separation zone, whose size is 1 bit. Such a partition of an input register may allow an operator to perform two operations a first operation between an operand contained in the first zone 21 and other operands of the same size contained in similar zones of other registers. not shown, and simultaneously a second operation between an operand contained in the third zone 22 of the input register 20 and other operands of the same size contained in similar areas of other input registers. The separation zone 23 is intended to contain a single separation bit between the two operands of the zones 21 and 22. It is obvious that the method according to the invention can be implemented with registers of different size from the size of the register. 20 and with different partitions, or with registers of the same size as the register 20 but with different partitions.

Moreover, the different zones containing the different operands are not necessarily of the same size for the same input register. in addition, a partition of an input register does not limit the latter necessarily to three zones. More two operands can be contained in the same input register for the implementation of the method according to the invention. Whenever an operand is added, a separator bit must also be added. This implies that the operator performing operations using the data contained in these input registers must be of the correct size. Thus, to perform simultaneously two operations on 24 bits according to the method of the invention, it is a 49-bit and not 48-bit operator that must be used. In a more general way, to perform x simultaneous operations with the method according to the invention, it is an operator size (n + x-1) bits to be used, n being the total number of bits operands intervening in operations.

As previously mentioned, the computation time is proportional to the logarithm in base 2 of the number of input bits of the operator. The difference in execution time between an operation on (n + x-1) bits and an operation on n bits is therefore negligible, x being most often a value much smaller than n. FIG. 3a represents an implementation of the method according to the invention in the case of two additions in parallel between numbers of size n / 2 bits. An adder n + 1 bit 30 operates from data contained in a first input register 31 and a second input register 32 which contain the different operands to be added. The notations defined in the description of FIG. 1b are used again here. Thus, to simultaneously realize two additions between firstly a first number A and a second number B of n / 2 bits, and secondly a third number C and a fourth number D of n / 2 bits, the distribution of different operands in the different input registers is as follows: in the first register 31, there is in a first zone 33 the first number A, in a second zone 34, the third number C and in a third zone 35 of size 1 bit, there is a separation bit of value 0.

In general, the separation bits involved in the addition, addition with saturation ... operations have the value 0. The separation bits involved in the subtraction, subtraction with saturation type operations are of value. 1. In the case of the simultaneous execution of several operations, the value of the separation bits is chosen to avoid a possible propagation of restraint between zones E <B> 10 </ B> tincts of the result register, these zones di.- _____- corresponding to results independent of different operations. For a given operator, the different separation bits inserted between two consecutive zones defined by the partition of the input registers are identical.

The structure of the register 32 is similar to that of the register 31, the numbers A and C being respectively replaced by the numbers B and D. The result is obtained in a result register 36 of size n + 1 bit and whose partition is the next: a first zone 37 of size n / 2 bits contains the result of the addition A + B; a second zone 38 of size n / 2 bits contains the result of the addition C + D; a third zone 39 of size 1 bit has a significant value of the presence of an outgoing restraint in the addition between C and D. An unrepresented microcontroller which manages all the operations performed can then transfer the results of the two separate operations in two separate registers. The outgoing restraint rs (A + B) of the addition A + B can be taken into account in a specific register such as a saturation unit 40.

FIG. 3b represents the case where the n + 1 bit adder 30 of FIG. 3a must be used to make a single addition between two numbers X and Y of size n bits, while keeping the same partition as in FIG. 3a of the first input register 31 and the second input register 32. This example shows that the means implemented by the method according to the invention, namely a partition of the input registers with addition of separation zones, do not are not an obstacle to continue performing a single operation using the relevant operator. Each of the two input registers is divided into two zones of size n / 2 bits separated by a separation zone of size 1 bit whose references are the same as in FIG. 3a. Using the notations defined in FIG. 1b, the distribution of the different operands in the different input registers is as follows: Y (n1: n / 2) in the zone 33 of the first input register 31, Y ( n / 2-1: 0) in the zone 34 of the first register 31, X (n1: n / 2) in the zone 33 of the second input register 32 and X (n / 2-1: 0) in the zone of the second input register 32 - the separation bits are 0 for the first input register 31 and 1 for the second input register 32.

It should be noted that the separation bit of the second input register is 1 because, in this case, it is desired that any retaining resulting from the addition of the operands contained in the different zones 34 be propagated. In the case of a subtraction, the value of the separation bit which would have ensured the propagation of a possible outgoing retention would have been 0. Indeed, since a single operation is carried out here, the data of the different operands are no longer independent of each other. others.

The result is obtained in the result register 36. The separation zone 39 contains a bit whose value depends on the presence of an outgoing carry when adding the least significant bits of the numbers X and Y. This separation bit does not however not part of the definiti result. The latter is stored in a definitive result register 41 which contains, coded on n bits, the result of the concatenation of the zones 37 and 38. Moreover, as in FIG. 3a, a saturation unit 40 may contain an outgoing restraint rs (X + Y) of the addition X + Y.

Claims (2)

1. A method for simultaneously performing several operations with a single operator (30) admitting operands stored in different input registers (31; 32) characterized in that it comprises the steps of: performing similar partitions of each register; input (31; 32) to obtain different areas (33; 34), each of the areas of each input register corresponding to an input data of a single operation; inserting between two consecutive zones a separator bit (35) to ensure the independence of the result (37; 38 of each of the operations performed simultaneously. 2. A method for simultaneously performing several operations with a single operator (30) according to claim 1 characterized in that it comprises the additional step of partitioning a result register (36) for receiving results from different operations, said partition being similar to the partitions of the input registers (31; 32). A method for simultaneously performing multiple operations with a single operator (30) according to claim 2 characterized in that it comprises the further step of transferring the different results contained in the result register (36) to separate output registers. .Procédé to simultaneously perform several operations with a single operator (30) according to one of the preceding claims characterized in that the separation bits are specific to each operator. 5. A method for simultaneously executing several operations with a single operator (30) according to one of the preceding claims, characterized by the fact that for a given operator, the different separation bits inserted between two consecutive zones defined by the partition of the input registers are identical. .