FR2800877A1 - Device for emulation of faults in digital logic circuits, such as programmable logic devices, has an image register and fault register associated with each working register to allow simultaneous copying of faults and debugging - Google Patents

Abstract

Circuit has a number of working registers (R1) associated with internal circuit nodes. These registers contain switching states of communication nodes dependent on input signals. Each working register has an associated image register (R2) enabling extraction of the switching state of the working register and a fault register (R3) connected so that the working register output is set to a fault value. The working register output is set to a fault value dependent on the fault register independent of an input signal applied to the working register.

Description

The present invention relates to a device for emulating faults in digital logic circuits and in particular a device for emulating faults in digital logic circuits comprising a debug circuit in which, at each internal useful register of the digital logic circuit, is associated an image register for extracting the contents of the associated useful register or registering a predetermined value in the associated useful register.

A PLD component (Programmable Logic Device), which allows the internal nodes to be observed by image elements associated with the internal nodes, is described in US-A. A-0799. This circuit makes it possible to transfer the states of the internal nodes inscribed in the useful registers internal nodes to the image elements which make it possible to make them available to the inputs / outputs by means of shift registers.

US-A-5,870,410 discloses an interface system comprising for example PLD components such as those described in US-A-5,764,079. The interface elements serve not only to observe the states of the internal nodes. , but also to apply test vectors for the observation of defects. If, however, the internal nodes suffer from faults, it is no longer possible to observe them at the same time by a normal circuit fault search operation (debugging).

The object of the present invention is to develop a device for emulating faults in digital logic circuits, making it possible to copy the faults of the logic circuit while at the same time making it possible to search for a fault (debugging) in such a faulty logic circuit. .

To this end, the invention relates to a device for emulating faults in digital logic circuits comprising a plurality of useful registers associated with nodes internal to the circuit in which the switching states of the internal switching nodes that are dependent on the input signals, characterized in that to each useful register is associated an image register for extracting the switching state of the useful register, by associating in one or more useful registers, a fault activation register connected to the useful register so that the output of the useful register is set to a fault value independently of the application of an input signal therefrom.

Such a fault activation register associated with the different registers used in a digital logic circuit allows statistical manipulation of a circuit manufactured to copy the defects originating from the manufacturing process and make it possible to judge the quality of the tests in the manufacture. such integrated circuits.

In preferred exemplary embodiments of the present invention, a dynamic fault activation register is further associated with the useful register as well as a dynamic fault level register; these registers are connected to the wanted register and to the fault activation register so that the output of the useful register is set for a predetermined duration during the operation of the digital logic circuit to a fault value, independently of the input signal applied. to the useful register. These additional registers allow dynamic manipulation of a circuit manufactured to copy and analyze the influence of the various faults on the operation.

The present invention creates a fault emulation device in digital logic circuits in which internal nodes are associated with circuits with useful registers, each time an image register. This image register makes it possible to observe and to grasp the internal behavior of a circuit, for example of an FPGA circuit (Programmable Field Gate Network) or of a PLD component, for example during a test of prototype or during a test in the system, in order to use the data entered during a subsequent analysis of the operation of the circuit.

The fault activation registers, the very dynamic fault activation registers and the fault level registers, in addition to the image registers, make it possible to intentionally copy both of these defects generated in the process of the invention. manufacturing of integrated circuits and modeling a fault behavior in the circuit, which corresponds precisely to disturbances under normal environmental conditions, such as circuits used in space, and subjected to cosmic radiation. The device according to the invention, for the emulation of faults, thus offers the possibility of jointly analyzing development defects, manufacturing defects and disturbances related to normal operation. The need for the combined analysis therefore has the consequence of developing the operation of a circuit, so that the circuit performs its function in normal mode while being tainted with a certain number of manufacturing defects or undergoing a defined number of disruptions. Such disturbances can be emulated by the device according to the invention Thus, it is possible according to the invention, in addition to freely predetermined definition of the internal states of the circuit and the reading of the internal states by one or more image registers, To position the faults in the digital logic circuit at the same time to have a fault positioning and a debug of the circuit. Thus, the momentary momentary switching state will be governed internally by the real-time operation of the circuit while the The states of the fault positioning registers result from specific faults that have been introduced into the circuit during configuration operation. The positioning of the faults in the circuit is ensured by a command which can activate the faults positioned with determined elements.

The device according to the invention is advantageous in that it allows the detection of the internal states of a digital logic circuit in real time, and at the same time posit the faults statistically or dynamically in the circuit. The process is independent of the applied technique and is not related to any particular property; the image registers integrated in the digital logic circuit, the fault activation registers and the dynamic fault activation registers as well as the dynamic fault level registers do not influence the speed and operation of the integrated circuit.

Fault activation registers, very dynamic fault activation registers and / or dynamic fault level registers can be combined in the image registers according to a detection chain, so that during a configuration mode some data is introduced while they are removed from the detection chain when outside the configuration mode.

According to other advantageous features of the invention, the image register and the fault activation register are mounted in a detection chain so that in a configuration mode, predefined values can be pushed into the image register and the register. of fault activation, the fault activation registers being cut off from the detection chain outside the configuration mode, # to one or more useful registers with which a fault activation register is associated, a dynamic register is also associated. a fault activation and a dynamic fault level register connected to the wanted register and the fault enable register so that the output of the useful register is set for a predetermined time, preferably during the operation of the digital logic circuit, on a fault value independently of the input signal applied to the useful register, # the dynamic register of fault activation defines whether the output of the useful register must be maintained at a fault value defined by the dynamic fault level register, # the dynamic fault activation register and the dynamic fault level register are provided in a detection chain so that in a dynamic fault configuration mode, predefined values can be entered therein, the dynamic fault activation register and the dynamic fault level register being cut off from the detection chain outside the dynamic fault configuration mode, an image register and / or the dynamic fault activation register and / or the dynamic fault level register are in the form of FIFO memories.

The present invention will be described hereinafter in more detail with the aid of embodiment examples presented in the accompanying drawings, in which FIG. 1 is a diagram of the set of a com cell carrying the useful register of FIG. a node of a digital logic circuit and a preferred embodiment of the device of the invention, FIG. 2 is a diagram showing how a useful register of a digital logic circuit is replaced by a global cell, FIGS. 3b are diagrams explaining how the device according to the invention is involved in the emulation of faults of a debug circuit, FIG. 4 is a diagram showing a useful circuit carrying a debug circuit / emulation of faults, FIGS. 5a-5c are diagrams describing the recording of predetermined switching states of a useful register of a digital logic circuit according to an image register, FIGS. 6a-6c are diagrams describing the reading of the states of the circuit of a useful register in a digital logic circuit according to an image register, FIGS. 7a-7c are diagrams describing a statistical emulation of faults, FIGS. 8 and 9 are schemas that, combined with Figure 1, are used to describe dynamic emulation of defects.

FIG. 1 shows an exemplary embodiment of a global cell replacing, in a digital logic circuit, a register that is useful for implementing a device according to the invention for fault simulation. According to FIG. 1, the global cell comprises a useful register R1, an image register R2, a fault activation register R3, a dynamic error activation register R4 and a dynamic register of fault levels R5. These registers have an identical structure according to a preferred example of the invention and may consist of flip-flop flip-flops D. The registers R1-R5 are connected by demultiplexers MUX1-MUX6 an input signal d, to a signal output signal q, at a scan detection channel input i, at a scan detection string output o and at a number of control signals Fsim e, Cpt e, DFS upd, DFS e, Set e, Scan e, so that the global cell can perform the functions of the fault emulator according to the invention.

In other words, FIG. 1 shows a cell of the fault emulator according to the invention, each time replacing a memory element of the useful circuit. All new registers, introduced, are accessible for a control of the defect emulator, for example by means of one or more shift channels, separated; in Figure 1, the segment (scan i ... scan-o) associated with a cell is only a shift chain. The useful register R1 performs the function of the original useful register in the useful circuit and is controlled by the clock. In order not to hinder the operation of the circuit, this register is not integrated in a control interface for controlling the emulator-debugger, in the example above in the detection chain. The image register R2 serves to emulate continuously for the analysis of defects as will be described hereinafter with reference to FIGS. 3a and 3b. The control of the debug circuit ensures the transfer of the contents of the useful register R1 into the image register R2 by the control signal Cpt e so that the state of the useful register circuit RI is read and stored by the image register R2 and the control interface, by the detection chain scan i ... scan o in the exemplary embodiment shown. Moreover, by the image register R2, the useful register RI can be initialized by the command signal Set -e with a value defined by the user.

The fault activation register R3 is then used to position a fault in the useful register RI. For this, by the control interface, the control can extract in the fault activation register R3 a value which controls whether the <U> Ri </ U> register is operating normally or if a fault has been activated. This recording of the fault positioning thus occurs in a configuration mode prior to the actual emulation of faults, it being noted that the useful circuit can not operate without interference during the positioning of faults in the circuit.

The activation of a fault means that the useful register R1 retains its contents, for example according to FIG. 1 by the reaction coupling 2 and by the upstream element MUX2, and that it is isolated by the data input (d ) proper. The R3 fault activation register is used to emulate statistical faults, while for the emulation of dynamic faults, that is to say during the normal systematic operation of the circuit, to position and activate or deactivate new ones. faults at any time at any position, in addition to both the dynamic fault activation register R4 and the dynamic fault level register R5 are required. It should be noted here that in exemplary embodiments of the invention, which must provide only a statistical emulation of faults, the fault activation register R3 is sufficient whereas in the variant embodiments which must furthermore ensure an emulation In the case of fault dynamics, the two registers R4 and R5 must also be provided.

Before describing in more detail the precise construction of the overall cell and its operation by referring to FIGS. 1 and 5 to 9, the mounting of the defect emulation device according to the invention in a debugging circuit system will be described.

According to FIG. 2, and as already mentioned above with reference to FIG. 1, to realize the defect emulation device according to the invention, the useful register R1 is replaced with a signal input ( d), a signal output (q) and a clock input C, by a global cell Z, having a signal input (d), a signal output (q), a clock input C1, a clock input C2 and receiving the control signals mentioned above of Figure 1. The clock input C2 is used to control the registers R2-R5 by the formed detector string. If for different registers R2, there are different detection strings, the registers can also be controlled with different clocks.

According to Figures 3a and 3b will be described below the relationship and the situation of the defect emulator according to the invention in the overall system of a debugger circuit.

FIG. 3a shows the environment 10 of the system concerned by the DUT 12 to be tested. The DUT 12 is connected to the environment 10 of the system through an interface 14 transmits both the input and output signals exchanged between DUT and the system environment. The DUT is further connected by a debugger / emulator circuit interface 16 to a control 18 for the debugger / emulator circuit; the control 18 is itself connected to a memory 20. FIG. 3a shows schematically a part 22 of the DUT which contains the components of the debugger / fault emulator circuit of the DUT. These components correspond, for example, to the registers R2-R5 of FIG. 1. The control 18 supplies the necessary control signals such as those shown for example in FIG. 1, allowing continuous operation of the debugger circuit, as well as the necessary control signals. to the emulation of defects.

For the continuously executed fault finding mode, the control 18 preferably cyclically extracts all the internal switching states of the DUT 12 by the image register and stores these states in the memory 20. The control 18 is also connected by a host interface 24 to a computer 26 which, from the switching state diagrams of the DUT 12 as inputted by the command 18 and stored in the memory 20 as well as vectors of the entered input signals, is able to to execute a programmed simulation of the behavior of the DUT 12. The switching model for the program simulation in the computer 26 preferably exists as a list of gate networks, so that the switching state diagrams, recorded in FIG. the memory 20 and read by the command 18, can be used without transformation for the simulation by the host computer 26.

According to FIG. 3b, an example of a debugging circuit process will be described, working continuously with the following program wording. The axis of the upper part of Figure 3b corresponds to the real time axis while the lower axis corresponds to a virtual simulation time. The DUT 12 operates in real time by applying input signals through the interface 14 which may represent the environment of the system on the DUT 12 during operation. During operation of the DUT 12, which may be for example an FPGA or a PLD, the switching states of all the internal switching nodes of the DUT 12 are extracted cyclically by the circuit 30; this is indicated by the arrow 31 in Figure 3b. The circuit 30 is connected by an interface 32 to the DUT 12. Although the circuit 30 and the DUT 12 are shown in FIG. 3b as separated by an interface 32, a part of the circuit 30, namely at least the image register of FIG. it is formed on the integrated circuit corresponding to the DUT 12. The operation of the logic circuit, for example by the execution of a prototype test or a test in the system, continues during the operation of the circuit debugger, until time t1 when a fault state 33 occurs in the DUT 12. This fault state 33 represents an interrupt condition.

When such an interrupt condition 33 occurs, depending on the cyclically extracted circuit states from the debug circuit 30 and the input signals provided to the DUT 12, a program simulation is performed to search for the causes of the circuit. Fault status 33. The transfer of data mentioned above is shown schematically in Figure 3b by an arrow 34. It is noted here that the operations shown above the arrow 34 correspond to a real-time environment, while the operations represented on the time axis, below the arrow 34, represent a virtual simulation time. As shown in FIG. 3b, for simu lation, to find the cause of the fault, we return back to the instant t1 to the instant t2 to start simulation at this instant t2. The return interval is preferably chosen so that the switching state diagram stored at time t2 indicates a correct operation DUT. Thus, there is a program simulation interval 35 for analyzing the cause of the fault. This interval begins at time t2. The interval consumption for the fault cause analysis method which starts after the entry of the fault state 33 is thus shortened considerably. As schematically indicated by the arrow 34, cyclically read data is used for a subsequent analysis of the switching behavior; the internal states of the circuit describe the internal behavior of the 12, while the input signals represent the environment leading to the observed behavior.

The search for faults, which continues in cyclical reading of the image register in the memory 20, offers the possibility of analyzing the causes of errors in a very rapid manner because, starting from defects produced, it is possible to return a predetermined time to then perform the program simulation from the switch state diagram stored at that time and the corresponding input signal vectors.

The fault emulation device according to the invention is then realized by the fault activation register R3, the dynamic fault activation register R4 and the dynamic fault level register R5 in the debugger / emulator circuit segment. The control signals necessary for the emulation of faults, which will be detailed later, are preferably provided by a common control 18 of the emulator / debugger circuit. Alternatively, to the embodiment described with the aid of FIG. 3a, other components of the defect search and emulation device, for example RAM 20, the basic elements of FIG. control 18 or the entire control 18 according to the space requirements of the circuit board of the DUT 12. It is noted that other components equipping the circuit board of the DUT 12 can offer advantages to 1 reading the register of the circuit thanks to shorter transit times of the signals; however, the limited space available on the platen can lead to limited memory capacity.

FIG. 4 schematically shows the wiring of several global cells Z according to the invention in a detection chain 40. According to FIG. 4, the control 18 provides the set of input signals described, for example, with reference to FIG. The control lines 42 are intermediated to the corresponding branches of the global cells Z which may also be called debug / emulation cells. It should be noted that the Z global cells are shown on an enlarged scale to be clearer in FIG. 4; the respective enlargement is dried matisé by a magnifying glass. As shown in FIG. 4, the global cells Z are combined in a detection chain and the respective detection inputs of the global cells of FIG. 4 bear the reference 44; the detection outputs of the global cells in FIG. 4 carry the reference 46. Each global cell receives a useful signal (d) and outputs a useful signal (q) towards a useful circuit as indicated schematically by the double arrow 48 to FIG. 4. According to FIG. 4, the input and the output of the detection chain are connected to the control 18. The control 18 is itself interfaced to a memory and / or a host computer as is indicated diagrammatically by the arrow 50 in FIG. 4. The frame 52 of FIG. 4 shows the useful circuit formed by the various useful registers belonging to the global cell Z.

The useful cells Z described above thus also provide the possibility of a continuous search for circuit faults by the cyclic reading of the internal switching states of the DUT, and a simultaneous emulation of the faults by a corresponding command of the control registers. Fault activation, dynamic fault activation registers and dynamic level registers of defects according to the invention. After describing the situation of the defect emulator according to the invention in the debug circuit, the following will be described with reference to FIGS. 1, 5, 6, 7, 8, both the structure and the operation of FIG. the preferred embodiment of a global cell representing a device according to the invention emulation of defects. It should be noted that the following description refers only to an exemplary embodiment envisaged here preferably of a device for emulation of defects; It is clear to those skilled in the art that circuit variants can be provided to provide the function of the fault emulation device according to the invention.

According to FIG. 1, the global cell of the preferred exemplary embodiment comprises the useful register R1, the image register R2, the fault activation register R3, the dynamic fault activation register R4 and the dynamic level register of defects R5. Either there are six demultiplexers MUX1-MUX6 connecting the registers R1-R5 to the control signals of a detection chain and to the input and output signals, to ensure the functionality according to the invention. In detail, the data input 100 of the useful register R1 is connected to the data output of the multiplexer MUX2. The data output 104 of the useful register R1 is connected by the feedback path 2 to a data input of MUX2, by a line <B> 106 </ B> to a data input of the demultiplexer MUX1, and further to the data output (q) of the global cell. The data input 108 of the image register R2 is connected to the data output of the demultiplexer MUX1. The data output 112 of the image register R2 is linked each time to a data input of the demultiplexers MUX1, MUX2, MUX3, MUX4. The data input 114 of the fault activation register R3 is connected to the data output of the demultiplexer MUX3. The data output 116 of the fault activation register R3 is connected in each case to a data input of the demultiplexer MUX3 and MUX4 as well as to a control input of the demultiplexer MUX2. It should be noted here that the terminals called each time data inputs of the demultiplexers are in the drawings, terminals provided on the large left side of the demultiplexers. On the contrary, the control inputs of the demultiplexers are provided every time on the small side of the demultiplexer.

The data input 118 of the dynamic activation register R4 is connected to the data output of the demultiplexer MUX5. The data output 120 of the dynamic fault activation register R4 is connected to the data inputs of the demultiplexers MUX3, MUX4, MUX5 as well as a control input of the demultiplexer MUX2. The data input 122 of the fault level register R5 is connected to the data output of the demultiplexer MUX6. The data output 124 of the register R5 is connected to a respective data input of the demultiplexers MUX2, MUX5, MUX6.

The data input (d) of the global cell is connected to a data input of the demultiplexer MUX2. The input of the scanning chain i of the global cell is connected to a data input of MUX1 and a data input of MUX6. The output of the detection chain scan o is connected to the data output of the demultiplexer MUX4.

The control signal Fsim e is connected to the respective control tracts of the demultiplexers MUX1, MUX2, MUX4. The control signal Cpt e is connected to a control input of MUX1. The control signal DFS upd is connected to a control input of MUX3 and to a control input of MUX4. The control signal DFS e is connected to the respective control inputs of the demultiplexers MUX1, MUX3, MUX4, MUX5, MUX6. The control signal Set e is connected to a control gateway of the demultiplexer MUX2. The scan command signal is connected to the respective control inputs of the demultiplexers MUX1, MUX2, MUX3, MUX5, MUX6.

To describe the operation of the circuit shown in FIG. 1, reference will be made to the different modes of operation of the circuit which will be described below according to the operating states. FIGS. 5b, 6b and 7b show only the elements and the lines necessary for the description of the respective operating mode, the other elements being eliminated in order to simplify the drawing. Figures 5a, 6a, 7a and 8 show state diagrams indicating the transition to the different states for different occupations of the control signals. FIGS. 5c, 6c, 7c and 9 describe the states in which the circuit is located as well as the output signals of the respective demultiplexers corresponding to the different states. Insofar as the following description will not evoke certain states or certain occupations of signals, which are not necessary for the understanding of the operation of the circuit, reference will be made to the state diagrams and the tables mentioned in the figures. -above.

According to FIGS. 5a-5c there will be described a state of operation mode for putting the useful circuit in a predetermined state. This means that all the useful registers R1 can be put into a predefined state. For this, the control signal Scan e is first set to state 1 so that the demultiplexer MUX1 switches the input of the detection chain scan i to its output in order to shift the predefined value in the image register R2; this is done at the clock frequency C2. This state 200 is represented in FIG. 5a by the designation Scan in. The occupation of the register R2 can be done by a serial detection chain, as shown in FIG. 4, which contains all or some of the emulator cells. It is also possible to envisage bus structures or other mechanisms for occupying the image registers R2 with the corresponding values.

If the image registers R2 are occupied by the corresponding values, the operation changes to a state 200 called the set status and for this the control signal Scan e is set to 0 while the Control Set e is set to state 1 as it appears in the state diagram of FIG. 5a. In this situation, as shown in FIG. 5c, the demultiplexer MUX2 switches the data input connected to the data output of the image register R2 to its input so that the value stored in the image register R2 can be read in the useful register Rl. The useful register R1 is thus loaded with a predefined value; then the operation proceeds to state 204 called state sim, in which the command signal Set -e is set to state 0. The state sim 204 thus represents the normal operation of the useful circuit of a fault emulation or a debugger circuit.

All the other control signals of the global cell shown in FIG. 1 remain inactive in this mode of operation, that is to say that these signals retain the selected polarity for which the state 1 indicates an active signal while the state 0 indicates a deactivated signal.

According to FIGS. 6a-6c, a debug mode of operation will be described hereinafter while the useful register operates undisturbed under normal conditions. In the debug mode of operation, the respective switch states of the useful register are read in the image register.

According to FIG. 6a, reference 206 shows that the debug mode is usually preceded by a mode of conditioning as described above. For the debug mode an additional control signal Ctp e is required which is set to active level from normal operation (state sim 204); then the state 208. By the activation of the control signal Cpt e, the demultiplexer MUX1 switches its data input connected to the data output of the useful register R1 on its output, so that the recorded information in the useful register R1 is loaded by the next edge of the clock signal C2 in the image register R2. Then the control signal Cpt e is deactivated and the signal Scan e activated, so that one goes into a detection state 210 designated by Scan-out. In this operating state 210, the content of the image register R2 is detected by the detection chain and is recorded for example in the RAM memory 20, as described above in relation to FIG. 3a. These operations take place without influencing the useful circuit. All control signals which do not participate in the debug mode are assumed to be in state 0. The debug mode thus represents the cyclic readout of the switching states of the internal nodes of a digital logic circuit. As will become clear below, this debug mode of operation can be executed without being disturbed by the emulation of defects according to the invention.

According to FIGS. 7a-7c, a first exemplary embodiment of a defect emulation according to the invention which relates to an emulation of a statistical fault will be described below. For the emulation of a statistical fault (as shown in FIG. 7b), the fault activation register R3 and two other demultiplexers MUX3, MUX4 are also needed. The statistical defects are located by the fault activation register R3 with the emulation itself said in the circuit; this is done by a set operating mode as indicated by the states 212, 214 of FIG. 7a. FIG. 7b shows a circuit in which the registers R2, R3 are combined according to a detection chain to have a simultaneous configuration of the very registers R1, R3 with a value defined by the user during the operating mode set to the state (Set ) because the Scan e control signal is activated during the state 212 (Scan in) in the control inputs of the three MUX1-MUX3 demultiplexers. In the next set state 214, the value stored in the image register R2 is stored in the useful register R1 to activate the control signal Set e. Thus, the fault activation register R3 contains a value indicating whether, during a subsequent emulation, it is necessary to emulate a fault in the useful register R1, which, in the exemplary embodiment represented, is the case if the fault activation register R3 contains a state 1 in the memory, because in this case the demultiplexer MUX2 is controlled by the output of the fault activation register R3 to put its data input connected to the output of the useful register R1 , on its output of data. Thus, the useful register R1 is blocked on a fixed fault value by its reaction line 2 and the demultiplexer MUX2. From the operating mode Set, which contains the states 212, 214, operation is switched to the sim state 216 by which the fault emulation starts with the state of the signal f.sub.im e. If the command activated by the control signal Cpt-e triggers a cyclic reading, i.e. a debug mode of operation, the input states and Scan-Out 218, 220 are executed; these states correspond mainly to the states 208, 210 described above in which the respective contents of the useful registers are read through the image registers and the detection chain. After reading the image registers in state 220, the operation by deactivation of the control signal Scan e goes back to the state sim 216; then, from this state, by the activation of the signal Cpt_e, it is possible to obtain again a snapshot of the internal switching states.

Loading registers R1, R3 with user-defined values (as described above for states 212, 214) can be considered as a configuration mode of operation. At the end of this configuration mode, by activating the control signal Fsim e, the output of the image register R2 is switched by the demultiplexer MUX4 directly on the scan o detection chain output, so that during the states 216, 218 , 220, the fault activation register R3 is released from the detection chain. The demultiplexer MUX4 thus represents a switching element for the internal switching of the detection chain, to shorten again the detection chain for the debug mode, that is to say the cyclical reading of the switching states of the useful register. , to obtain only the image element R2.

As appears in the table of FIG. 7c for MUX2, there is in this case a fault emulation so that, depending on the value recorded in the fault activation register R3, via the demulse - MUX2, the input signal (d) is transmitted in a clockwise fashion in the useful register R1, or the register is kept at a fault value by the feedback line 2 if the value registered in the activation register of defects R3 is equal to 1.

Next to the assembly of Figure 7b of the detection chain, there are mounting variants of the emulator cells with each other and with the control to achieve the function of the invention. For example, only one image register can be kept in a detection chain and then in a first step the value of the initialization of the useful register in the circuit is set. In a second step, it is then possible to precisely set the initialization for the fault activation register R3. Again, alternatively, two registers can be made accessible simultaneously by separate accesses the command; this can <I> by </ I> example be done by two separate detection strings. In the embodiment described above, an intermediate path has been chosen in which the two registers R2, R3 are integrated in the detection chain; however, it is possible to exclude the fault activation register R3 in debug mode from the detection chain, so that the reading of the image register R2 does not lengthen the time necessary for the time to be two incursions. Successive switching state during the debug mode is not increased.

The emulation described above of statistical defect can be done in parallel to a debugging process without disturbing it while allowing to emulate variable defects during the debugging process.

To allow such a dynamic fault emulation, in the preferred embodiment of the present invention, as shown in FIG. 1, it is possible to provide the additional dynamic fault activation register R4, as well as the register R5 fault level dynamic, additional. The operation of the circuit comprising these two additional registers will be described hereinafter with reference to FIGS. 1, 8 and 9.

In the dynamic emulation, for each useful register it is possible to position both a new fault value in the dynamic level register R5 as well as a dynamic activation signal of defects in the dynamic fault activation register. R4. A DFS upd command signal validates the new fault location when this signal is activated. When this DFS upd command signal is activated, the useful register R1 takes the new default value of the register R5 if the value stored in the dynamic fault activation register R4 indicates that a new fault positioning must be activated. The content of the dynamic fault activation register R4 is then transmitted to the register R3 to activate this fault positioning.

In order not to disturb either the normal mode or the current fault position, the detection chain in the exemplary embodiment shown in FIG. 1 is switched by signal DFS e so as to load a new fault position into the registers. R4, R5, without modifying the useful register R1 and the registers R2, R3. In addition, the fault position is mainly composed of a fault value on which the useful register R1 remains. Similarly, it is important to know the information that a fault must be activated for the cell concerned, that is to say the useful register R1 concerned or if the useful register must operate in normal mode. Basically, for a dynamic fault emulation, it is also necessary that new fault positions can be introduced during the operation of the useful circuit, that is to say the DUT circuit, without disturbing the normal operation without that a localized fault already is modified temporarily and, preferably, without interrupting the debugging operation. In principle, it is necessary to have a separate access from the control to the registers R4, R5. This can be achieved, on the one hand, by a completely separate access or, as in the embodiment of FIG. 1, by a corresponding wiring of the detection chain.

According to FIG. 8, the emulation of a dynamic fault begins with the initialization of the circuit, that is to say the setting of the initial values for the useful register and the initial fault positioning in the circuits. states 222 (Scan in) and 224 (Set), corresponding to the states 212, 214 of Figure 7a. After this configuration mode, there is again the fault search cycle and emulation corresponding to the state 226 in Figure 8 and again designated by state sim. Starting from this state 226, FIG. 8 again shows the cyclic reading of the internal switching states by the states 228, 230 corresponding mainly to the operating states 218, 220 of FIG. 7a.

As an alternative to this reading in the states 228, 230, it is also possible to carry out a new fault positioning which begins by setting the control signal DFS e to the state 232 called scan in fp. In this state, by the detection chain, in which the registers R4, R5 are switched, user-defined values are loaded in these registers. Registers R1-R3 thus remain unchanged. After the recording of new fault positions in the registers R4, R5 in the operating state 232, the status update 234 is changed to update, in which the DFS upd command signal is set. This activates the new fault position saved previously.

Since only one detection chain is used in the embodiment shown in FIG. 1 between the cells of the debugger / emulator circuit and the control positive, it is possible to perform the new positioning of the faults by the route. states 232, 234, only as a variant of the execution of a reading by the passage in the states 228, 230. However, it is obvious that by providing separate accesses to the registers R4 and R5, one can have a simultaneous passage in the states entered 228 and scan in fp 232 if the command and the interfaces are performed appropriately.

The present invention thus develops a defect emulation device that simultaneously enables fault analysis by circuit, by the cyclic extraction of internal switching states by image registers with a fault emulation of the internal nodes in the circuit. The device according to the invention allows both the positioning of statistical defects and that of dynamic defects.

The above exemplary embodiment of the present invention has been described with reference to image registers or defect positioning registers having a FIFO level equal to unity. As a variant, it is possible, in particular, to produce the registers R2, R4, R5 by registers having a higher FI level FO, enabling the emulation of dynamic defects in which the various defects are positioned only for a short duration in a cell such as this is clear in the following explanations.

If we configure the image register R2 as a single register with a FIFO level equal to unity, we can extract only in each second rate of the register, a value of the circuit whereas from a FIFO level equal at 2, can extract at each rate C2, a value of the circuit and supply it to the order. This allows an observation of the circuit without interval.

In an embodiment of the dynamic R4 fault activation register with a FIFO level equal to unity, only information indicating whether a new fault must be activated for global activation of the fault emulation or if the cell should work normally. If this register R4 is instead configured as a FIFO memory, continuously transmitting the stored information for an active emulation of faults, it is possible to activate faults for a predetermined duration and then deactivate them again, independently of the other cells. debugger and emulator circuit. For example, for a FIFO level equal to four and filling this FIFO register with the sequence [1,1,1,0], it is possible to obtain, after activation of the fault emulation, for three C2 cell rates. a state 1 is stored in the register R3, which in the embodiment shown represents the activation of the fault. The state 0 inscribes in the next rate, and which represents a deactivation of the fault, thus commutes the fault by excluding it again for three rates.

In a manner comparable to the register R4, it is also possible to record, in the register R5, a sequence of large defects if the register R5 is a FIFO memory. In each cadence we have the possibility to set the register to a defined value. This allows, on the one hand, to create a sequence of different levels of defects. On the other hand, even in the circuit, it is possible to generate a sequence of simulations of series circuit parts. In this way, it is also possible to simulate circuit parts defined within the useful circuit.

Claims (1)

<U> REVENDICATI 0 NS </ U> 1) Device for emulating faults in digital logic circuits (12) comprising a plurality of useful registers (R1) associated with nodes internal to the circuit, in which the states are recorded switching of the internal communication nodes dependent on the input signals, characterized in that each register (R1) is associated with an image register (R2) for extracting the switching state of the useful register) , by further associating with one or more useful registers (R1) a fault activation register (R3), connected to the useful register (R1) so that the output of the useful register (R1) is set to a value of default independently of the application of an input signal therefrom. 2) Device according to claim 1, characterized in that the image register (R2) and the fault activation register (R3) are mounted in a detection chain (40), so in a configuration mode, preset values can be pushed into the image register (R2) and the fault activation register (R3), the fault activation registers (R3) being cut off from the detection chain (40) out of configuration mode. 3) Device according to any one of the claims or 2, characterized in that to one or more useful registers (R1) which is associated with a fault activation register (R3), there is also associated a dynamic register of fault activation (R4) and a dynamic fault level register (R5), connected to the wanted register (R1) and to the fault activation register (R3) so that the output of the useful register is set for a period of time. predetermined, preferably during operation of the digital logic circuit (12), on a fault value independently of the input signal applied to the wanted register (R1). 4) Device according to claim 3, characterized in that the dynamic fault activation register (R4) defines whether the output of the useful register (R1) must be maintained at a fault value, defined by the dynamic level register of default (R5). Device according to any one of claims 3 4, characterized in that the dynamic fault activation register) and the dynamic fault level register (R5) are provided in a detection chain (40) so that in a dynamic fault configuration mode, predefined values can then be entered into them, the dynamic fault activation register (R4) and the dynamic fault level register (R5) being cut off from the detection chain ( 40) outside the dynamic fault configuration mode. Device according to one of Claims 1 5, characterized in that an image register (R2) and / or the dynamic fault activation register (R4) and / or the dynamic fault level register (R5) are in the form of FIFO memories.