FR2752486A1 - METHOD FOR MANUFACTURING A CAPACITOR STRUCTURE FOR A SEMICONDUCTOR MEMORY DEVICE - Google Patents

Abstract

The method of the invention makes it possible to form a charge storage capacitor having a tree structure, for a transfer transistor (14, 18, 16) of a DRAM memory cell. An electrode of the capacitor, connected to a drain region (16) of the transistor, includes a trunk-shaped layer (44A) and a branch-shaped layer (38). An opposite electrode (48) covers these layers, with the interposition of a dielectric layer (46). This structure makes it possible to increase the charge storage capacity for the same area occupied on the surface of the substrate.

Description

METHOD FOR MANUFACTURING A STRUCTURE

CAPACITOR FOR A DEVICE

FROM MEMORY TO SEMICONDUCTORS

  The invention relates generally to metering devices.

  semiconductor memory, and more particularly relates to a method for manufacturing a dynamic random access memory (or DRAM) cell having a transfer transistor and a charge storage capacitor.

  Figure 1 is a circuit diagram of a single metal cell

  classic moire for a DRAM device. As depicted in the

  sin, a DRAM cell is essentially constituted by a transfer transistor T and a charge capacitor C. A source terminal of the transfer transistor T is connected to a corresponding bit line BL, and a drain terminal of the transistor is connected to a storage electrode 6 of the charge storage capacitor C. A gate terminal of the transfer transistor T is connected to a word line WL

  corresponding. An opposite electrode 8 of the capacitor C is con-

  connected to a constant voltage source. A dielectric film 7 is formed between the storage electrode 6 and the opposite electrode 8 of the capacitor C. In the conventional DRAM manufacturing process, essentially a practically two-dimensional capacitor, called a planar type capacitor, is used for DRAM devices. classics with a storage capacity of less than 1 MB (megabyte). In the case

  a DRAM memory having a memory cell that uses a

  planar type densifier, electrical charges are stored on

  electrodes arranged on the main surface of a semicon substrate

  conductor, which means that the main surface must have a relative area

  ment large. This type of memory cell is therefore not suitable for

  a DRAM memory with a high level of integration. For a me-

  DRAM memory with high level of integration, like a DRAM memory

  having more than 4 MB of memory, we introduced a condense structure

  three-dimensional sator, constituting what is called a capacitor

  stacked or trench type.

  With stacked or trench type capacitors, it was possible to obtain a larger memory capacity for a

  similar surface area. However, to achieve a semi-device

  conductors with an even higher level of integration, such as a circuit with a very high level of integration (or VLSI) having a capacity of 64 MB, a capacitor with a simple three-dimensional structure,

  like the stacked type or the classic trench type, turns out to be insufficient

  health. A solution to improve the capacity of a capacitor

  DRAM memory cell is to use what is called the con-

  stacked fin type densifier, an example of which is provided by Ema et al., in "3-Dimensional Stacked Capacitor Cell for 16M and 64M

  DRAMs ", International Electron Devices Meeting, pages 592-595, Decem-

  bre 1988. The stacked fin type capacitor includes electro

  electrodes and dielectric films which extend in the form of a

  lette in a set of stacked layers. DRAM memories having the finned type stacked capacitor are also described in U.S. patents. No. 5,071,783 (Taguchi et al); 5,126,810 (Gotou);

  5,196,365 (Gotou); 5,206,787 (Fujioka).

  Another solution to improve the capacitance of a capacitor

  of memory cell is to use what's called conden-

  stacked cylindrical type, an example of which is proposed by Wakamiya et al., in "Novel Stacked Capacitor Cell for 64-Mb DRAM",

  1989, Symposium on VLSI Technology, Digest of Technical Papers, pa-

  ges 69-70. The stacked cylindrical type capacitor includes electrodes and dielectric films which extend with a shape

  cylindrical, so as to increase the surface areas of the electrodes.

  A DRAM memory cell having the stacked capacitor of cy- type

  Lindric is also described in the U.S. Patent. No. 5,077,688

(Kumanoya et al.).

  With the trend towards increased integration density, it is born

  stop further reducing the size of the DRAM memory cell in a plane (that is, the surface area it occupies in a plane). In general, a reduction in the size of the conventional cell leads to a reduction in the charge storage capacity (electrical capacity) of the conventional capacitors. In addition, when the

  electrical capacity is reduced, the probability of transient errors

  both the incidence of a rays is increased. There is therefore a need in this area for a new storage capacitor structure which, while occupying a smaller area in a plane, can

  maintain the same electrical capacity, as well as on an appropriate process

prayed to fabricate the structure.

  An object of the invention is therefore to provide a method of manufacturing

  cation of a semiconductor memory device having a tree type capacitor structure which provides increased area for charge storage, without increasing the surface area which is used

in the device.

  In accordance with the foregoing objects of the invention, as well as others, the invention provides a new and improved method for

  fabricate a semiconductor memory device.

  According to a preferred embodiment of the invention, the semiconductor memory device comprises a substrate, a

  transfer transistor formed on the substrate and a stock capacitor

  age electrically connected to a source / drain region of the transfer transistor. The process includes the following steps:

  first insulating layer on the transfer transistor, a layer is formed

  protection against attack on the first insulating layer, a second insulating layer is formed, a stacked layer is formed on the

  second insulating layer, the stacked layer containing a portion in

  line which exposes the second insulating layer, a third insulating layer is formed at a periphery of the recessed part, a fourth insulating layer is formed to fill the recessed part, the third insulating layer, the fourth insulating layer is removed and a part of the second insulating layer being located directly below the third insulating layer, to form an opening, the opening not exposing the protective layer against attack, a

  first conductive layer to fill the recessed part and open it

  ture, we remove the stacked layer, we form a fifth layer iso-

  bonding, a second conductive layer is formed on the fifth insulating layer, the second conductive layer penetrating at least through the fifth insulating layer, the first conductive layer, the second insulating layer, the attack protection layer and the first layer insulating, and being electrically connected to the drain region, part of the second conductive layer is removed to form a conductive layer in the form of a trunk, the first conductive layer forming a conductive layer in the form of a branch, and the conductive layers in form of trunk and branch-shaped forming together a storage electrode of the storage capacitor, removing the second and fifth insulating layers, forming a dielectric shape on bare surfaces of the first and second conductive layers, and forming a third layer conductive on a surface of the layer

  dielectric, to form an opposite electrode.

  According to another aspect of the invention, the trunk-shaped conductive layer is an integrated and electrically connected element to the source / drain region. The cross section of the trunk-shaped conductive layer can be T-shaped, or this layer can be

similar to a full cylinder.

  According to another aspect of the invention, several steps are in

  additionally included after removal of the stacked layer and before forming

  the fifth insulating layer. The additional steps are as follows: a sixth insulating layer is formed and then a fourth insulating layer is formed on the sixth insulating layer. Thus, the second conductive layer is formed so as to penetrate through the fourth conductive layer and the sixth insulating layer. A pattern is also formed in the fourth conductive layer so

  that it becomes part of the conductive layer in the form of a branch

  che. The sixth insulating layer is then removed. We also form the

  dielectric film on a bare surface of the fourth layer

conductive.

  According to another aspect of the invention, a chemomechanical or attack technique is used to remove part of the second

  conductive layer on the fifth insulating layer.

  According to another aspect of the invention, the steps from the step of forming the second insulating layer to the step of removing the stacked layer are repeated at least once before the formation of the fifth insulating layer. Therefore, at least

  two branch-shaped conductive layers are formed.

  Another preferred embodiment of the invention provides a method of manufacturing a semiconductor memory device. The

  semiconductor memory device includes a substrate, a tran

  transfer sistor formed on the substrate, and a storage capacitor electrically connected to a source / drain region of the transistor

  transfer. The process comprises the following stages: a pre-

  first insulating layer on the transfer transistor, a pre-

  first conductive layer which penetrates at least through the first insulating layer and which is electrically connected to the region of

  source / drain, we form a second insulating layer, we form a

  che stacked, containing a recessed part which exposes the second layer

  insulating che, a third insulating layer is formed at a periphery of the recessed part, a fourth insulating layer is formed to fill

  the recessed part, the first and fourth insulating layers are removed

  tes and a part of the second insulating layer being directly below the third insulating layer, to form an opening, the opening being in the second insulating layer but not exposing the first conductive layer, a second conductive layer to fill the recessed portion and the opening, remove the stacked layer, form a fifth insulating layer, form a third conductive layer which penetrates at least through the fifth insulating layer, the second conductive layer and the second insulating layer, so as to be electrically connected to the first conductive layer, a pattern is defined in the first conductive layer for

  form part of the conductive layer in the form of a trunk, the pre-

  third and conductive layers forming the trunk-shaped conductive layer, the second conductive layer forming a branch-shaped conductive layer, and the trunk-shaped and branch-shaped conductive layers forming a storage electrode of the storage capacitor. The second and fifth insulating layers are removed, a dielectric layer is formed on exposed surfaces of the first, second and third conductive layers, and a fourth conductive layer is formed so as to form an opposite electrode

of the storage capacitor.

  According to another aspect of this latter preferred embodiment

  d, steps for forming a layer of protection against attack on a first insulating layer, and then for forming a seventh

  insulating layer on the attack protection layer, are in or

  be carried out just after the formation of the first insulating layer.

  Then the first conductive layer is formed so that it penetrates

  be further through the seventh insulating layer and the pro-

  tection against attack. The seventh insulating layer is removed before the

  formation of the dielectric layer.

  The invention will be better understood on reading the description which

  will follow embodiments, given by way of nonlimiting examples.

  The following description refers to the accompanying drawings, in which:

  Figure 1 is a circuit diagram of a single metal cell

  DRAM device memory; FIGS. 2A to 21 are sections showing the steps involved in a method of manufacturing a memory device using

  semiconductors according to a first embodiment of the invention

  tion; Figures 3A to 3E are sections showing the steps

  involved in a manufacturing process for a metering device

  semiconductor memory according to a second embodiment of the invention; Figure 4 is a section of a third embodiment of the semiconductor memory device of the invention; Figures 5A to 5E are sections showing the steps

  involved in a manufacturing process for a metering device

  semiconductor memory according to a fourth preferred embodiment of the invention; Figures 6A to 6E are sections showing the steps

  involved in a manufacturing process for a metering device

  semiconductor memory according to a fifth preferred embodiment of

  reading of the invention; and Figure 7 is a sectional view showing a semiconductor memory cell having a tree type capacitor according to

  a sixth embodiment of the invention.

  First embodiment FIGS. 2A to 21 are sections representing the steps which

  involved in a manufacturing process of a first embodiment

  preferred position of the semiconductor memory device according to the invention.

  Referring first to FIG. 2A, we note that we learn

  applies thermal oxidation to a silicon substrate 10 by the process

  from LOCOS ("local oxidation of silicon", i.e. local oxidation of

  silicon), to form a field oxide film 12 having for example-

  ple a thickness of about 300 nm, on the silicon substrate 10. In-

  thereafter, thermal oxidation is again applied to the silicon substrate.

  cium 10 to form a gate oxide layer 14 having a thickness which is for example about 15 nm. After this, we put a layer

  polycrystalline silicon over the entire upper surface of the

  silicon trat 10, by chemical vapor deposition (or CVD), or

  chemical deposit in the vapor phase at low pressure (or LPCVD), up to a thickness which is for example around 200 nm. We can broadcast

  suitable impurities, such as phosphorus ions, in the coating

  polycrystalline silicon, to increase its conductivity. In addition, one can for example deposit a layer of refractory metal on the layer of polycrystalline silicon and then apply an annealing operation thereto.

  to transform the polycrystalline silicon layer into polycrystalline silicon

  tallin / silicide, in order to further increase the conductivity of the polycrystalline silicon layer. The refractory metal layer may for example be a tungsten layer (W), deposited for example up to a thickness of approximately 200 nm. We then carry out a process of photolithography and classic attack on the edge, to define and

  forming polycrystalline silicon metallization layers on the wafer

  lin, which are called word lines WL1 and WL2, which fulfill the function of grids, as shown in FIG. 2A. Next, a drain region 16 and a source region 18 are formed in the substrate by

  silicon 10, for example by implanting arsenic ions in

  gions selected on the silicon substrate 10. During this process, the word lines WL1 and WL2 fulfill the function of a mask for implantation, and the arsenic ions are implanted for example with a

  energy of 70 keV and a concentration of approximately 1 x 1015 atoms / cm2.

  Referring next to FIG. 2B, it is noted that in a

  next step an iso- layer is deposited over the entire slice

  lante 20, such as borophosphosilicate glass (or BPSG), by chemical vapor deposition (or CVD), for example up to a thickness

  about 700 nm. After this, we use the same CVD process to de-

  applying a layer of protection against attack 22, such as a layer of silicon nitride, on the insulating layer 20, for example up to a

thickness of about 100 nm.

  Referring to FIG. 2C, it is noted that a layer is deposited

  thick che 24 of an insulating material, such as silicon dioxide, by the CVD process, on the attack protection layer 22, up to

  a thickness which is about 700 nm. After this, we successively deposit

  Vement on the insulating layer 24 an insulating layer and a layer of sacrificial polycrystalline silicon. Then we perform on the edge a

  classic photolithography and attack process, so as to remove

  worm selected parts of the insulating layer and the sacrificial polycrystalline silicon layer. The remaining part of the insulating layer

  is indicated by reference 26 and the remaining part of the silicon layer

  sacrificial polycrystalline cium is indicated by the reference 28 on the fi

  gure 2C. The insulating layer 26 may for example be silicon nitride.

  cium deposited up to a thickness which is for example around 100 nm, and the sacrificial polycrystalline silicon layer 28 is deposited up to a thickness which is for example around 100 nm. The insulating layer 26 and the sacrificial polycrystalline silicon layer 28 form

  in combination a stacked structure (26, 28) having inside a

  verticality 30. The cavity 30 is practically aligned with the region of

drain 16 located below.

  Referring next to Figure 2D, we note that in the next step

  In addition, spacers 32 of silicon dioxide are formed on the side walls of the stacked structure (26, 28). In this embodiment, the silicon dioxide spacers 32 are formed by first depositing a layer of silicon dioxide, to a thickness which is for example about 100 nm, and then reducing by attacking the thickness of the layer of silicon dioxide. Then deposited on the wafer a layer 34 of an insulating material, such as silicon nitride, by CVD, to a thickness which is for example about 200 nm. The insulating layer 34 practically fills the cavity 30. A chemo-mechanical polishing (or CMP) is then carried out on the upper surface of the wafer, so as to remove by polishing the insulating layer 34, at least until the surface of the structure

stacked (26, 28) either naked.

  Referring to FIG. 2E, it is noted that the stacked structure (26, 28) and the insulating layer (34) are then used together as an attack mask, by applying an attack operation to the edge for removing the silicon dioxide spacers 32. After the complete removal of the silicon dioxide spacers 32, the etching process continues, still using the stacked structure (26, 28) and the insulating layer (34) as an attack mask,

  to remove by attack the parts of the insulating layer 24 which are

  wind directly below the positions at which the test elements

  32 silicon dioxide placement were originally. The attack

  is controlled so as to continue to a predefined depth

  finished to form cavities 36 in the insulating layer 24. We note-

  ra that the depth of the cavities 36 can be arbitrarily adjusted, but

  that the bottoms of the cavities 36 must be at a certain distance

  above the upper surface of the attack protection layer

  that, 22. Then, using the sacrificial polycrystalline silicon layer 28 as an attack mask, the wafer is attacked to remove

the insulating layer 34.

  Referring next to FIG. 2F, it is noted that a layer of polycrystalline silicon 38 is then deposited on the stacked structure (26, 28) and the insulating layer 24, up to a thickness which is for example around 100 nm, this layer practically filling the cavities 36. It is possible to diffuse in the layer of polycrystalline silicon

  38 arsenic ions, for example, to increase its conductivity.

  After this, chemo-mechanical polishing is carried out on the wafer, at least until the upper surface of the insulating layer 26 is

  naked. The remaining part of the polycrystalline silicon layer is indi-

  quée by the reference 38 in Figure 2F. Polishing also removes the sacrificial polycrystalline silicon layer 28. Then, jointly using as a protective mask against attack the layer

  of polycrystalline silicon 38 and the insulating layer 24, an operation is carried out

  wet attack ration on the wafer, to remove the layer

  insulating 26. The stacked structure (26, 28) is therefore entirely removed.

  An insulating layer 40 is then deposited on the wafer, consisting for example of silicon dioxide, by CVD, until a

  thickness which is for example around 200 nm.

  Referring next to FIG. 2G, it is noted that in a following step, a conventional photolithography and etching process is carried out to form a storage electrode contact hole 42 through the insulating layer 40, the layer of polycrystalline silicon 38, the

  insulating layer 24, the protective layer against attack 22, the layer

  insulating che 20 and the gate oxide layer 14, up to the upper surface

  of the drain region 16. A layer is then deposited by CVD

  of polycrystalline silicon 44, so as to fill the contact hole with electro

  storage trode 42 and to cover the upper surface of the layer

insulating 40.

  Referring next to FIG. 2H, it is noted that a conventional photolithography and attack process is then carried out for

  set the storage electrode for the data storage capacitor

  born of the DRAM cell which must be trained. Then using the cou-

  protection against attack 22 as the end point of the attack, we

  performs a wet attack on the wafer, to completely remove

  rement both the insulating layer 40 and the insulating layer 24. This completes the manufacture of the storage electrode for the capacitor.

  DRAM cell data storage. As depicted in the

  sin, the storage electrode comprises a layer of polycrystalline silicon

  trunk-shaped flax 44A which has a cross-section practically in

  T, and branch-shaped polycrystalline silicon layer sections

  che 38, which have a practically L-shaped cross section. The root 44B (lower end) of the trunk-shaped polycrystalline silicon layer 44A is electrically connected to the drain region 16 of the

  DRAM cell transfer transistor. The layer sections of si-

  branch-shaped polycrystalline silicon 38 having an L-shape, par-

  laterally from the vertical part 44C (they are perpendicular to the vertical part 44C of the trunk-shaped polycrystalline silicon layer 44A, having a T shape), and they then extend downwards towards the substrate 10. Because of its particular forms, too

  although overall that for the constituent elements, the stock electrode-

  age is called hereinafter in this description "storage electrode

  tree type ", and the data storage capacitor which is

  thus formed is called "tree type capacitor".

  Referring further to FIG. 21, it is noted that in a following step, on the bare surfaces are formed both the trunk-shaped polycrystalline silicon layer 44A and the shaped polycrystalline silicon layer sections. branch 38, a dielectric layer 46, consisting for example of silicon dioxide, silicon nitride, NO (silicon nitride / silicon dioxide), ONO (silicon dioxide / silicon nitride / silicon dioxide), or the like . Then, to complete the manufacture of the tree type capacitor, we train on the

  dielectric layer 46 a layer of polycrystalline silicon 48 filled

  sant the function of an electrode opposite to the storage electrode (44A, 38). The process for the formation of the opposite electrode 48 comprises a first step of depositing polycrystalline silicon by CVD to a thickness which is for example around 100 nm, a second step of diffusion of N-type impurities in the polycrystalline silicon, to increase its conductivity, and a final step consisting in carrying out a photolithography and etching process on polycrystalline silicon

  to form the desired opposite electrode 48.

  To complete the manufacturing of the DRAM cell, the following steps

  include the manufacturing of bit lines, measurement ranges

  nexion, interconnections and passivation layers, as well as con-

  addition. These steps only use conventional techniques,

  so there is no need to describe them here.

Second embodiment

  In the first preceding embodiment, 'each elect

  storage trode comprises a single conductive layer in the form of a branch, having an L-shape, comprising two sections. The invention is however not limited to the use of a single set of conductive layer sections in the form of an L-shaped branch. It is possible to incorporate

  two or more sets of strand-shaped conductive layer sections

  che en L. The second embodiment envisaged here comprises an elec-

  storage trode with two sets of conductive layers in the form of an L-shaped branch. FIGS. 3A to 3E are sections representing the steps involved in a method of manufacturing a second mode of

  realization of the semiconductor memory device in accordance with the

  vention, this device comprising a condensate storage electrode

  tree type capacitor, having two sets of L-shaped branches. The tree type capacitor of the second embodiment is based on the

  structure of figure 2F. The elements of FIGS. 3A to 3E which have a structure and a purpose identical to those of FIG. 2F are designated by

  the same reference numbers.

  Referring to Figure 3A, in conjunction with Figure 2F, we

  note that after having formed the structure of figure 2F, one deposits succes-

  on the insulating layer 40 an insulating layer and a sacrificial polycrystalline silicon layer. Then we go through a process

  classic photolithography and etching to remove dry parts

  lectionnées both of the insulating layer and the sacrificial layer.

  The remaining part of the insulating layer is indicated by the reference 50, and the remaining part of the sacrificial polycrystalline silicon layer is indicated by the reference 52 in FIG. 3A. The insulating layer 50 can consist of silicon nitride deposited up to a thickness which is

  example of around 100 nm, and the sacrificial polycrystalline silicon layer

  cielle 52 is deposited to a thickness which is for example about

  ron 100 nm. The insulating layer 50 and the sacrificial polycrystalline silicon layer 52 form in combination a stacked structure (50, 52) having inside a cavity 54. The cavity 54 here has a width greater than the cavity 30 which is formed during steps previously accomplished, shown in Figure 2C, and it is practically

  vertically aligned with the drain region 16.

  Referring next to FIG. 3B, it is noted that in a next step, spacers made of silicon dioxide, 56, are formed on the side walls of the stacked structure (50, 52). In this embodiment, the silicon dioxide spacers 56 are formed by first depositing a layer of silicon dioxide, up to

  a thickness which is for example around 100 nm, and while performing

  following an attack operation to reduce the thickness of the layer. An insulating layer 58 is then formed, for example by depositing on the edge of the silicon nitride, by CVD, up to a thickness which is for example around 200 nm. The insulating layer 58 practically fills the cavity 54. After this, chemo-mechanical polishing is applied to the upper surface of the wafer to remove by polishing part of the insulating layer 58, at least until the upper surface

  of the stacked structure (50, 52) is exposed.

  Referring next to FIG. 3C, it is noted that by using the stacked structure (50, 52) and the insulating layer 58 jointly as an attack mask, the edge is attacked to remove the dioxide spacers. of silicon 56. After the complete removal of the spacers of silicon dioxide 56, the attack continues,

  always using as an attack mask both the em-

  crushed (50, 52) and the insulating layer 58, to remove by attack parts

  parts of the insulating layer 58 which lie directly below the positions at which the silicon dioxide spacers

  56 were originally. The attack is commanded to reach-

  dre a predetermined depth to form cavities 60 in the insulating layer 58. It will be noted that the depth of the cavities 60 can be arbitrarily adjusted, but that the bottom of the cavities 60 must be at a certain distance above the upper surface of the layer of

  protection against attack 22. After the cavities 60 have been completely

  formed, an additional attack operation is applied to the wafer

* to remove the insulating layer 58, using as a mas-

  than attacking the sacrificial polycrystalline silicon layer 52.

  Referring to Figure 3D, we note that in a next step

  vante, a layer of polycrystalline silicon is deposited both on the stacked structure (50, 52) and on the insulating layer 40, to a thickness which is for example about 100 nm, so as to practically fill the cavity 60. Can be diffused in the silicon layer

  polycrystalline for example arsenic ions, to increase its conduc-

  activity. After this, chemo-mechanical polishing is carried out until

  that the upper surface, at least, of the insulating layer 50 is exposed.

  The remaining part of the polycrystalline silicon layer is indicated by the reference 62 in FIG. 3D. By this process, the silicon layer

  polycrystalline sacrificial 52 is removed. Then, using joint-

  as a protective mask against attack the silica layer

  polycrystalline cium 62 and the insulating layer 40, a wet etching operation is applied to the wafer to remove the insulating layer 50. The entire stacked structure (50, 52) is thus removed. Next, an insulating layer 64, such as a layer of silicon dioxide, is deposited by CVD, up to a thickness which is for example around nm. Referring next to FIG. 3E, it is noted that a conventional photolithography and etching process is then carried out to form a storage electrode contact hole 66 through the insulating layer 64, the polycrystalline silicon layer 62, the insulating layer 40, the polycrystalline silicon layer 38, the insulating layer 24, the attack protection layer 22, the insulating layer 20 and the gate oxide layer 14, up to the upper surface of the drain region 16. After this, a layer of polycrystalline silicon 68 is deposited, by

  CVD, on insulating layer 64, to fill the contact hole with electricity

  storage trode 66 and to cover the upper surface of the diaper

insulating 64.

  Then, a new class process is carried out on the wafer.

  photolithography and attack sic, to define the position of the elect

  storage trode for the data storage capacitor of the DRAM cell to be formed. After this, using the layer

  of protection against attack 22 as an end point of attack, we apply

  that at the edge a wet attack process to remove

  fully insulating layers of silicon dioxide 64, 40 and 24.

  This completes the manufacturing of the storage electrode for the condensate.

  DRAM cell data storage device.

  As shown in FIG. 3E, the storage electrode comprises a layer of polycrystalline silicon in the form of a trunk 68 which has a practically T-shaped cross section, and two layers of polycrystalline silicon in the form of a branch 62 and 38 each having two segments of which the cross section has practically an L shape. The root 68B (lower end) of the shaped polycrystalline silicon layer

  of trunk 68 is electrically connected to the drain region 16 of the tran-

  DRAM cell transfer sistor. The two sets of branch-shaped polycrystalline silicon layers 62 and 38, having a shape

  L, depart respectively laterally (horizontally, i.e. pa-

  parallel to the surface of the substrate) of the vertical part 68A of the cover

  polycrystalline silicon in the form of a trunk 68, having a T shape, and they then extend downwards. All the following steps are classic steps to complete the manufacturing of the DRAM cell,

  so there is no need to describe them here.

Third embodiment

  In the first and second preferred embodiments pre-

  above, each tree type capacitor has a part in

  shape of trunk which has a cross section practically in T. The

  vention is however not limited to the formation of the trunk portion

  with such a shape. The conductive trunk-like layer can also

  Also be a vertical pillar, as described below.

  Figure 4 shows a section showing the steps which

  come in a manufacturing method of the third embodiment of the invention, which comprises a shaft type capacitor having a

  conductive layer in the form of a trunk which has the shape of a pillar. The con-

  tree type densifier of this embodiment is based on the structure of Figure 2G. Elements of FIG. 4 whose structure and function are identical to those of FIG. 2G are designated by the

same reference numbers.

  Referring to Figure 4, in conjunction with Figure 2G, it is noted that upon completion of the structure which is shown in Figure

  2G, chemo-mechanical polishing is carried out on the edge to remove

  worm by polishing the horizontal part 44A of the poly-silicon layer

  crystalline 44, at least until the upper surface of the insulating layer 40 is exposed, leaving only the vertical part 44C of the

  polycrystalline silicon layer 44, which has practically a pi-

  bind. A wet attack operation is then carried out using

  reading the attack protection layer 22 as the end point of attack, to completely remove the insulating layers of silicon dioxide 40 and 24. This completes the manufacture of the storage electrode

  for the DRAM cell data storage capacitor.

  As shown in Figure 4, the storage electrode includes a

  44C trunk-shaped polycrystalline silicon layer which has practical-

  a pillar shape, and a layer of polycrystalline silicon in

  form of branch 38 which comprises two segments, the cross section of which

  versale has practically an L shape. The root 44B (lower end

  lower) of the trunk-shaped polycrystalline silicon layer 44C, having the shape of a pillar, is electrically connected to the drain region 16 of the transfer transistor of the DRAM cell. The L-shaped polycrystalline silicon layers 38, having an L shape, extend laterally (perpendicular to the trunk-like layer 44C and parallel to the upper surface of the substrate 10) from the polycrystalline silicon layer 44C, and they are '' then extend downwards

  substrate direction 10. All of the following steps to complete the fa-

  DRAM cell bricings are classic, which makes it not

  necessary to describe them further.

  In this third preferred embodiment, the layer

  trunk-shaped ducting 44C, having the shape of a pillar, is formed using chemo-mechanical polishing. However, alternatively,

  it can be formed by a thickness reduction attack to remove

  ver the horizontal part 44A of the polycrystalline silicon layer 44 which is shown in FIG. 2G, leaving the vertical part 44C. Another possibility for forming the trunk-shaped conductive layer 44C, having the shape of a pillar, consists in growing by epitaxy a layer of polycrystalline silicon in the storage electrode contact hole 42. The epitaxial layer of silicon polycrystalline which is formed then fulfills the function of the conductive layer in the form of a trunk 44C,

shaped like a pillar.

  Fourth embodiment In the first, second and third previous embodiments, the trunk-shaped part of each storage electrode is an element formed in one piece, and each conductive layer in

  branch shape, seen in section, includes two L-shaped segments, or

  tokens, which start from the vertical part of the conductive layer in

trunk shape.

  The invention is however not limited to such structures.

  A fourth embodiment, envisaged by way of example, comprises a storage electrode having a conductive layer in the form of a trunk consisting of two or more trunk-shaped segments, and a conductive layer in the form of a branch having two offspring, a child

  having a practically L-shaped cross section (formed by a seg-

  horizontal and one vertical segment), and the other offspring being made up

  only by a horizontal segment.

  FIGS. 5A to 5E are sections showing the steps involved in a manufacturing process of the fourth mode of

  production. The tree type capacitor of the fourth embodiment

  The reading is based on the structure of Figure 2B. The elements in FIGS. 5A to 5E which have a structure and a purpose practically identical to

  those of FIG. 2B are designated by the same numerical references

ques.

  Referring to Figure 5A in conjunction with Figure 2B, it is noted that after the completion of structure 2B, a process is used

  classic photolithography and attack to form a hole

  storage electrode tact 70 through the protective layer against

  The attack 22, the insulating layer 20 and the gate oxide layer 14, up to

  than at the upper surface of the drain region 16. Next, a layer of polycrystalline silicon 72 is deposited by CVD. Arsenic ions can, for example, be diffused in the polycrystalline silicon layer 72, in order to increase its conductivity. As shown in Figure 5A,

  the polycrystalline silicon layer 72 fills the contact hole with electro

  storage trode 70 and covers the upper surface of the attack protection layer 22. A thick insulating layer 74 is then formed, for example by depositing silicon oxide on the polycrystalline silicon layer 72, up to a thickness which is about 700 nm. After this, we deposit successively by CVD on the iso- layer.

  lante 74 an insulating layer and a polycrystalline silicon layer sa-

  critical. Then we carry out a classic photolithographic process.

  phie and attack on the wafer to remove selected parts of the insulating layer and the sacrificial layer. The remaining part of the insulating layer is indicated by the reference 76, and the remaining part of

  the sacrificial polycrystalline silicon layer is indicated by the ref-

  rence 78, in FIG. 5A. The insulating layer 76 can be formed in deposition

  for example silicon nitride up to a thickness which is

  example of around 100 nm, and the layer of polycrystalline silicon is deposited

  sacrificial tallow 78 to a thickness which is for example around

  nm. The insulating layer 76 and the polycrystalline silicon layer sa-

  crificiel 78 form in combination a stacked structure (76, 78) having

  inside a cavity 80. The cavity 80 is practically aligned vertica-

  with one side (the left side in Figure 5A) of the region of

drain 16.

  Referring next to FIG. 5B, we note that we form

  then spacers of silicon dioxide 82 on the pa-

  lateral kings of the stacked structure (76, 68). In this embodiment

  tion, the silicon dioxide spacers 82 are formed by first depositing a layer of silicon dioxide to a thickness which is for example about 100 nm, and then applying an etching operation to reduce the thickness of the layer. Then deposited on the wafer, by CVD, an insulating layer 84, consisting for example of silicon nitride, to a thickness which is for example about 200 nm. The insulating layer 84 practically fills the cavity

  80. A chemo-physical polishing is then carried out on the iso- layer.

  lante 84, at least until the upper surface of the structure

stacked (76, 78) either naked.

  Referring next to FIG. 5C, it is noted that by using the stacked structure (76, 78) and the insulating layer 84 jointly as an attack mask, the wafer is attacked to remove the dioxide spacers. of silicon 82. After the complete removal of the spacers 82, the attack continues, still using at

  title of attack mask for both the stacked structure (76, 78) and the

  insulating che 84, for removing by attack parts of the insulating layer 74 which are located directly below the positions at which the spacers 82 were originally located. The attack is

  controlled so as to form cavities 86 of predetermined depth

  finished in the insulating layer 74. It should be noted that the depth of the cavities 86 can be arbitrarily adjusted, but that the bottom of the cavities 86 must be at a certain distance above the upper surface of the polycrystalline silicon layer 72. Next , using the sacrificial polycrystalline silicon layer 78 as an attack mask, an etching operation is carried out to remove the insulating layer 84. Next, a layer of polycrystalline silicon is deposited on the stacked structure (76, 78) and on the insulating layer 74, up to a

  thickness which is for example about 100 nm, this layer fills

  practically providing the cavities 86 and 80. It is possible, for example, to diffuse

  full of arsenic ions in the po! ycrystalline silicon layer, for

  increase its conductivity. A chemo-polishing is then carried out

  mechanical at least until the top surface of the layer

  insulating 76 either bare. The remaining part of the poly- silicon layer

  lens is indicated by reference 88 in Figure 5C. By this process

  above, the sacrificial polycrystalline silicon layer 78 is also

lifted.

  Referring next to FIG. 5D, it is noted that by using

  title of protective mask against attack both the layer of sili-

  polycrystalline cium 88 and the insulating layer 74, an operation is carried out

  wet attack to remove the insulating layer 76. The structure

  complete stacked ture (76, 78) is therefore removed by this process. An insulating layer 90 is then deposited by CVD, consisting for example

  in silicon dioxide, up to a thickness which is for example about

  ron 200 nm. Then we carry out on the wafer a classic process

  photolithography and attack, to successively remove by attack

  that selected parts of the insulating layer 90, of the polycrystalline silicon layer 88 and of the insulating layer 74, until the upper surface of the polycrystalline silicon layer 72 is exposed,

  to thereby form a hole 92 and to separate the layer of poly-

  crystalline 88 in branches (offspring) left and right 88A and 88B, having an L shape. Then, in the hole 90 is formed a layer of polycrystalline silicon 94 in the form of a pillar, for example by epitaxy or by

deposition and attack process.

  Referring now to FIG. 5E, it is noted that an additional photolithography and attack process of the conventional type is then carried out on the wafer, for the selective removal of parts of the

  layers of polycrystalline silicon 88 and 72, so as to define an electro

  storage trode for the data storage capacitor of the

  DRAM cell to be trained. This process has the effect of

  to the vertical segment 88B2 of the left L-shaped branch 88B of the layer

  of polycrystalline silicon 88, leaving only its horizon segment-

  tal 88B1, in the form of an offspring. After this, using the attack protective layer 22 as the end point of attack, a wet attack operation is applied to the wafer to remove the

  insulating layers of silicon dioxide 90 and 74. This completes the manufacture

  cation of the storage electrode for the data storage capacitor for the DRAM cell. As shown in the drawing, the storage electrode comprises a conductive layer in the form of a lower trunk 72A, a layer of polycrystalline silicon in the form of an upper trunk 94, which starts from the conductive layer in the form of a trunk

  lower 72A, and a branch-shaped conductive layer consisting

  both in a first offspring 88A directed to the right, which has a practically L-shaped cross section, and in a second offspring 88B directed to the left which comprises only a horizontal segment. The lower trunk-shaped conductive layer 72A has a substantially T-shaped cross section, and its root 72B (lower end) is electrically connected to the drain region 16 of the transfer transistor of the DRAM cell. The trunk-shaped polycrystalline silicon layer

  upper 94 is practically pillar-shaped, extending vertically-

  ment from the upper surface 72C of the conductive layer in the form of a lower trunk 72A. The branch-shaped polycrystalline silicon layer (88A, 88B1) extends laterally from the upper trunk-shaped polycrystalline silicon layer 94, that is to say it extends

  horizontally and practically perpendicular to the layer 94.

  Fifth embodiment In addition to the four previous embodiments,

  killing examples, the fifth embodiment includes a con-

  tree type densifier which includes a storage electrode having L-shaped conductive layers, together with

  horizontally extending branch-like conductive layers.

  Furthermore, in the previous fourth embodiment, the horizontal part of the conductive layer in the form of a lower trunk 72A comes into contact with the underlying attack protection layer 22. The invention is however not limited to this. The lower surface of the horizontal part of the lower trunk-shaped conductive layer 72A can be separated by a certain distance from the

  protective layer against the underlying attack 22, so as to increase

  further lie the surface area of the storage electrode.

  Figures 6A to 6E are sections showing the steps involved in a manufacturing process of a fifth preferred embodiment of the invention, in which the tree type capacitor is based on the structure of Figure 2B. The elements represented

  in FIGS. 6A to 6E, the structure and purpose of which are practically identical

  ticks to those of Figure 2B are designated by the same reference numerals. Referring to Figure 6A in conjunction with Figure 2B, it is noted that after the completion of the structure of Figure 2B, an insulating layer 96 is formed, for example by deposition of silicon dioxide by

  CVD, on the attack protection layer 22, up to a thick-

  which is for example about 100 nm. We then perform a pro-

  classic cessation of photolithography and wafer attack, fa-

  how to form a storage electrode contact hole 98 through the insulating layer 96, the attack protection layer 22, the insulating layer 20 and the gate oxide layer 14, up to the upper surface of the drain region 16. A layer of polycrystalline silicon 100 is then deposited by CVD on the insulating layer 96. Arsenic ions can for example be diffused in the polycrystalline silicon layer 100 to increase its conductivity. The polycrystalline silicon layer 100

  fills the storage electrode contact hole 98 and covers the over-

  upper face of the insulating layer 96. Next, a thick insulating layer 102, for example made of silicon dioxide, is deposited on the polycrystalline silicon layer 100, up to a thickness which is for example 700 nm. Then deposited successively on the insulating layer

  102 an insulating layer and a sacrificial polycrystalline silicon layer

  sky. Then we perform a classic photolithography process

  and etching, to remove selected parts of the iso- layer

  lante and the sacrificial layer. The remaining part of the iso- layer

  lante is indicated by the reference 104, and the remaining part of the sacrificial polycrystalline silicon layer is indicated by the reference 106, in FIG. 6. The insulating layer 104 can be a layer of silicon nitride having a thickness which is for example approximately 100 nm, and the sacrificial polycrystalline silicon layer 106 is deposited to a thickness which is for example approximately 100 nm. The insulating layer 104 and the sacrificial polycrystalline silicon layer 106 form in

  combination of a stacked structure (104, 106) having inside a

  vity 108. The cavity 108 is practically vertically aligned with the

drain region 16.

  Referring next to FIG. 6B, it is noted that elements

  spacers 110 silicon dioxide are then formed on the pa-

  lateral kings of the stacked structure (104, 106). In this embodiment

  sation the spacers 110 silicon dioxide are formed by first depositing a layer of silicon dioxide to a thickness which is for example about 100 nm, and then reducing the thickness of the layer by an attack operation. An insulating layer 112, for example made of silicon nitride, is then deposited by CVD, to a thickness which is for example around 200 nm. The insulating layer 112 practically fills the cavity 108. Chemo-mechanical polishing is then carried out on the upper surface to remove by polishing part of the insulating layer 112, at least until

  the upper surface of the stacked structure (104, 106) is exposed.

  Referring next to FIG. 6C, it is noted that by using, as an attack mask, both the stacked structure (104, 106) and the insulating layer 112, an attack operation is carried out to remove

  spacers 110 silicon dioxide. After removal

  Completely complete with the silicon dioxide spacers 110, the etching process continues, still using both the stacked structure (104, 106) and the insulating layer 112 as an etching mask, to remove by attacking the parts of the insulating layer 102 which

  are located directly below the positions at which the elements

  110 silicon dioxide spacers were originally found.

  The attack is commanded to reach a predeter depth-

  mined to form cavities 114 in the insulating layer 102. It should be noted that the depth of the cavities 114 can be arbitrarily adjusted,

  but that the bottom of the cavities 114 must be at a certain distance above

  above the upper surface of the polycrystalline silicon layer

  100. Then, using the silica layer as an attack mask

  sacrificial polycrystalline cium 106, an etching operation is carried out to remove the insulating layer 112. Next, on the stacked structure (104, 106) and on the insulating layer 102, a layer of polycrystalline silicon, up to a thickness which is example 100 nm, this layer practically filling the cavities 114 and 108. We can make

  diffuse for example arsenic ions in the layer of poly-

  crystalline, to increase its conductivity. Then we polish

  chemo-mechanical wise of the polycrystalline silicon layer, at least

  until the upper surface of the insulating layer 104 is exposed.

  The remaining part of the polycrystalline silicon layer is indicated by the reference 116 in FIG. 6C. By this process, the silicon layer

  polycrystalline sacrificial 106 has been completely removed.

  Referring next to FIG. 6D, it is noted that by using

  title of protective mask against attack both the layer of sili-

  polycrystalline cium 116 and the insulating layer 102, a wet etching operation is now applied to the wafer to remove the insulating layer 104. The complete stacked structure (104, 106) is thus

  removed by this process. We then use the CVD process to

  successively applying an insulating layer 118, a polycrystalline silicon layer 120 and an insulating layer 122. The insulating layer 118 can be formed for example by silicon dioxide, to a thickness which is for example around 200 nm, and similarly the

  insulating layer 122 can be formed for example by silicon dioxide

  cium, but to a thickness which is only, for example, about

  ron 100 nm. We can diffuse for example arsenic ions in the

  polycrystalline silicon layer 120 to increase its conductivity. In-

  following, using a classic photolithography and atta-

  that, we form a hole 124 in a selected part of the slice which

  is practically aligned with the drain region 16, making progress

  successively attack through the insulating layer 122, the layer

  polycrystalline silicon 120, the insulating layer 118, the silicon layer

  polycrystalline cium 116 and the insulating layer 102, until the super-

  upper face of the polycrystalline silicon layer 100 is exposed.

  Referring next to FIG. 6E, it is noted that a layer of polycrystalline silicon 126 having the shape of a solid pillar is formed in the hole 124, for example by epitaxy or by a process of deposition and reduction of thickness per attack. We then perform on

  layers of polycrystalline silicon 120 and 100 a new classic process

  photolithography and attack sic, to reduce their dimensions

  horizontal and thus define a storage electrode for the conden-

  DRAM cell data storage server, having

  120A and 116 branch-shaped polycrystalline silicon

  polycrystalline silicon layer in the form of a lower trunk 100A. In-

  Next, using the attack protective layer 22 as the final attack point, a wet attack operation is carried out to completely remove the insulating layers of silicon dioxide.

  112, 118, 102 and 96, which are bare. This completes the manufacture of the elect

  storage trode for the data storage capacitor of the

DRAM cell.

  As shown in FIG. 6E, this storage electrode comprises the lower trunk-shaped polycrystalline silicon layer A, which has a practically T-shaped cross section, an upper trunk-shaped polycrystalline silicon layer 126, which extends to starting from the lower trunk-shaped polycrystalline silicon layer 100A, and two branch-shaped polycrystalline silicon layers A and 116, among which the branch-shaped polycrystalline silicon layer 116 comprises two offspring 116A and 116B, on the other hand, which practically each have an L-shaped cross section,

  and the 120A branch-shaped polycrystalline silicon layer

  also takes two offspring 120A1 and 120A2 on either side of it, but each of them being practically rectangular. The root 100B (lower end) of the lower trunk-shaped polycrystalline silicon layer 100A is electrically connected to the drain region

  16 of the DRAM cell transfer transistor, and the silicon layer

  upper trunk-shaped polycrystalline cium 126 extends upward from the top of the polycrystalline silicon layer

  lower trunk 100A. Each of the two layers of polycrystalline silicon

  branch-shaped flax (116A and 116B) and 120A share laterally,

  i.e. horizontally and substantially perpendicular to the upper trunk-shaped polycrystalline silicon layer 126. The branch-shaped polycrystalline silicon layer 120A has

  two horizontal rectilinear segments 120A1 and 120A2, extending horizontally

  horizontally on each side, and the branch-shaped polycrystalline silicon layer 116 comprises two L-shaped parts (116A, 116B), each of them comprising a first segment (respectively 116A1 and 116B1) extending horizontally from one side and on the other, and a second segment (respectively 116A2 and 116B2) extending towards the

down from the first segment.

  Sixth embodiment In the sixth embodiment, various structures are used for the trunk-shaped and shaped elements.

  branch taken from the first and fifth embodiments.

  FIG. 7 is a section through a storage electrode of the type

  as a tree in accordance with a sixth preferred embodiment of the invention

  tion, in which the tree type capacitor is based on the struc-

  Figure 2F. The elements represented in FIG. 7, the structure and purpose of which are practically identical to those of FIG. 2F

  are designated by the same reference numerals.

  We then use a CVD operation to deposit a

  polycrystalline silicon che 39 and an insulating layer (not shown)

  on the polycrystalline silicon layer 39. The insulating layer on the

  polycrystalline silicon che 39 can consist, for example, of

  silicon, but with a thickness which is only for example approxi-

  ron 100 nm. Arsenic ions can, for example, be diffused in the polycrystalline silicon layer 39, in order to increase its conductivity. A polycrystalline silicon layer 130A and its root B are then formed, using processes similar to those used for

  forming the polycrystalline silicon layer 44A and its root 44B. By con-

  sequent, the trunk-shaped polycrystalline silicon layer 130A

  nters in polycrystalline silicon layers 39 and 38; and its root 44B is electrically connected to the drain region 16 of the transistor

transfer of the DRAM cell.

* According to the preceding descriptions of the embodiments

  preferred by the invention, it will appear to specialists in semiconductor technology that the various structures for the elements in

  trunk shape and branch shape can be used either individually

  dual, either in various combinations and in various numbers, to

  form a tree type capacitor. We must consider that such

  the configurations are within the scope of the invention.

  In addition, although in the previous description of the modes of

  preferred embodiments, the drain of the transfer transistor is based on a region diffused in a silicon substrate, the invention is not limited

  to such a semiconductor structure. It is also possible to use other

  very structures for the drain region, like a drain region of the

  trench type, and these structures are within the scope of the invention.

  In addition, all of the elements in the accompanying drawings are

  schematically, only for illustrative purposes, and therefore not at actual scale. Such illustrated dimensions should therefore not

  in no way be considered limitations of the framework of the

vention.

  Various other modifications can of course be made.

  tees to the method described and shown, without departing from the scope of the invention.

Claims (29)

  1. A method of manufacturing semiconductor memory on a substrate (10) on which a transfer transistor (14, 16, 18) is formed, characterized in that it comprises the following steps: (a) forming a first layer insulator (20) on the transfer transistor; (b) forming an attack protection layer (22) on the first insulating layer; (c) a second insulating layer (24) is formed on the layer of   protection against attack; (d) a structure of stacked layers is formed.   lées comprising inside it a recessed portion (30) disposed at-   above a source / drain region (16) of the transistor, and exposing part of the second insulating layer; (e) forming a third insulating layer (32) at the periphery of the recessed portion; (f) forming a fourth insulating layer (34) so as to fill the recessed portion; (g) removing the third insulating layer (32) and the fourth insulating layer (34) from the recessed portion, and removing part of the second insulating layer (24) located directly below the third insulating layer (32), to form a cavity (36), so that the cavity does not expose the protective layer against attack (22); (h) forming a first conductive layer (38) so as to fill the recessed portion and the cavity; (i) removing the structure of stacked layers (26,   29); (j) a fifth insulating layer (40) is formed above the se-   this insulating layer and the first conductive layer; (k) a second conductive layer (44) is formed on the fifth insulating layer,   so that the second conductive layer penetrates through the cin   fifth insulating layer, the first conductive layer, the second layer   insulating che, the protective layer against attack and the first layer   insulating, and either in electrical contact with the source / drain region   (16); (1) part of the second conductive layer is removed to form   a conductive layer in the form of a trunk (44A), the first conductive layer forming, in section, a conductive layer in the form of a branch (38), and the conductive layers in the form of a trunk and   of branch constituting together a storage electrode of a   storage intensifier; (m) removing the second and fifth insulating layers; (n) forming a dielectric layer (46) on exposed surfaces of at least the first and second conductive layers; and (o) on   forms a third conductive layer (48) on a surface of the layer   dielectric, to form an opposite electrode.   2. Method according to claim 1, characterized in that   step (d) comprises: the formation of a first film on the   first insulating layer (24) and then the formation of a second film on the first film, the first film being a film   insulating and the second film being a conductive film; and the challenge   nition of a pattern in the first film and the second film, to form the structure of stacked layers (26, 28) and the recessed part (30) in the latter.   3. Method according to claim 1, characterized in that it further comprises: the formation of a sixth insulating layer on the first conductive layer (38) after step (i); and forming a fourth conductive layer on the sixth insulating layer; and in that: step (k) further comprises forming the second conductive layer (44) so that it penetrates through the fourth conductive layer and the sixth insulating layer; step (I) further comprises forming a pattern in the fourth conductive layer so as to constitute a part of the conductive layer in the form of a branch;   step (m) further comprises removing the sixth iso- layer   lante; and step (n) further comprises forming the dielectric layer   stick (46) on a bare surface of the fourth conductive layer.   4. Method according to claim 3, characterized in that the   fourth conductive layer has, in section, the form of a base   is watching, and it is connected to the conductive layer in the form of a trunk.   5. Method of manufacturing a semicon memory device   conductors on a substrate (10) on which a transistor is formed   fert (14, 16, 18), characterized in that it comprises the following stages: (a) forming a first insulating layer (20) on the transfer transistor; (b) forming an attack protection layer (22) on the first insulating layer; (c) forming a second insulating layer   (24) on the attack protection layer; (d) we form a pre-   first structure of stacked layers (26, 28) on the second iso-   lante, the first structure of stacked layers with, inside   from it, a first recessed part (30) disposed above a re-   source / drain region (16) of the transistor and exposing part of the second insulating layer; (e) forming a third insulating layer (32) at the periphery of the first recessed portion (30); (f) forming a fourth insulating layer (34) to fill the recessed portion; (g) removing the third insulating layer and the fourth insulating layer from the first recessed portion (30), and removing part of the second   insulating layer located directly below the third layer   insulating che, to form a first cavity (36), the first cavity not exposing the protective layer against attack (22); (h) forming a first conductive layer (38) to fill the first recessed portion and the first cavity; (i) removing the first structure of stacked layers (26, 28); (j) forming a sixth insulating layer (40); (k) forming a second structure of stacked layers (50, 52) on the sixth insulating layer, the second structure of stacked layers   having, inside it, a second recessed part (54) arranged above   above the source / drain region (16) and exposing a portion of the sixth insulating layer; (I) forming a seventh insulating layer (56)   at the periphery of the second recessed portion (54); (m) an oil is formed   third insulating layer (58) so as to fill the second recessed portion; (n) removing the seventh insulating layer, the eighth insulating layer and   a part of the sixth insulating layer lying directly above   below the seventh insulating layer, to form a second cavity   (60), the second cavity not exposing the protective layer   be the attack; (o) a fourth conductive layer (62) is formed so that   lesson in filling the second recessed part (54) and the second cavity (60); (p) removing the second structure from stacked layers (50, 52); (q) we   forms a fifth insulating layer (64) on the fourth iso-   lante and on the fourth conductive layer; (r) a second conductive layer (68) is formed on the fifth insulating layer, the second conductive layer penetrating through the fifth insulating layer, the fourth conductive layer, the sixth insulating layer, the first conductive layer, the second insulating layer, the protective layer   against the attack and the first insulating layer, and being in electrical contact   stick with the source / drain region (16); (s) part of the second conductive layer is removed to form a conductive layer by   trunk shape (68), the first and fourth conductive layers form   mant, in section, of the branch-shaped conductive layers (38, 62) which are practically parallel to each other, each of which being connected to the trunk-shaped conductive layer (68), and the layers trunk-shaped and branch-shaped conductors together constituting a storage electrode of a storage capacitor; (t) removing the second, fifth and sixth insulating layers; (u) we train   a dielectric layer (46) on at least bare surfaces of the   first, second and fourth conductive layers; and (v) we form a   third conductive layer (48) on a surface of the dielectric layer   that to form an opposite electrode.   6. Method according to claim 1 or 5, characterized in that the conductive layer in the form of a trunk (68) has a T-shaped cross section. 7. Method according to claim 1 or 5, characterized in that   the trunk-shaped conductive layer (44C) forms a practical pillar full.   8. The method of claim 1 or 5, wherein each of the branch-shaped conductive layers (38, 62) has a cross section which has at least one L-shaped part. 9. Method according to claim 1 or 5, characterized in that   each of the branch-shaped conductive layers (38, 62) comprises   takes a first segment and a second segment; the first segment is electrically connected to the trunk-shaped conductive layer (44A, 68) and extends therefrom substantially parallel to an upper surface of the substrate (10), and the second segment is connected   electrically to the first segment and extends from it di-   rection of the upper surface of the substrate (10).   10. The method of claim 7, characterized by the use of   tion of a chemo-mechanical polishing technique to remove part of the second conductive layer (68) until the fifth insulating layer is bare.   11. Method according to claim 7, characterized by the use of   tion of an attack technique to remove the part of the second layer   conductive che (68) on the fifth insulating layer.   12. Method of manufacturing a semi-memory device   conductors on a substrate (10) on which a transistor is formed   transfer (14, 16, 18), characterized in that it comprises the following steps:   Vantes: (a) a first insulating layer (20) is formed on the transfer transistor; (b) forming a first conductive layer (72) which penetrates at least through the first insulating layer and which is in electrical contact with a source / drain region (16) of the transfer transistor; (c) forming a second insulating layer (74) on the first conductive layer; (d) forming a stacked layer structure (76, 78) on the second insulating layer, this structure having inside it a recessed portion (80) which bares a portion of the second insulating layer; (e) forming a third insulating layer (82) at the periphery of the recessed portion (80); (f) forming a fourth insulating layer   (84) to fill in the recessed portion; (g) remove the third and fourth   third insulating layer of the recessed part (80), and part of the second insulating layer lying directly below the third insulating layer is removed, to form a cavity (86), the cavity does not   exposing the first conductive layer; (h) we form a se-   conductive layer (88) to fill the recessed part and the cavity   you; (i) removing the structure of stacked layers (76, 78); (j) forming a fifth insulating layer (90) above the second insulating layer and the second conductive layer; (k) we form a third   conductive layer (94) which penetrates at least through the fifth layer   insulating che, the second conductive layer and the second iso-   which is in electrical contact with the first conductive layer.   trice; (I) a pattern is defined in the first conductive layer, the   first and third conductive layers forming a conductive layer   trunk-shaped trice (72A, 94), the second conductive layer forming a branch-shaped conductive layer (88A, 88B1), and the trunk-shaped and branch-shaped conductive layers constituting an electrode for storing a storage capacitor; (m) we remove the   second and fifth insulating layers; (n) a di-   electric (46) on bare surfaces of the first, second and third conductive layers; and (o) a fourth conductive layer (48) is formed on the dielectric layer, to form an opposite electrode of the storage capacitor.   13. The method of claim 12, characterized in that the trunk-shaped conductive layer comprises a lower trunk-shaped part (72A) which is electrically connected to the source / drain region (16), and a shaped part upper trunk (94) which is electrically connected to the lower trunk-shaped part and which   extends substantially in the opposite direction to the substrate.   14. Method according to claim 13, characterized in that the portion in the form of a lower trunk (72A) has a T-shaped cross section. 15. The method of claim 14, characterized in that the upper trunk-shaped part (94) has a cross section in the form of a straight rod, or is produced in the form of a pillar practically full.   16. The method of claim 12, characterized in that step (1) further comprises defining a pattern in the second conductive layer (88) so that the conductive layer in the form of   branch includes a straight segment (88B1) which is electrically connected   trunk to the conductive layer in the shape of a trunk and which extends from   practically parallel to the upper surface of the substrate (10).   17. The method of claim 15, characterized in that step (I) further comprises the use of a polishing technique   chemo-mechanical to remove part of the third layer   conductive (94), until the fifth insulating layer (90) is exposed.   18. The method of claim 15, characterized in that step (I) further comprises the use of an etching technique to remove part of the third conductive layer (94) until   the second conductive layer (88) is exposed.   19. Method according to claim 1, characterized in that   step (d) further comprises the following steps: a pre-   first film on the second insulating layer (24) and then a layer   films on the first film, the first film being an insulating film and the second film being a conductive film; and we define a pattern in the first film and the second film   to form the structure of stacked layers (26, 28) and the portion thereof line (30) therein.   20. Method according to claims 1 and 7, characterized in that   that it further comprises the following stages: a sixth layer is formed   insulating che after step (i); and we form a fifth conductive layer   trice on the sixth insulating layer; and in that step (k) further comprises forming the third conductive layer so that it penetrates through the fifth conductive layer and the sixth insulating layer; and step (I) further comprises defining a pattern in the   fifth conductive layer to form part of the con-   branching ducting; step (m) further comprises removing   ment of the sixth insulating layer; and step (n) includes training   of the dielectric layer (46) on a bare surface of the fifth layer conductive che.   21. The method of claim 20, wherein the fifth   conductive layer has a cross section in the form of a rod   tilinear and it is connected to the conductive layer in the form of a trunk.   22. Method according to claim 12, characterized in that it   further includes the following steps: a layer of pro-   tection against attack on the first insulating layer (20) after the step   (at); and a seventh insulating layer is formed on the protective layer   tion against attack after step (b); and in that, in step (b), the first   the first conductive layer (72) further penetrates through the attack protection layer and the seventh insulating layer; and step (m)   further includes removing the seventh insulating layer.   23. Method of manufacturing a semi-memory device   conductors on a substrate (10) on which a transistor is formed   transfer (14, 16, 18), characterized in that it comprises the following steps:   Vantes: (a) a first insulating layer (20) is formed on the transistor   transfer; (b) a first conductive layer (100) is formed which   at least through the first insulating layer and which is in electrical contact with a source / drain region (16) of the transfer transistor; (c) forming a second insulating layer (102) on the first conductive layer; (d) forming a first structure of stacked layers   (104, 106) on the second insulating layer, this structure having inside   laughing at it a recessed part (108) which bares part of the se-   insulating layer; (e) forming a third insulating layer (110) at the periphery of the recessed portion (108); (f) forming a fourth insulating layer (112) to fill the recessed portion; (g) removing the third and fourth insulating layers from the recessed portion, and removing part of the second insulating layer located directly below the third insulating layer, to form a cavity (114), this cavity does not exposing the first conductive layer; (h) forming a second conductive layer (116) to fill the part with   withdrawal (108) and the cavity (114); (i) the first layer structure is removed   stacked ches (104, 106); (c ') forming a fifth insulating layer (118) on the second conductive layer; (d ') forming a second structure of layers stacked on the fourth insulating layer, this structure having inside it a recessed portion which bares part of the fifth insulating layer; (e ') forming a sixth insulating layer at the periphery of the recessed portion; (f ') forming a seventh insulating layer to fill the second recessed portion; (g ') the sixth and seventh insulating layers are removed from the recessed part, and we   removes part of the second and fifth insulating layers   vant directly below the sixth insulating layer, to form a cavity, this cavity not exposing the first or second conductive layers; (h ') forming a third conductive layer (120) to fill the second recessed portion and the second cavity; (i ') on   removes the second structure from stacked layers; (j) an oil is formed   third insulating layer (122) on the third conductive layer and the fifth   fifth insulating layer; (k) a fourth conductive layer is formed   (126) which penetrates at least through the eighth insulating layer, the third   fifth conductive layer, the fifth insulating layer, the second layer   che conductive and the second insulating layer, and which is in electrical contact with the first conductive layer (100); (I) patterns are defined in the conductive layers, the first and fourth conductive layers forming trunk-shaped conductive layers (100A, 126), the second and third conductive layers forming layers   branch-shaped conductors (116, 120A), and the conductive layers   these in the form of a trunk and in the form of a branch constituting a storage electrode of a storage capacitor; (m) we remove the second,   fifth and eighth insulating layers; (n) a di-   electric (46) on bare surfaces of the first, second, third and fourth conductive layers; and (o) forming a fifth conductive layer (48) on the dielectric layer, to form an electrode   opposite of the storage capacitor.   24. The method of claim 12 or 23, wherein the branch-shaped conductive layer, or at least one of them, has a cross section in L.   25. The method of claim 12 or 23, wherein the se-   this branch-shaped conductive layer, or each of them, comprises a first segment and a second segment, the first segment (116A1, 116B1) being electrically connected to a trunk-shaped conductive layer (126) and extending from substantially parallel to an upper surface of the substrate (10), and the second segment (116A2, 116B2) being electrically connected to the first segment and extending towards the substrate (10).   26. The method of claim 23, characterized in that step (I) comprises defining a pattern in the second and third conductive layers (116, 120), so that each of the branch-shaped conductive layers comprises a straight segment   (120A1, 120A2) which is electrically connected to a conductive layer   trunk-shaped (126) and which extends in a substantially parallel manner   lele to an upper surface of the substrate (10).   27. The method of claim 23, characterized in that it further comprises the following steps: after step (i '), a ninth insulating layer is formed after the removal of the second structure of stacked layers; and forming a sixth conductive layer on the ninth insulating layer; and in that step (k) comprises forming the fourth conductive layer so that it further penetrates through the sixth conductive layer and the ninth insulating layer;   I step (I) further includes the definition of a pattern in the sixth   conductive che so that it forms a shaped conductive layer   additional branch; Step (m) includes removal of the new   5th insulating layer; and step (n) includes forming the layer   dielectric (46) on a bare surface of the sixth conductive layer.   28. The method of claim 27, characterized in that the   sixth conductive layer has a cross-section in the form of a   is watching and it is electrically connected to a conductive layer in trunk shape.   29. The method of claim 12 or 23, characterized in that it further comprises the formation of a protective layer against   the attack on the first insulating layer (20) after step (a).   Method according to claim 23, characterized in that it   further includes: forming a protective layer against   tack on the first insulating layer (20) after step (a); and the training   tion of a ninth insulating layer on the protective layer against attack; and in that, in step (b), the first conductive layer (100) further penetrates through the attack protection layer   and the ninth insulating layer; and step (m) further comprises removing   of the ninth insulating layer.