FR2748871A1 - SYNCHRONIZATION AND CONTROL CIRCUIT FOR A DOWNSTREAM CONVERTER EMPLOYING A SYNCHRONOUS RECTIFIER - Google Patents

Abstract

An isolated downstream switching power converter includes a primary side circuit (20) and a secondary side circuit (30) having an output coil (L), a first MOS transistor coupled in series with the output coil (L ), a second MOS transistor coupled in a bypass relationship with the output coil (L) and a synchronous rectifier control circuit (10) which senses the voltage across the output coil (L) and alternately bias the first and second forward and reverse transistors in response thereto.

Description

SYNCHRONIZATION AND CONTROL CIRCUIT FOR A

  DOWNSTREAM CONVERTER USING A SYNCHRONOUS RECTIFIER

  The present invention relates to a synchronization and control circuit for a converter

  downstream using a synchronous rectifier.

  In known downstream switching supply circuits employing synchronous rectifiers, the diodes on the secondary side are replaced by transistors to obtain a lower voltage drop in the on state. The transistors must be polarized to conduct from the source to the drain (for an N-channel power field effect MOS transistor) when a diode would have been conductive from the anode to the cathode and, conversely, must be ordered to block the voltage from the drain to the source when a diode has

  been blocked from the cathode to the anode.

  In these known synchronous rectification circuits, the gate signals to the transistors must be synchronized as close as possible to the inflection points of the output coil current, which inflection points correspond to the zero crossings of the wave voltage. coil square

  exit. Grid signals can be "auto-

  controlled "(that is to say that the gate signal is linked directly to the circuit) or" controlled synchronized "(that is to say that a synchronization signal is deduced from any point in the circuit and supplied to a gate gate controller

field effect MOS transistor).

  Examples of prior art synchronous rectifiers can be found in US Patents N 4,903,189 to Ngo et al., 5,430,640 to Lee and 5,457,624 to Hastings and in the following articles: "Synchronous Rectifiers Improve Efficiency in Low Output Voltage Forward Converters "from Clemente et al. (pages 347-350) and "The Impact of Low Output Voltage Requirements on Power Converters" by Jitaru, HFPC,

  May 1995 publication (pages 1-10).

  Some prior art synchronous rectifier circuits monitor the control signals on the primary side and transfer these signals to the secondary side of the current converter (i.e., across the isolation limit) to synchronize control synchronous transistors. Unfortunately, expensive, non-optimal and complex circuit elements are required to maintain isolation

  between the primary and secondary parts of the circuit.

  For example, when optoisolators are used to maintain isolation, unwanted delays and unpredictable gain variations introduce

errors in the system.

  Other synchronous rectifier circuits of the prior art use additional transformer windings to transfer synchronization information to the transistors of the

  secondary circuit and still maintain isolation.

  However, these transformers are more expensive and more complex and a problem resetting the

transformer also occurs.

  Therefore, there is a need in the art for a new synchronous rectification circuit which does not require additional optocouplers or transformer windings to transfer synchronization information across the isolation limit between primary and secondary circuits

  in a downstream power converter.

  In order to overcome the drawbacks of synchronous rectification circuits of the prior art, the present

  invention provides "auto-

  "produced by controlling the voltage across the converter output coil and alternately controlling the transistors in response to the transitions of the coil voltage, so that a first transistor is always on when the other

is blocked, and vice versa.

  More specifically, the present invention relates to an isolated downstream switching power converter, comprising: a primary side circuit coupled to a primary winding of an isolation transformer; and a secondary side circuit coupled to a secondary winding of the isolation transformer, the secondary side circuit comprising: an output coil coupled in series with the secondary winding to a first node and coupled to a second node to a capacitor of output at the terminals of which an output voltage is taken; a first MOS transistor coupled in series with the secondary winding and the output coil; a second MOS transistor coupled in bypass from the first node to ground; and a synchronous rectifier control circuit coupled to the first and second MOS transistors, the synchronous rectification circuit detecting the voltage across the output coil and alternately polarizing the first and second transistors by

  direct and reverse in response to it.

  According to other characteristics of the invention: - the peak value of the coil voltage

  detected is limited to the output voltage.

  - a first terminal of a resistor is coupled to the first node, the cathode of a diode is coupled to the second node, the anode of the diode is coupled to the other terminal of the resistor to a third node and the voltage of detected coil is obtained from the

third node.

  the secondary circuit further comprises an auxiliary source of DC voltage, the auxiliary source of DC voltage being taken across a Zener diode, the Zener diode coupled to the first node by a blocking diode and a

  current limiting resistor.

  - the peak value of the detected coil voltage is limited to the auxiliary source

of continuous voltage.

  - a first terminal of a resistor is coupled to the first node, the cathode of a diode is coupled to the auxiliary DC voltage source, the anode of the diode is coupled to the other terminal of the resistor at a third node and the detected coil voltage is obtained from the third

node.

  - the detected voltage is coupled to a non-inverter detection circuit and to a

inverter detection.

  - The non-inverting detection circuit comprises a non-inverting amplifier coupled to a first control circuit; - the first control circuit is coupled to the gate of the first transistor; - the inverter detection circuit comprises an inverter amplifier coupled to a second control circuit; and the second control circuit is coupled to the

gate of the second transistor.

  the non-inverting amplifier comprises a bipolar transistor connected according to an emitter-follower configuration; - The first control circuit includes two bipolar push-pull transistors; - the inverting amplifier comprises a bipolar transistor; and - the second control circuit comprises

  two bipolar push-pull transistors.

  - the non-inverting amplifier comprises a MOS transistor; the first control circuit comprises two push-pull MOS transistors; the inverting amplifier comprises a MOS transistor; and - the second control circuit comprises

two push-pull MOS transistors.

  The other features and advantages of the present invention will become apparent from the

  description which follows of the invention which refers

to the attached drawings.

  In order to illustrate the invention, the forms which are currently preferred are shown in the drawings, it being understood, however, that the invention is not limited to the precise arrangements and the equipment shown. Figure 1 is an embodiment partially in the form of blocks of a rectifier

synchronous according to the invention.

  Figure 2 is an equivalent circuit of a secondary circuit of Figure 1 during a first mode of operation. Figure 3 is an equivalent circuit of the secondary circuit of Figure 1 in a second mode of operation. Figure 4 illustrates waveforms at various points during operation in the circuit of the

figure 1.

  Figure 5 shows the circuit of Figure 1 with a comparator, shown on the block diagram of the

  Figure 1, shown in detail in Figure 5.

  FIG. 6 shows another embodiment of the comparator of FIG. 5. With reference now to the drawings in which identical numbers indicate similar elements, a synchronous rectifier 10 according to the invention which comprises a primary circuit 20 and a secondary circuit 30 is shown in FIG. 1. The primary circuit 20 comprises a voltage source Vin, a primary winding 11 of a transformer 12, a switch Sp, a reset winding 13 for resetting the core of the transformer 12 and a reset diode Dr The switch Sp is shown, for simplicity, as a unipolar switch; however, in reality, the switch may be a conventional MOS switch, such as a power field effect MOS transistor or a transistor

bipolar with insulated grid (IGBT).

  The secondary circuit 30 comprises a secondary winding 14, an output coil L and an output capacitor C, a first transistor

  power Si and a second power transistor S2.

  Each power transistor Si, S2 includes a

antiparallel diode across its terminals.

  A comparator 40 is connected to the terminals of the output coil L to detect the voltage across its terminals, VL, that is to say to detect the potential difference between the voltages VA and Vout. The comparator has an output connected to the gate of transistor S1 and an inverted output connected to the gate of

transistor S2.

  When the voltage VL across the coil L is positive, the transistor Si is forward biased and the transistor S2 is reverse biased. Conversely, when the voltage VL is negative, the transistor S2 is forward biased and the transistor S1 is biased

in reverse.

  Thus, the rectifier 10 has two operating modes. In the first mode, Mode 1, the transistor Si is on and conducts the current and the transistor S2 is blocked and blocks the current. In the second mode, Mode 2, the transistor S1 is blocked and blocks the current and the transistor S2 is on and

conducts the current.

  We can better understand Mode 1 by referring to the equivalent circuit of FIG. 2 in which Vs represents the voltage across the terminals of the secondary winding 14, the transistor S1 is represented by an ideal diode S1 and the output voltage is represented by an output voltage source Vo. The relationship between the various voltages is as follows: Vs = VL + VO and VL = VS - Vo. Since Vs is greater than

Vo, VL is therefore positive.

  Also, IL in Mode 1 follows a di

  rising or increasing. Therefore, - is positive.

  dd Since VL = L -, this analysis shows dt

  also that VL is positive in Mode 1.

  Mode 2, in which the transistor S1 blocks the current and the transistor S2 conducts the current, can be represented by the equivalent circuit shown in FIG. 3, where the transistor S2 is represented by the ideal diode S2. As in the equivalent circuit for Mode 1, Vs = VL + Vout and, therefore, VL = VS - Vout. Here, VA is zero volts, which is less than Vout and, therefore, VL is negative. Also, in Mode 2, it decreases or follows a downward slope. Therefore, -d is negative. Since VL = Ld -, this analysis di dt

  also indicates that VL is negative in Mode 2.

  The waveforms appearing at different points in the circuit of Figure 1 during operation are shown in Figure 4. With reference now to Figure 5, a detailed embodiment of the comparator 40 of Figure 1 is shown, which includes a transistor comparator

  non-inverter Q1 and control transistors (push-

  pull) Q3 and Q4 associated and a comparator with inverting transistor Q2 and control transistors (push-pull) Q5 and Q6 associated. The transistors Q1 and Q2 react to the voltage Vsense relative to the mass, o Vsense

  varies as a function of VL and VA.

  In Mode 1, VA is greater than Vout (i.e.

  say that VA = Wine. (NS / Np)) and, therefore, Vsense is a positive voltage roughly equal to Vout + VfD1, O VfD1 is the direct voltage drop across the diode D1. This results in the forward bias of the transistor Q1 and in the reverse bias of the transistor Q2. The output from the transmitter of Q1 is therefore a positive voltage which causes the

  the passing state of Q3 and the blocking state of Q4.

  Consequently, the voltage at the gate of S1 amounts to approximately Vzz and S1 becomes conducting. Conversely, the output from the collector of Q2 is approximately zero volts, which causes Q6 to go on and evacuate the charge from the grid of S2 and puts it at

blocked state.

  In Mode 2, VA is less than Vout (i.e.

  say that VA z 0 volt) and, therefore, Vsense = VA t 0 volt.

  This results in the reverse polarization of the

  transistor Q1 and by the forward bias of Q2.

  The output from the collector of Q2 is therefore a positive voltage which causes the Q5 to go on and Q6 to go into the blocked state. Consequently, the voltage at the gate of S2 amounts to approximately Vzz and S2 becomes conducting. Conversely, the output from the transmitter of Q1 is about zero volts, which causes Q4 to go on and evacuates the

  charge the Si grid and put it in the blocked state.

  So, the control of S1 and S2 is a function

  of the voltage VL at the terminals of the coil L, that is to say

  say that, when VL is positive, S1 is polarized in direct (the grid voltage of S1 is positive compared to that of its source) and S2 is polarized in reverse (the grid voltage of S2 is low compared to that of its source). When VL is negative, on the other hand, Si is reverse biased and S2 is

polarized live.

  Advantageously, the gates of the transistors are "self-controlled" by detecting the states in the secondary circuit 30, namely the coil voltage, VL. Thus, there is no need for slow, unpredictable and expensive opto-isolators or additional windings in transformer 12. In addition, the efficient use of discrete components avoids the need for integrated circuit type comparators

expensive.

  Note that the diode D1 advantageously limits the

  voltage at Vsense at a diode voltage drop at-

  above Vout, which also limits the voltage entered towards Q1 and Q2. Thus, the circuit is protected from reverse oscillation at the peak values of VA because these peak values are not fed back into the circuit of the present invention. In addition, by limiting the maximum excursions of Vsense to approximately Vout, the transistors are in the off state when Vout is under voltage (that is to say when Vout is less than 1) thus ensuring, improved starting characteristics of the converter. It is noted that Dl allows an additional diode voltage drop from the control voltage to control Q1-Q6 (that is to say that Vsense = Vout + VfDl). However, if Vout is designed to be a very low output which would not allow a correct control voltage to Q1-Q6, then the cathode of diode D1 can be connected to Vzz. Thus, a higher voltage would be obtained to control Q1-Q6 (that is to say that Vsense =

VZz + VfD).

  Capacitors C1 and C2 are used to introduce respective delay times into the circuits of Q1 and Q2 in order to provide dead time

necessary.

  The reason for the dead time is as follows: the gate signals of the synchronous rectifier must be synchronized as close as possible to the transitions.

  of VL (i.e., zero crossing points).

  If the respective grids are ordered too long (i.e., ordered early, cease to be ordered late), an overshoot or a current swing due to cross conduction between Si and S2 may occur. If the respective gates are ordered too late or cease to be ordered too soon, the antiparallel diode of the MOS power field effect transistors will conduct, giving higher conduction losses while it is driving and reverse overlap effects when 'she is blocked

  while the voltage switches to the opposite polarity.

  Thus, to avoid cross conduction, when VA is greater than Vout, the transistor S1 becomes on after a dead time and the transistor S2 becomes blocked. Conversely, when VA is less than Vout, the transistor S1 becomes blocked and the transistor S2 becomes conducting after a dead time. Advantageously, the duration of the dead time can be predetermined to allow configurations comprising different types of MOS transistors with power field effect. The resistor R8, the capacitor C3 and the diode D2 serve as a source of control power or as

  auxiliary source of continuous power.

  Alternatively, Vout can be used as Vzz if Vout is high enough to provide sufficient control voltage to the grids of S1 and S2 to reduce their direct resistance (i.e., for

  totally improve the S transistors! and S2).

  R8 serves as a limiting resistor for charging C3. C3 supplies current to the circuit and maintains Vzz

  according to the avalanche voltage VD2 of the Zener diode D2.

  If VA is greater than VD2, then Vzz is roughly

  equal to the avalanche voltage of the Zener diode D2.

  On the other hand, if VA is less than VD2, then, Vzz

  is roughly equal to the peak value of VA.

  Advantageously, the supply of Vzz makes it possible to control the power field effect MOS transistors with a voltage high enough to totally improve the devices and lower their direct resistances. This decreases the need for additional winding on the transformer or

additional food.

  FIG. 6 shows another embodiment 40 ′ of the comparator 40 of FIG. 5. In the embodiment of FIG. 6, field effect transistors Q7-Q11 are used in place of the bipolar transistors Q1-Q6 of FIG. 5. The operation of this embodiment is essentially identical to that of the embodiment of FIG. 5. More specifically, when VA is greater than Vout, a high voltage is entered at the gate of S1 and a low voltage is entry to the grid of S2. Conversely, when VA is less than Vout, a low voltage is applied to the grid of S1 and a high voltage

is applied to the grid of S2.

  Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and many other uses

  will become obvious to those skilled in the art.

  It is therefore preferable that the present invention does not

  is not limited by this specific presentation.

Claims (10)

  1. An isolated downstream switching power converter, comprising: a primary side circuit (20) coupled to a primary winding (11) of an isolation transformer (12); and a secondary side circuit (30) coupled to a secondary winding (14) of the isolation transformer (12), the secondary side circuit (30) comprising: an output coil (L) coupled in series with the winding secondary (14) to a first node and coupled to a second node to an output capacitor (C) at the terminals of which an output voltage (VO) is taken; a first MOS transistor coupled in series with the secondary winding (14) and the output coil (L); a second MOS transistor coupled in bypass from the first node to ground; and a synchronous rectifier control circuit (10) coupled to the first and second MOS transistors, the synchronous rectification circuit detecting the voltage across the output coil (L) and alternately polarizing the first and second transistors by   direct and reverse in response to it.   2. Isolated downstream switching power converter according to claim 1, characterized in that the peak value of the coil voltage (VL)   detected is limited to the output voltage (VO) -   3. Isolated downstream switching power converter according to claim 2, characterized in that a first terminal of a resistor is coupled to the first node, the cathode of a diode is coupled to the second node, the anode of the diode is coupled to the other terminal of the resistance at a third node and the detected coil voltage (VL) is obtained from the third node. 4. Isolated downstream switching power converter according to claim 1, characterized in that the secondary circuit (30) further comprises an auxiliary DC voltage source, the auxiliary DC voltage source being taken across a Zener diode (D2), the Zener diode (D2) coupled to the first node by a blocking diode and a   current limiting resistor (R8).   5. Isolated downstream switching power converter according to claim 4, characterized in that the peak value of the detected coil voltage (VL) is limited to the auxiliary DC voltage source. 6. Isolated downstream switching power converter according to claim 5, characterized in that a first terminal of a resistor is coupled to the first node, the cathode of a diode is coupled to the auxiliary DC voltage source, the diode anode is coupled to the other terminal of the resistor at a third node and the coil voltage (VL) detected   is obtained from the third node.   7. Isolated downstream switching power converter according to claim 1, characterized in that the detected voltage is coupled to a non-inverter detection circuit and to an inverter detection circuit. 8. Isolated downstream switching power converter according to claim 7, characterized in that the non-inverting detection circuit comprises a non-inverting amplifier coupled to a first control circuit; the first control circuit is coupled to the gate of the first transistor; the inverter detection circuit comprises an inverter amplifier coupled to a second control circuit; and the second control circuit is coupled to the gate of the second transistor.   9. Isolated downstream switching power converter according to claim 8, characterized in that the non-inverting amplifier comprises a bipolar transistor connected in an emitter-follower configuration; the first control circuit comprises two bipolar push-pull transistors; the inverting amplifier comprises a bipolar transistor; and the second control circuit includes two bipolar push-pull transistors.   10. Isolated downstream switching power converter according to claim 8, characterized in that the non-inverting amplifier comprises a MOS transistor; the first control circuit comprises two push-pull MOS transistors; the inverting amplifier comprises a MOS transistor; and the second control circuit includes two push-pull MOS transistors.