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FR2733614B1 - Systeme multiprocesseur en groupes et procede pour controler une phase d'horloge de groupes - Google Patents

Systeme multiprocesseur en groupes et procede pour controler une phase d'horloge de groupes

Info

Publication number
FR2733614B1
FR2733614B1 FR9605305A FR9605305A FR2733614B1 FR 2733614 B1 FR2733614 B1 FR 2733614B1 FR 9605305 A FR9605305 A FR 9605305A FR 9605305 A FR9605305 A FR 9605305A FR 2733614 B1 FR2733614 B1 FR 2733614B1
Authority
FR
France
Prior art keywords
group
controlling
clock phase
multiprocessor system
group clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9605305A
Other languages
English (en)
Other versions
FR2733614A1 (fr
Inventor
Koichi Horikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2733614A1 publication Critical patent/FR2733614A1/fr
Application granted granted Critical
Publication of FR2733614B1 publication Critical patent/FR2733614B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR9605305A 1995-04-26 1996-04-26 Systeme multiprocesseur en groupes et procede pour controler une phase d'horloge de groupes Expired - Fee Related FR2733614B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7102532A JP2786124B2 (ja) 1995-04-26 1995-04-26 共有メモリ型マルチプロセッサシステム

Publications (2)

Publication Number Publication Date
FR2733614A1 FR2733614A1 (fr) 1996-10-31
FR2733614B1 true FR2733614B1 (fr) 1998-06-12

Family

ID=14329912

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9605305A Expired - Fee Related FR2733614B1 (fr) 1995-04-26 1996-04-26 Systeme multiprocesseur en groupes et procede pour controler une phase d'horloge de groupes

Country Status (2)

Country Link
JP (1) JP2786124B2 (fr)
FR (1) FR2733614B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3288261B2 (ja) 1997-06-19 2002-06-04 甲府日本電気株式会社 キャッシュシステム
US6269428B1 (en) * 1999-02-26 2001-07-31 International Business Machines Corporation Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system
JP2001167077A (ja) 1999-12-09 2001-06-22 Nec Kofu Ltd ネットワークシステムにおけるデータアクセス方法、ネットワークシステムおよび記録媒体
US6799217B2 (en) * 2001-06-04 2004-09-28 Fujitsu Limited Shared memory multiprocessor expansion port for multi-node systems
JP6428521B2 (ja) * 2015-07-23 2018-11-28 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05100952A (ja) * 1991-10-07 1993-04-23 Fuji Xerox Co Ltd データ処理装置
EP0553743A1 (fr) * 1992-01-31 1993-08-04 Motorola, Inc. Contrôleur d'antémémoire
US5394555A (en) * 1992-12-23 1995-02-28 Bull Hn Information Systems Inc. Multi-node cluster computer system incorporating an external coherency unit at each node to insure integrity of information stored in a shared, distributed memory

Also Published As

Publication number Publication date
FR2733614A1 (fr) 1996-10-31
JPH08297642A (ja) 1996-11-12
JP2786124B2 (ja) 1998-08-13

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20101230