FR2719430A1 - Error detection circuit. - Google Patents

Abstract

The error detection circuit according to the invention comprises sampling means (25, 30, 35) for sampling segments of a data bit, counting means (40, 45) for counting the number segments which have logic state 0 and logic state 1, as well as comparison means (50, 52, 55, 57, 60, 65) serving to compare with a predetermined value (60) the number of segments which have logic state 0 and the number of segments which have logic state 1, where, if the number of segments having state 1 exceeds the predetermined value, then a data signal having logic value 1 is produced, and , if the number of segments having the state 0 exceeds the predetermined value, then a data signal of logic level 0 is produced, while, if these two numbers exceed the predetermined value, then an error signal is produced.

Description

The present invention relates to an error detection circuit and, more

  particularly, but not exclusively, an error detection circuit in

bit segments.

  The data bits of a digital data signal are created so as to be in one of two well-defined states, namely a logic state 1 (high state) or a logic state 0 (low state). However, circuits and data paths subject to electrical noise have effects such that the states of the data bits of a data signal become less well defined as they are propagated through circuits and journeys. Data errors often occur when bits of data become defective in this way. Bit error detection circuits are known which can check the validity of incoming bits and identify the existence of errors 1 when a defined validity threshold has been exceeded. However, in such circuits, the problem arises that the defined threshold used to detect an error is typically fixed, so that error detection is often excessively sensitive, which leads to

  unnecessary return of valid data bits which slows data transfer.

  In addition, error detection may not be sensitive enough, which

  authorizes the reception of erroneous bits of data which have not been detected.

  The invention aims to provide an error detection circuit in which

  the above-mentioned drawbacks are mitigated.

  According to the invention, an error detection circuit is proposed which comprises: an input terminal connected so as to receive a data signal whose level varies between upper and lower limits; sampling means coupled to the input terminal and serving to sample the data signal over a predetermined time in order to produce a plurality of samples of the data signal, each sample having a first or a second signal level depending that the level of the data signal, at the time of its sampling, was closer to the upper limit or closer to the lower limit, respectively; counting means coupled to the sampling means and for counting the number of samples which have the first signal level and the number of samples which have the second signal level; comparison means coupled so as to receive a predetermined value and connected to the counting means in order to compare with the predetermined value the number of samples which have the first signal level and the number of samples which have the second signal level and to produce a first output signal if the number of samples having the first signal level exceeds the predetermined value and to produce an error signal if the number of samples which have the first signal level and the number of 'samples that have the second signal level both exceed the predetermined value. Preferably, the comparison means are designed to produce a second output signal if the number of samples having the first signal level does not exceed the predetermined value. Alternatively, the comparison means may preferably be designed to produce a second output signal if the number of samples having the

  second signal level exceeds the predetermined value.

  The sampling means preferably comprise logic means coupled so as to detect the level of the data signal, these logic means comprising a first AND gate, coupled so as to receive a clock signal and the data signal, and a second AND gate, coupled to receive the clock signal and connected to a NO gate to receive the data signal in reverse form; o the first AND gate produces said first signal level when the data signal is closer to one of the upper and lower limits and the second gate and produces said second signal level when said data signal level is closer to the other of the limits

upper and lower.

  The counting means preferably comprises a first counter designed to count the number of samples having the first signal level and a second counter designed to count the number of samples

  having the second signal level.

  Preferably, the comparison means comprise a first and a second comparator, a first and a second locking circuit, as well as a control means, the control means being intended to produce the predetermined number, o, if the number d samples having the first signal level exceeds the predetermined number, then the first comparator positions the first latch circuit and, if the number of samples having the second output level exceeds the predetermined number, then the second comparator

  positions the second locking circuit.

  In a preferred embodiment, the predetermined duration corresponds to the duration of a data bit. Preferably, the counting means

  and the comparison means are repositioned at the start of each predefined duration

  finished. In this way, by varying the predetermined number, there is an interval of validity threshold values by means of which the validity of the incoming data bits can be checked.

  The following description, intended to illustrate the invention, aims

  to give a better understanding of its characteristics and advantages; it is based on the appended drawings, among which: FIG. 1 represents a preferred embodiment of an error detection circuit according to the invention; Figure 2 is a profile view of a typical data bit on which the error detection circuit of Figure 1 operates; and FIG. 3 is a truth table which belongs to the detection circuit

Figure 1 error.

  Reference is made to FIG. 1, which shows an error detection circuit 10. A data input terminal 15 of circuit 10 is connected so as to receive a digital data signal from a data source. serial, for example a serial bus or data access. A clock signal input terminal 20 is coupled to receive a clock signal. The clock signal is synchronized with the digital data signal to divide

  a single bit of the data signal in a number of segments.

  A first AND gate 25 has a first input coupled to the data input terminal 15, a second input coupled to the clock input terminal 20, and an output. Similarly, a second AND gate 35 has a first input coupled to the data input terminal 15 via a NON gate 30,

  a second line coupled to the clock input terminal 20, and an output.

  In this way, a sampled segment of the digital data signal is obtained each time the clock signal occurs. The sampled segment will have a value which is logical level 1 (high level) or logical level 0 (low level). If the value of the sampled segment is high (logic level 1), then the two input signals of the first AND gate 25 will be at the high level, so that their output signal will be at the high level. Conversely, if the sampled segment is at the low level (logic level 0), then the two input signals of the second AND gate 35 will be at the high level, so that their output signal will be at the high level. So the level of the data bit is

  sampled several times during the duration of the data bit.

  A first counter 40 and a second counter 45 are coupled to the respective outputs of the first and second AND gates 25 and 35. The first counter 40 is therefore intended to count the number of sampled segments which are at the high level and the second counter is intended to count the number of sampled segments that are at the low level. A control input terminal 60 is coupled to receive a control signal from a user device or switch, this

  control signal to be described more fully below.

  A first comparator 50 is coupled to receive the control signal from the control input terminal 60 and is further coupled to the first counter 40 and the first latch circuit 52. The signal

  command indicates a value which corresponds to a number of sampled segments

  given. If the first counter 40 counts up to the value indicated by the control signal, then the first comparator 50 positions the first locking circuit 52. Likewise, a second comparator 55 is coupled so as to receive the control signal coming from the control input terminal 60 and is further connected to the second counter 45 and to the second latch circuit 57. Likewise, if the second counter 45 counts up to the value indicated by the control signal, then the second comparator 55 positions

  the second locking circuit 57.

  The first latch circuit 52 and the second latch circuit 57 have outputs which are switched to the conductive state when the latch circuits are positioned. A data output terminal 70 is connected to receive the output signal from the first circuit

lock 52.

  A third AND gate 65 is coupled by an input to the output of the first latch circuit 52, by another input to the output of the second latch circuit 57, and by its output to an error signal output terminal 75. In this way, if the two locking circuits 52 and 57 are positioned, the AND gate presents a high level output signal which produces a

  signal on the error signal output terminal 70.

  We now refer to FIG. 2, which is a graph of the voltage V as a function of time T for a typical data bit. Ideally, the data bits present on the data path which is connected to the data input terminal 15 are in a well-defined state, either at the high level (VH) or at the low level (VL). However, in reality, due to noise on the data path and possible other factors, the data bits have a less ideal profile, as can be seen for the data bit shown in Figure 2. If l 'we use a sample taken in the middle of the data bit to determine the state, the result will be a high level. However, examination of the profile shows that the data bit, even if it is not markedly in either of the two states

  well defined, is more likely to represent a low state.

  While the circuit is running, the data bit of FIG. 2 is received on the data input terminal 15. The clock signal received on the clock input terminal 20 has a first clock pulse which identifies a first segment 80 of the data bit. Then, the second, third, fourth and fifth clock pulses respectively identify the other segments 85,

, 95 and 100.

  The clock signal is produced by an internal prior divider from the internal clock signal of a device to which the error detection circuit

10 is coupled.

  The input terminal 60 receives the control signal continuously during the operation of the error detection circuit 10. Thus, the comparators 50 and 55 receive a threshold value. If the number of samples counted by the counter 40 exceeds this threshold value, then the first comparator 50 positions the first locking circuit 52. Similarly, if the number of samples counted by the counter 45 exceeds the threshold value, then the second comparator 55 positions the second locking circuit 57. In this way, the tolerance of the error detection circuit 10 is variable, because it

  depends on the threshold value contained in the control signal.

  In the case of the first clock pulse, the value of the data signal relating to the first segment 80 is less than a median threshold value and therefore constitutes a low state. The median threshold value 105 is determined by the internal threshold of AND gates 25 and 35. The arrangement of AND gates 25 and 35 and NON gate 30 is such that AND gates 25 and 35 operate in a mutually exclusive manner. If the first input of the first AND gate 25 is at the low level, then its output will also be at the low level. Conversely, the first input of the second AND gate 35 will be at the high level, due to the presence of the NON gate 30, so that its output will also be at the high level. By

  Consequently, the second counter 45 will be incremented by one.

  The sequence presented above is repeated for the following segments of the data bit which are produced by the clock pulses, the first counter 40 incrementing if the value of the segment is high, and the second counter incrementing if the segment value is low. Therefore, for the data bit in Figure 2, the first counter increments for the third segment 90, and the second counter increments for all the other segments, 80, 85, 95 and 100. A at the end of the data bit sampling period, the first counter has the value 1 and the second counter has the value 4, indicating the respective numbers of sampled segments which are at the level

high and low.

  If the value imposed by the control signal is 2, then only the second locking circuit 57 will be positioned. Consequently, the data output terminal 70 will have a low level signal (logic level 0), the output signal of the third AND gate 65 will be low, and the error signal will not be produced on the output terminal. error signal 75. Therefore, the result will be a

logic level 0, without error.

  If the value fixed by the control signal is 1, then the first locking circuit 52 and the second locking circuit 57 will both be positioned. Consequently, the data output terminal 70 will have a high level signal (logic level 1), the output signal of the third AND gate 65 will be

  high, and an error signal will be produced on the error signal output terminal 75.

  We will therefore have, as a result, an error.

  Thus, for the same data bit, as shown in FIG. 2, an error can be detected or discarded, depending on the value of the control signal. At the end of the data bit sampling period, the first and second counters 40 and 45 and the first and second latch circuits

  52 and 57 are repositioned, to prepare the processing of the next data bit.

  By way of example, with reference to FIG. 3, one can see a truth table presenting results for a data bit with five segments, for which the control signal has the value 2. All the possibilities of values of the segments are shown. Line 5 in Figure 3 represents the data bit

  used as an example in Figure 2.

  There are four segments that have the low value and only one

  segment that has the high value.

  The error detection circuit 10 is therefore designed to operate

  with a variable error tolerance, as given by the control signal.

  In addition, it operates independently of the number of sampled segments.

  It will be understood that other embodiments than the one presented above can be implemented, for example by using a register with

  offset in place of the first and second counters 40 and 45.

  In addition, it would be possible to use a discrete logic implementation for the truth table of FIG. 3, instead of the first and second comparators and 55, the first and second latch circuits 52 and 57, and the

third gate AND 55.

  In addition, it would be possible, through the use of inverters or similar means, to place the first and second locking circuits 52 and 57 and the AND gate 65 so that the second locking circuit 57 provides

  the output signal to the data output terminal 70.

  Of course, those skilled in the art will be able to imagine, from the

  circuit whose description has just been given by way of illustration only and

  in no way limiting, various variants and modifications not departing from the scope of the invention.

Claims (10)

  1. An error detection circuit (10), characterized in that it comprises: an input terminal (15) coupled so as to receive a data signal whose level varies between upper and lower limits; sampling means (25, 35), coupled to the input terminal, which serve to sample the data signal over a predetermined period to produce a plurality of samples of the data signal, each sample having a first or indeed a second signal level depending on whether the level of the data signal, when sampled, is respectively closer to the upper limit or closer to the lower limit;   counting means (40, 45) coupled to the exchange means   tillonnage and used to count the number of samples which have the first signal level and the number of samples which have the second signal level; comparison means (50, 52, 55, 57, 60, 65) coupled so as to receive a predetermined value (60) and connected to the counting means in order to compare with the predetermined value the number of samples having the first level signal and the number of samples having the second signal level and in order to produce a first output signal if the number of samples having the first signal level exceeds the predetermined value and to produce an error signal if the number of samples having the first signal level and the number of samples having the second signal level both exceed the predetermined value. 2. Error detection circuit according to claim 1, characterized in that the comparison means are designed so as to produce a second output signal if the number of samples having the first level does not exceed not the predetermined value.   3. Error detection circuit according to claim 1, characterized in that the comparison means are designed to produce a second output signal if the number of samples having the second signal level   exceeds the predetermined value.   4. Error detection circuit according to any one of the claims.   cations 1 to -3, characterized in that the sampling means comprise logic means which are connected so as to detect the level of the data signal. 5. Error detection circuit according to claim 4, characterized in that the logic means comprise a first AND gate (25) connected so as to receive a clock signal (20) and the data signal (15), and a second AND gate (35) coupled to receive the clock signal (20) and connected to a NON gate (30) to receive the data signal in reverse form; and in that the first AND gate produces said first signal level when the data signal is closer to one of the upper and lower limits, and the second AND gate produces said second signal level when said level of the data signal is closer to each other the upper limits and lower.   6. Error detection circuit according to any one of the claims.   cations 1 to 5, characterized in that the counting means comprise a first counter (40) designed to count the number of samples which have the first signal level and a second counter (45) designed to count the   number of samples that have the second signal level.   7. Error detection circuit according to any one of the claims.   cations 1 to 6, characterized in that the comparison means comprise a first and a second comparator (50, 55), a first and a second locking circuit (52, 57) and a control means (60), the means control   being intended to produce the predetermined value.   8. Error detection circuit according to claim 7, characterized in that, if the number of samples which have the first signal level exceeds the predetermined value, then the first comparator positions the first locking circuit and, if the number of samples that have the second signal level exceeds the predetermined value, then the second   comparator positions the second locking circuit.   9. Error detection circuit according to any one of the claims.   cations 1 to 8, characterized in that the predetermined period corresponds to the period of a data bit.   10. Error detection circuit according to any one of the claims.   cations 1 to 9, characterized in that the counting means and the means of   comparison are repositioned at the start of each predetermined period.