FR2717971A1 - Device for synthesizing a signal form, transmitter station and receiver station comprising such a device. - Google Patents

Abstract

This device comprises a digital circuit (1) for generating the signal to be synthesized in order to supply a first series of digital samples representative of this signal, formed by words with N binary elements and a digital-to-analog converter circuit (30) to supply said signal. signal in analog form. A circuit (40) is also provided for filtering, according to a band-pass characteristic, the samples of the first series and for supplying said digital-to-analog converter circuit (30) with a second series of samples consisting of N words. 'binary elements where N> = N'. A feedback loop (45) subtracts the samples of the second series from the samples of the first series. Application: direct digital frequency syntheses.

Description

DEVICE FOR SYNTHESIZING A SIGNAL FORM, TRANSMITTER POST

  AND RECEIVER STATION COMPRISING SUCH A DEVICE.

Description:

  The present invention relates to a frequency synthesis device, device comprising a digital signal generating circuit to synthesize to provide a first series of digital samples representative of this signal, consisting of words & N binary elements and a digital-converter circuit. analog to provide said

signal in analog form.

  The present invention also relates to a station

  transmitter and a receiving station having such a device.

  A device of this kind finds important applications in particular to develop sinusoidal signals at a given frequency and to constitute, thus, a direct digital synthesizer of frequencies. U.S. Patent No. 5,014,231 discloses the

description of such a device.

  A first requirement often imposed on this kind of device is that the signal provided must be of high purity and a second, which follows, is that it must have no stray line. These lines are caused mainly by the sinusoidal and periodic form to be synthesized. To satisfy this first requirement, it is possible to provide a large number of bits for the samples of the first series. For example, to obtain a sinusoid with a purity of 84 dB, the output samples of the shape generation circuit must have 14 bits. This follows from the formula: Nb R / 6 where Nb is the number of bits and R is the ratio in decibel between the level of the

  sinusoid and parasitic lines.

  Then, when one wants to use this kind of device for high frequencies, for example of the order Inv.93 / 120 PHF 94/515 FR of a few hundred megahertz, the problem of finding a digital-to-analog converter circuit cheap. To satisfy the second requirement, the aforementioned patent proposes to add a random number to the samples of the first series. If, in this way, the level of these lines is lowered, it is to the detriment of a general degradation of the purity of the signal and the presence of a converter can not be avoided.

expensive digital-analog

  The invention proposes to avoid the use of a digital-to-analog converting circuit processing a large

number of bits.

  For this, such a device is remarkable in that there is provided a mounting for filtering according to a band-pass characteristic the samples of the first

  series and to provide to said digital converter circuit-

  analogously a second series of samples consisting of words with N 'bits o N 2 N' and in that a feedback loop is provided to subtract from the samples

  from the first series the samples of the second series.

  The following description with reference to the drawings

  annexed, all given as a non-restrictive example, will

  understand how the invention can be realized.

  - Figure 1 shows an embodiment of the invention. FIGS. 2a and 2b show the shape of the samples of

  the first and the second series.

  - Figure 3 shows the block diagram of the device

the invention shown in FIG.

  FIG. 4 shows an advantageous embodiment of a

device according to the invention.

  FIGS. 5a and 5b show a transmitter station and a

  receiving station having such a device.

  In FIG. 1, the reference 1 indicates a digital generation circuit. This circuit provides at its output 5 a

  first series of digital samples Ecl, Ec2, E c3, ....

  representing sinusoidal Sin as shown in Figure 2a. These samples are words with N binary elements, for example N = 16, and are supplied at the rate of a clock circuit 10. This circuit 1 comprises, according to the mode of embodiment shown in FIG. 1, an accumulator 12 whose output 13 is connected to the addressing input of a memory 20. The accumulator is formed, in the usual way, of an addition member 25 whose output is connected to a register 28. The output of this register constitutes the output of the accumulator and is connected, in addition, to a first input of the member 25. The second input of this organ receives the indication, under digital form, the frequency to synthesize Fs. This frequency may vary according to AFs steps depending on the desired use. The input of this register is connected to the output of the organ 25 and its

  load control at the output of the clock circuit 10.

  The output samples after processing, which the invention provides, are applied to the input of a digital digital converter 30 which provides at the output 32 a sinusoidal signal. This signal does not present parasitic signals that are difficult to suppress by an analog band-pass filter 35 for which no delicate constraint

is not imposed.

  In accordance with the invention, the digital-to-analog converter circuit 30 processes a second series of binary bit samples with N 'bits, for example N' = 12, derived from the samples of the first series. An assembly 40 is provided to provide at its output 42 connected to the converter circuit 30 filtered and truncated samples in their number of bits. There is also provided a counter-reaction formed from a subtraction member 45 which subtracts from the samples of the first series which arise at the output 5 the samples of the

  second series which arise at the exit 42 of said assembly 40.

  The assembly 40 is formed firstly of a digital filter 60, an exemplary embodiment of which is shown in FIG. 4, and of a truncation member 61 which reduces the number of bits of the words applied to its input. This is schematically illustrated in FIG. 2b, the Inv.93 / 120 PHF 94/515 FR graduations As on the vertical axis are much more distant than

  the graduations Ae of Figure 2a. Eccl, Ecc2, Ecc3, ....

  are the samples drawn according to this new graduation to define the sinusoid Sin. The member 61 can be made by means of a read-only memory or simply by neglecting the bits of lower weight. The filter 60 is centered around a frequency fo which is the average value of

the variation of Fs.

  Figure 3 is a diagram for explaining the device of the invention. The quantities in play are variables sampled at the rate of T o T is the sampling period fixed by the clock 10, and we consider them at the instant "n". Thus, x (n) represents the sample at the output 5, v (n) is the sample at the output of the filter 60 and y (n) is the sample at the output 42 mounting 40. On this diagram, are only the elements necessary for this explanation are represented. It will be noted that the truncation member 61 is represented by a noise adder b (n) at the signal v (n) at the output of the filter 60. This noise b (n) represents the error made by the truncation member on samples with a larger number of bits. By taking the Z transforms of these magnitudes X (Z), V (Z) and Y (Z) and using the Z transfer function of the filter 60 which is written H (Z), the following relations are established: :

V (Z) = [X (Z) - Y (Z)] H (Z)

Y (Z) = V (Z) + B (Z)

  which finally gives: y (Z) = X (Z) H (Z) + B (Z)

1 + H (Z) 1 + H (Z)

  This last formula shows that if H (Z) has a large modulus then Y (Z) becomes close to X (Z) while the contribution

  of B (Z) is reduced by the value of the H (Z) modulus.

  It goes without saying that the errors made by the truncation member still exist but that their spectrum is rejected out of the bandwidth of the filter so that the Inv.93 / 120 PHF 94/515 EN analog filter 35 can then easily reject these

parasitic components.

  Figure 4 shows a preferred embodiment of the invention. In this embodiment, the digital generation circuit 1 is a digital resonator circuit. It is

  formed of two delay elements 81 and 82 cascaded.

  The input of the element 81 is connected to the output of an addition member 85 which constitutes that of the circuit 1. The addition device 85 receives the result of two multiplication elements 88 and 90 which respectively multiply by b1

  and by b2 the samples at the output of elements 81 and 82.

  Two switches 95 and 96 allow to apply values

  initials at the inputs of elements 81 and 82.

  It is easy to show that such a circuit oscillates at a frequency Fs which is deflected by the value b1 which gives the agreement of the tuning frequency: cos2nF. T = + b1 / 2 b2 = - 1 To ensure a good stability of the digital wave supplied, this circuit is reinitialized, with a period Ti, by the following values, by acting on the switches 95 and 96 ( Ti has a value of the order of one second and is chosen to avoid any untimely discontinuity): x (0) = A x (-1) = A cos 2nF.T

  o A is a constant defining the amplitude of the wave.

  FIG. 5 also shows a possible structure of the digital filter 60. It is a purely recursive filter structure formed of a plurality of delay elements 100, 101, 102, 103, ... connected to the output of the filter. The signals at the outputs of these delay elements are multiplied by different coefficients bp1, bp2, bp3, bp4,... By means of multiplying elements 110, 111, 112, 113, .... 120 to 123 ... add to the input signal all the signals at the output of the elements 110, 111,

112, 113, ...

  Inv.93 / 120 PHF 94/515 FI The value of these different coefficients bp1, bp2, bp3, bp4, .. depends on the frequency F. to be synthesized and on the spectral purity to be obtained. These values determine the filtering characteristic. In the book: "DIGITAL PROCESSING OF SIGNAL" by M. BELLANGER published by Masson editions all indications for the realization of this filter as well as other possible structures and not

necessarily purely recursive.

  A conversion member 150 ensures the changes of the different values b1, bpl, bp2, bp3, bp4, x (O) and x (1) in

  function of the value Fs to be synthesized.

  FIG. 5 shows a transmitter station comprising a synthesis device 100 according to the invention. The device 100 is used to set the carrier frequency of the signal to be transmitted on the antenna 110. A modulator 120 modulates this frequency as a function of information provided by a processing circuit 130 receiving on a terminal 135 the useful information to be transmitted. FIG. 5 shows at b a receiver station comprising a synthesis device 200 according to the invention. The device 200 serves as a local oscillator for demodulating or charging, by means of a circuit 220, the frequency of the wave received by the antenna 230. A processing circuit 240 establishes the information for the user on a terminal 245. Inv.93 / 120 PHF 94/515 EN

Claims (4)

CLAIMS.   1 - Frequency synthesis device, device comprising a digital signal generating circuit to be synthesized to provide a first series of digital samples representative of this signal, consisting of words with N bits and a digital-to-analog converter circuit to provide said signal in analog form, characterized in that there is provided an arrangement for filtering the samples of the first series according to a band-pass characteristic and for supplying to said digital-to-analog converter circuit a second series of samples consisting of N 'bits   o N k N 'and in that a counter loop is provided   reaction to subtract from the samples of the first series   the samples of the second series.   2 - frequency synthesis device according to claim 1, characterized in that the digital signal generation circuit is constituted from a memory containing the digital samples addressed by a code   defining the frequency to be synthesized.   3 - frequency synthesis device according to claim 1, characterized in that the digital signal generation circuit is formed from a digital resonator circuit formed of at least one delay element and an addition member for summing samples at the inputs and outputs of said weighted elements by agreement weighting values.   4 - Frequency synthesis device according to one   Claims 1 to 3, characterized in that the mounting in   cascade comprises a recursive digital filter formed of at least one delay element and an addition element for summing samples at the inputs and outputs of said elements   weighted by filtering weight values.   - Frequency synthesis device according to the   claims 3 and 4, characterized in that a   a tuning circuit which provides the tuning and filtering values Inv.93 / 120 PHF 94/515 EN according to the frequency to be synthesized. Inv. 93/120 PHF 94/515 EN