FR2704337A1 - Logic device for centralized management. - Google Patents

Abstract

The present invention relates to logical devices for centralized management of a plurality of elements to be managed 23, 24, 25. The device according to the invention is essentially characterized by the fact that it comprises a central management unit 1 with two lines. inputs-outputs 2, 3 capable of transmitting and receiving data messages comprising an address, control input means 4, a plurality of repeater means 5, 6, 7 each comprising two first 8, 9, 10 and second 11, 12, 13 input-output terminals and bypass input-output means 14, 15, 16, the repeater means being connected in series to form a ring management circuit 17 whose two ends are respectively connected to the two input-output lines 2, 3, and controllable automatic addressing means 20, 21, 22 connecting the bypass input-output means 14, 15, 16 to the elements to be managed 23, 24, 25. Application to the control of various elements of a machine tool in the mechanical industry, various components of a motor vehicle such as headlights, indicators, control elements, etc.

Description

I.The present invention relates to logical management devices

  centralized, that is to say the devices that allow, according to different predefined data, to control different elements of an application, for example different elements of a machine tool in the mechanical industry such as sensors, actuators , various elements of a motor vehicle such as headlights, turn signals, control elements, etc. There are already centralized management devices comprising a programmable central unit, for example based on a microprocessor, which

  emits signals able to control different elements.

  However, the centralized management devices known to date have the disadvantage of requiring a major programming study to define a specific program or software

  to the intended application for each device.

  In addition, the elements to be controlled are connected directly to the central unit by wired connection means and, when the number of these elements is important, the number of wired links becomes very high, which contributes to considerably increasing the cost of returns from the entire management device and, for example, the weight of the vehicle whose various elements are controlled by such a centralized management device embedded. These disadvantages have important consequences in the industrial world. The object of the present invention is thus to provide a logical centralized management device for a plurality of elements to be managed, which overcomes most of the disadvantages mentioned above while making it possible to obtain results identical to those obtained with the devices of the prior art. More specifically, the subject of the present invention is a logic device for centralized management of a plurality of elements to be managed, characterized in that it comprises: a central management unit comprising two first and second input-output lines capable of transmitting and receiving at least data messages comprising an address, control input means, a plurality of signal repeater means, each repeater means comprising two first and second input-output terminals and means input-output device of said signals, said repeater means

  being connected in series between their first and second input terminals-

  outputs for forming a ring management circuit between two ends, the two said ends being respectively connected to the two first and second input-output lines of said central unit, and a plurality of controllable automatic addressing means, each connecting the input-output means for bypassing a repeater means to

an element to manage.

  Other features and advantages of the present invention

  will appear in the following description given next to the drawings

  appended by way of illustration, but in no way limiting, in which: FIG. 1 represents the block diagram of an embodiment of a centralized management logic device according to the invention, FIG. 2 represents the block diagram of a mode of embodiment of the repeater means forming part of the embodiment of the device according to FIG. 1, FIG. 3 represents the block diagram of one embodiment of the controllable automatic addressing means forming part of the embodiment of the device according to FIG. FIG. 4 represents the block diagram of an embodiment of the central management unit forming part of the embodiment of the device according to FIG. 1; FIG. 5 represents the block diagram of a mode. embodiment of a part of the logic module present in the block diagram of FIG. 4, corresponding to the control and command of the direction of propagation of the signals emitted by the unit FIG. 6 represents an operating diagram explaining the implementation, in the device according to the invention, of bursting and concatenation functions. FIG. 7 represents the block diagram of one embodiment of another embodiment. part of the logic module present in the block diagram of FIG. 4, corresponding to the functions "bursting" and "concatenation" in association with a control and control logic, FIG. 8 represents the block diagram of one embodiment of the means performing the "concatenation" function in accordance with the representation according to FIG. 7, and FIG. 9 represents the block diagram of an embodiment of the intermediaries realizing the "bursting" function in agreement with the representation

according to Figure 7.

  Figures 1 to 9 show a same embodiment of a centralized management logic device. Consequently, the same references designate the same elements, whatever the figure on which they appear. FIG. 1 represents the block diagram of an embodiment of a logic device according to the invention, of centralized management of a plurality

of elements to manage.

  This centralized management logic device comprises a central management unit i comprising two first 2 and second 3 input-output lines, control input means 4, a plurality of signal repeater means 5, 6, 7,. .., each of the repeater means comprising two first 8, 9, 10, ... and second 11, 12, 13, ... input-output terminals and bypass input-output means 14, 15, 16

  . signals. These repeater means are connected in series with each other between their first 8, 9, 10, ... and second 11, 12, 13, ... input-output terminals to form a ring management circuit. 17 between two ends 18, 19..DTD: respectively connected to the two first 2 and second 3 input lines-

  outputs of the central unit 1. The centralized management logic device also comprises controllable automatic addressing means 20, 21,

  22, ... connecting, each, the input-output bypass means 14, 15, 16, ...

  repeater means 5, 6, 7, ... to an element to be managed 23, 24, 25, ....

  The function of the central unit 1 is to deliver messages in the form of signals or signal trains such as, for example, series of bits "0" to one of its two input-output lines 2, 3. and "'T'". The constitution of these messages is adapted to the general configuration of the device. It can be broken down into two entities: a control entity which can be defined by a first field for the addressing composed of "i" bits, a second field for Ila subaddress composed of "j" bits and a third field allowing define the number of information contained in the messages and exchanged between the central unit 1 and the elements to be managed composed of "k" bits, and a data entity whose size is function of the message. In the example chosen for the

present description:

  i = 6; j = 4; k = 14 D'I) a normal way, the logical management unit 1 is shaped to send messages "go" so that they travel the ring management circuit 17 from a first line of inputs-outputs , for example its input-output line 2, towards the second, or its input-output line 3, the messages successively crossing the different

  repeater means 5, 6, 7, ... according to this chronological order.

  It is first necessary to initialize the device by assigning each element to be managed 23, 24, 25, ... an address of its own, different from the addresses assigned to other elements. According to an advantageous embodiment, the various addresses intended to identify the elements to be managed have increasing values, for example "1", "2", 11 "3", ... "N", in chronological order. repeater means 5, 6, 7, ... in the direction of rotation on the ring management circuit 17, from the input-output line 2 to the input-output line 3, that is, to say in the chronological order of the elements

  to manage 23, 24, 25, ... associated with these repeater means. The address value "N" above

  above is therefore the maximum number of addressing means 20, 21, 22, insertable in the circuit 17. It can be calculated by the following equation: N = 2i-2

  In the example chosen for the present description, N = 62.

  To initialize the device, the central unit 1 sends on the ring management circuit 17 successive messages each having a different address which will be assigned to an element to be managed and will be implemented.

  memory in the controllable automatic addressing means 20, 21, 22.

  associated with this element to be managed, according to the operation described below.

  The central unit 1 sends, on its first line of inputs-outputs 2, a first message said "go" comprising, for example, the address "i1". In this initial state, the repeater 5 is blocked and derives this first message to the controllable automatic addressing means 20 which analyze it and store the value of the address "1" while returning to the central unit 1 , in the direction opposite to that defined above, that is to say in the direction "repeater 5" to the first line of inputs-outputs 2, a "return" message confirmation of storage of this address "1", then unlocking the

repeater 5.

  When this first address message "1" has been stored in the addressing means 20 associated with the element 23 to be managed, the central unit 1 sends on its input-output line 2 the message "to go". "next having an address of greater value than the first, for example" 2 ". This message will be analyzed by the addressing means 20 which will not recognize its address and, therefore, remain transparent. This message therefore passes through the first repeater 5 and is applied to the first input-output terminal 9 of the repeater 6 which is blocked and which derives this message to the addressing means 21 associated with the element to be managed 24. In the same way that previously the addressing means 20, the addressing means 21 stores the address "2", return to the central management unit 1 a "return" message confirmation of storage of the address " 2 "and unlock the repeater 6. These operations are repeated as many times as there are elements to manage and that the device includes sets" repeater means "and" addressing means ". The maximum number of addressing operations is a function of the number of addressing means connected to the ring circuit 17. It is

  limited to "N", that is, to "62" in the example chosen.

  When the addresses have been defined and respectively allocated to each addressing means as defined above, the device can

  operate and manage the different elements 23, 24, 25, ... as described above.

  after, being specified that the direction of propagation of the messages "go" in the ring management circuit 17 is automatically defined according to the address of the message and the state of this circuit, and that the messages "return" ", if they exist, always propagate in the opposite direction to that of the

propagation of "go" messages.

  When an element must be controlled according to a predetermined order, following a control command applied to the input 4 of the central unit 1, for example by a user pressing a button, the central unit generates a message comprising the address of the element to be managed and the order that corresponds to the command to be performed on this element. The device actually has two modes of operation, a first so-called "cyclic" mode that ensures determinism and security, and a second mode called "random", these

  two modes being explained below.

  This message is sent in the ring management circuit 17 so as to traverse it in the direction of the input-output line 2 to the input-output line 3. It passes through the different repeaters 5, 6, 7 , ... being each time derived on the input / output terminal of derivation 14, 15, 16, ... As long as the address of the message does not correspond to the address stored in the means of addressing 20, 21, 22, ..., the message is not processed by the addressing means and continues its progression in the ring circuit 17. When the message has reached the repeater associated with the addressing means containing in memory the address of this message, the addressing means transmit the message of the command to the element to be managed to operate the

desired order.

  When this command is carried out, the element to be managed, in association with its addressing means, sends a confirmation "return" message to the central unit, in the opposite direction to that of the propagation of the message of the order order he had received. This "return" message blocks the repeater associated with the controlled element during the time of

  its emission, the repeater becomes active again at the end of the "return" message.

  The message "go" continues its way in the ring management circuit 17 because it may interest other elements to manage. In this case, it is

  an exchange called "broadcast" that does not include a message "return".

  FIG. 2 represents the block diagram of an exemplary embodiment of the repeater means 5, 6, 7 ..., and more particularly repeater means 5, forming part of the constitution of the embodiment of the device illustrated in FIG. 1 , being specified that all repeater means are

  identical and that, from the description of one of them, it is possible to deduce

  embodiment of all others.

  These repeater means 5 comprise a first input terminal

  outputs 8 consisting essentially of transmitter means 30 and receiver means 31, and a second input-output terminal 11 symmetrically constituted by a transmitter 32 and a receiver 33..As a result, these terminals 8 and 11 may be both inputs and outputs for receiving as well as transmitting signals. These emitters and receivers are for example constituted by optocouplers which also provide a

  galvanic isolation between the different repeater means.

  The emitters 30 and 32 receive, through respectively two multiplexers 36 and 37, the signals which are developed in a control logic 34 which receives, on bypass inputs 35 belonging to the input-output branching means 14, signals from

  addressing means 20 and / or the element to be managed 23.

  The repeater means 5 further comprise a first cladding module 38, an output of which is connected to an input of the multiplexer 36 and of which another output is connected, through a logic gate 39, to the addressing means 20. The inputs of FIG. covering module 38 are respectively connected to an output of the control logic 34 and to an output of the addressing means 20. The function of this dressing module is to complete the message that will be sent by the transmitter 30 for obtain a complete "return" message capable of being recognized by the central management unit 1 if the message

  "go" was received on the first input-output terminal 8.

  The repeater means 5 also comprise a second cladding module 40, an output of which is connected to the transmitter 32 through the multiplexer 37 and of which another output is connected to an input of the addressing means 20 through the logic gate 39. The inputs of the dressing module 40 are respectively connected to an output of the control logic 34 and to an output of the addressing means 20. This dressing module 40 enables the message to be transmitted by the transmitter to be processed. 32 to obtain a complete "return" message capable of being recognized by the central management unit 1 if the

  "go" message was received on the second I / O terminal 11.

  These repeater means 5 furthermore comprise, at the output of the two receivers 31 and 33, receiver logic modules 50 and 51 whose inputs and outputs are respectively connected to the control logic 34 and to the means

  addressing 20 through two logic gates 41 and 42.

  A repeater as illustrated in FIG. 2 essentially has three modes of operation, a transmit mode, a receive mode, and a repeat mode. The operation of this repeater can be broken down into four phases, a phase A which is a phase of waiting for the reception of the "go" message, a phase B which is a reception phase of the "go" message, a phase C which is an analysis phase of the "go" message and a phase D which

  is a response phase, that is to say emission of the message "return".

  During phase A, the modules 50 and 51 are respectively listening for the links 8 and 11, the transition to phase B being done on arrival of a "go" message. At the arrival of a "go" message, for example on the input 8, the module 50 carries out the following processes: activation of a message signal during reception and sending of this signal to the control logic 34 and to the addressing means 20 via the logic gate 42, - reformatting the received signal and sending it to the multiplexer 37, - undressing the received message and sending it to the addressing means 20

via the logic gate 41.

  During phase B, that is to say upon receipt of the message, the control logic 34 prohibits the listening of the circuit 17 by blocking the module 51 and validates the routing of the message by the multiplexer 37 to obtain transmission through the transmitter 32 of the message received at the input 8 and

reformatted by the module 50.

  The transition to phase C is done on the detection of the end of the "go" message. The module 50 disables the message signal being received and sends it to the logic 34 and the addressing means 20) via the logic gate 42. Upon receipt of this message, the logic 34 blocks the repeater 5 and the means addressing 20 analyze the address of the received message. If these addressing means do not recognize the specific address assigned to the element to be managed 23 or if they recognize a broadcast address assigned to all the elements, then these addressing means 20 transmit to the logic 34 an end of exchange signal which makes the repeater go back to phase A. If the addressing means 20 recognize the specific address assigned to the element to be managed 23, they go to phase D. During this phase D, repeater 5 processes the message "go" and prepares the message "return". A control command is sent to the logic 34 which blocks the modules 50 and 51 and activates the multiplexer 36 so that the data transmitted by the addressing means 20 dressed by the module 38 can be transmitted by the transmitter 30. detection of the end of the "return" message, the addressing means 20 generate, to the logic 34, an end of exchange signal that makes the repeater in phase A. The process

  reverse is done for all messages received at input 11.

  FIG. 3 represents the block diagram of an embodiment of the controllable addressing means 20 forming part of the constitution of the embodiment of the device according to FIG. 1 described above. In the advantageous embodiment illustrated, these addressing means 20 comprise a reception processing module 43 whose inputs are connected to bypass outputs 55 belonging to the bypass input / output means 14 of the repeater means 5 defined herein. above and whose outputs are respectively connected to inputs of a comparator 44 and to control inputs of an address extractor 45. The addressing means 20 further comprise an address memory 46 whose inputs 47 The outputs of this address memory are respectively connected to the control inputs of a transmission processing module 48 whose outputs are connected to bypass inputs 54 belonging to the bypass input-output means 14 of the repeater means 5 defined above, and to inputs of a signal state-building module 49, this module is also connected to

comparator 44.

  The addressing means described above have two possible functions, a function allowing the automatic allocation of the address and a

work function.

  For the function allowing the automatic assignment of the address, two cases must be considered: the initialization function and the deactivation function. At initialization, the module 49 blocks all the dressing means 38, 40, the multiplexers 36, 37 and the transmitters 30, 32 via the bypass input 35 of the control logic 34. On the arrival of a "go" message, the module 43 receives it from the bypass outputs 55 of the repeater means 5. It sends it to the comparator 44 and the address extractor 45. The comparator 44 compares the address of the message with a predefined reference value that corresponds to a "message-address label". If the comparator does not recognize this tag, there is no initialization and the

  Addressing means are waiting for a new message.

  If, on the other hand, the comparator recognizes the label, the extractor 45 extracts the address to be stored contained in the data field of the received message and controls its storage in the memory 46. This memory 46 sends a command signal to the module 49 to initialize it and another command signal to the module 48 which produces a "return" message which is transmitted to the repeater 5 via

  the bypass inputs 54 of this repeater 5.

  The initialization of the addressing means 20 is performed.

  I.a deactivation function is that which allows to go from the initialized state to the uninitialized state. To perform this deactivation, it is sent

  on the management circuit 17 a message "go" of deactivation.

  The process of deactivating the addressing means 20 is substantially identical to that of its initialization. However, in this case comparator 44 compares the address of the received "go" message with a predefined reference value which corresponds to a "message-address reset tag". As long as the comparator does not recognize this label in the "go" message received, the addressing means retain their initialization state. If the comparator recognizes the reset label, it carries out the following processing: the memory 46 is emptied, it generates the end of exchange signal, the module 49 is deactivated and sends a command signal to block the transmitters 30, 32, cladding modules 38, 40 and multiplexers

  36, 37. Repeater 5 goes to sleep and waits for a new message.

  The operation of the addressing means 20 in their normal working function is carried out as follows: The element to be managed 23 receives the data of the "go" message via the module 43 and a message recognition signal from the comparator 44. The same element 23 provides the module 48 with a request

  sending a "return" message as well as data to be transmitted.

  Any message received at the inputs-outputs 8 and 11 of the repeater 5 is derived and presented to the module 43 via the receiver 31, the module 50, the logic gate 41, the input-output terminal 14 (if the reception is on the input-output 8), or via the receiver 33, the module 51, the logic gate 41 and the input-output terminal 14

  (if the reception is done on the input-output 11).

  The module 43 analyzes the message received and present to the comparator 44 the address of the message. The comparator 44 knows that the addressing means 20 are initialized because it receives a signal generated by the module 49. It compares the address of this message with that stored in the memory 46. The processing

  is terminated if there is no address equality.

  On the other hand, if there is an equality of addresses, the data of the message is transmitted to the element to be managed 23. The latter processes this data according to the application requested, then supplies the module 48 with a request request.

  sending a "return" message and the data associated with this message.

  The module 48 dials the "return" message so that it is transmitted via the repeater 5

  to the Central Management Unit 1.

  The structure and operation of the repeater means 5 and the addressing means 20 described above are identical for each set "repeater means 5, 6, 7, ..." and "addressing means 20, 21, 22, ... ", knowing that the" return "messages always propagate in the opposite direction to that of the

  propagation of messages "go" command of the elements to manage.

  FIG. 4 represents the block diagram of an embodiment of the central management unit 1 forming part of the constitution of the embodiment

of the device according to FIG.

  This central unit i essentially comprises a logic module

  central management 60 which has two inputs-outputs 61 and 71.

  The input-output 61 is connected to an output transmitter 62 through a transmission processing module 63 and to a receiver 64 through a reception processing module 65. The output 66 and the input 67 respectively transmitter 62 and receiver 64 are connected together to form the line

  I / O 2 defined previously.

  The input-output 71 is connected to an output transmitter 72 through a transmission processing module 73 and to a receiver 74 through a reception processing module 75. The output 76 and the input 77 respectively transmitter 72 and receiver 74 are connected together to form the line

  I / O 3 defined previously.

  The management unit 1 further includes a plurality of modules having different functions which are all interconnected by a bus 80. These modules of different functions are for example constituted by an interface module 81, a maintenance module and errors 82, an interface module of different applications 83 and an exchange memory module 84. The central management unit i further comprises control input means 4 which allow the potential users of the device to develop different control commands and / or to exchange data in memory of exchanges. The central management unit can thus fit into a system

  host and interact with it via the control input means 4.

  The bus 80 is connected to the inputs 88 and 89 of the central management logic module 60 through a control module 90 generally constituted by a micro-sequencer such as, for example, a PROMNI memory looped on a

  register, and through an exchange memory interface module 91.

  The exchange memory 84 advantageously comprises two parts,

  a "data" part and a "frame" part.

  The "frame" part is used for the management of the entire ring circuit 17 by the central management unit 1. This "frame" part can be contained in a PROM or in a RAM or in a combination of these two types of memory. When the "frame" part is composed only by a RAM, it is the reception system, via the input means 4, which provides the data necessary for the management of the "frame" part and which places them in this frame. memory. When this "frame" part is composed of a combination of a PROMN and a RAM, the PROM constitutes a cyclic frame background and the system

  host will insert the messages in this cyclic frame.

  I.a "data" part is used to store all the data

  propagate throughout the device.

  There are in fact two possibilities for accessing the exchange memory 84, either by the reception system via the input means 4 and through the interface module 83, or from each set "element to

  manage-addressing-repeater means "says" MIES ".

  For example, if a device according to the invention is installed in a motor vehicle and comprises a set MNES "headlights-means

  "repeater addressing", the device operates as follows.

  The set MES receives a message "go" with a control of lighting of the headlights. In the "return" message, it sends the information "lights on" if this information is present on an application input of the set MIES, that is to say if it was previously stored in the exchange memory 84,

  because a set of MNIES can not create information.

  In general, a set MES provides on its application outputs the information it has received in a "go" message sent by the central management unit 1. In the "return" message, it transmits to the unit management center 1 the information present on its application inputs and

  stored in the trading memory 84.

  Returning to the application example chosen above, there are two possibilities for controlling the lighting of the headlights. If the central management unit does not include a reception system, the "lighting headlights" command is made from a command injected on an application input of a set MES. The information "control of the lighting of the headlights" is taken by this set MNIES to be transmitted to the exchange memory 84 in a "return" message. From this moment, the device operates in the same way as described below, from this memory

of exchange 84.

  When the central management unit is inserted in a reception system, it is this system which carries out the application "control of the lighting of the headlights", the ring circuit 17 only serving as support for the transmission to convey the information contained in the messages

"back and forth".

  However, it is possible that in the ring management circuit 17 occurs at least one break preventing certain messages from occurring.

  propagate in the direction of the input-output line 2 to the input-line

  outputs 3 and reach the repeater means associated with the elements to be managed

for which they are intended.

  The device according to the invention is advantageous because it is said to be "fault-tolerant", that is to say it knows how to take into account and overcome so-called "simple" failures. For example, it is able to support a cut of a wired segment between two sets MES and continue to operate

  correctly without loss of information and ensuring initial determinism.

  In the case where several wire segments connecting two successive MES sets are cut, only the MES sets between the two extreme cut wire segments are isolated, all others remain accessible. The device performs its self-monitoring permanently and, when a fault is detected on the circuit 17 by monitoring means included in the central management logic 60, the part 100 (described below with reference to FIG. 5) whose function is to automatically define the direction of propagation of the messages in the ring management circuit 17 is activated. To perform the self-monitoring of the state of the ring management circuit 17, "go" messages are sent in the circuit from the input-output line 2. The central unit 1 then goes into mode. waiting to receive the "return" message. Upon receipt of this "return" message, the monitoring means verify the complete consistency of this message and compare its address with that of the "go" message. If there is no error detected, the exchange is considered good. If an error is detected (for example inconsistency of the "return" message, mismatch of the two addresses), the address of the "go" message is saved in an intermediate register of logic 60. The same "go" message is sent again, possibly several times for security. If error is confirmed, the value of the address saved in the intermediate register is stored as a break address in a

  memory of part 100 of logic 60.

  FIG. 5 represents the block diagram of part 100 of the central management logic module 60 whose function is to define automatically

  the message propagation direction in the ring management circuit 17.

  This part 100 comprises, from a bus 103 conveying the various messages to be sent in the ring management circuit 17, an address extraction module 104 whose output is connected to a first input 105 of a comparator 106, the other input 107 of the comparator being connected to an output 108 of an analysis and control module 109, this analysis and control module 109 being able to deliver to this output 108 a reference value corresponding to the value of the break address. The comparator 106 is able to deliver on its two outputs 110 and 111 two types of control signals depending on whether the addresses of the messages applied to its input 105 are smaller or greater than or equal to the breaking address value, these signals controller controlling the analysis and control module 109 for controlling, ie the opening of the transmitting means 62-63 and receiving means 64-65 forming the input-output line 2 and the closing of the transmitting means 72-73 and reception 74-75 for sending the messages conveyed on the bus 103 having addresses less than the value of the breaking address on the input-output line 2, ie the closing of the transmission means 62 63 and reception 64-65 and the opening of the transmission means 72-73 and reception 74-75 forming the input-output line 3 to send the messages carried on the bus 103 having higher or equal addresses to the value of the break address on the

  line of inputs-outputs 3, which allows to obtain the results defined above.

  In the case of so-called "broadcast" messages which concern all MES sets, they are systematically transmitted in the direction of the first line of inputs-outputs 2 to the second, then in the opposite direction. The device guarantees the routing of this type of message irrespective of the state of the message.

ring circuit 17.

  The device according to the invention can, in an advantageous embodiment, manage two types of data, so-called "unmarked" data and so-called "Boolean" data. The "unmarked" data is transparent to the device, that is, it can be processed without being adapted or modified. "Boolean" data is trivialized data sets and is usually in the form of signal sequences

logical "0" and "T" "".

  As recalled above, the transfer of information in the device is performed in the form of a message which is generally a set of pulse trains. These messages are exchanged via the ring management circuit 17 between the central management unit 1 and the signal repeater means 5, 6, 7, ... to reach, through the addressing means

  , 21, 22, ..., the different elements to be managed 23, 24, 25, ..., and vice versa.

  The central unit 1 prepares the various messages necessary for the management of the different elements with information B1, B2, B3,..., FIG. 6, which are contained in the exchange memory 84 and store in this memory

  the information it has received from the items to be managed.

  Advantageously, the central management logic module 60 performs a bijection between the data of a message arriving or departing from the input-output lines 2, 3 (for example eight consecutive bits whose rank

  in the message is "modulo 8") and the addresses of the exchange memory 84.

  In this case, it is said that the device works "by unmarked information". However, the device can also operate by duplicating information. In this case, the central logic management module 60 performs the automatic transfer of information input or output of a repeater means to the input or output of another repeater means, or several others. This module 60 transforms the bijection mode defined above into an overjection. Thus, an address of the exchange memory 84 corresponds to an input and at least one output, this mechanism being able to be used with a

  unmarked data or Boolean information.

  In order for the device to operate in Boolean mode, it comprises, on the one hand, data bursting means (for example eight consecutive bits whose rank in the message is "modulo 8") consisting of "8" information. Booleans in "8" trivialized information in the exchange memory 84, and on the other hand means of concatenation to obtain the

  inverse function to that of the burst.

  These means of bursting and concatenation can cooperate with

means of association.

  The associating means make it possible to associate, with an input information stored in a box of the exchange memory 84 (whether this information comes from a set MES or from the reception system via the input means 4) , one or "n" output information, knowing that all these

  information must be of the same nature.

  The bursting means make it possible to decompose "n" consecutive elementary bits whose rank in the "return" message is "modulo n" into "n" information that can be stored in the exchange memory

  84, knowing that this information can take two Boolean values.

  The concatenation means make it possible to gather "n" information contained in the exchange memory 84 into "n" elementary bits whose rank in the "go" message is "modulo n", knowing that

  this information can take two Boolean values.

  To this central management logic module 60 is associated a transcoding table 120 (FIG. 6) which makes it possible to control, in particular through the central management logic module 60 and the memory interface module.

  of exchange 91, the addressing of the exchange memory 84.

  FIG. 6 diagrammatically shows the operating diagram of the mechanism described above in which 121 represents, in a first case, a message arriving via an input-output line 2, 3 in the central management unit 1 (FIG. from the repeater means) and which, thanks to the bursting means contained in the central management logic module 60, is split into boolean information B1, B2,..., Bn which are stored in the exchange memory 84 according to the transcoding table 120. In this same FIG. 6, is shown diagrammatically the diagram of the mechanism described above in which 121 represents a message sent by the central management unit 1 and obtained by grouping 123 of Boolean information. B1, B2, ..., Bn contained in the exchange memory 84 by virtue of the concatenation means contained in the central management logic module 60 in association with the transcoding table 120. FIG. shows the block diagram of an embodiment of another part 130 of the central management logic module 60 present in the block diagram of FIG. 4, corresponding to the functions "bursting" and "concatenation" in association with a logic circuit of FIG. control and

command 133.

  This portion 130 of the logic module 60 includes a concatenation module 131 whose block diagram of an embodiment is shown in Figure 8 described below. Its input 132 is connected to the exchange memory 84 through the exchange interface module 91 and its output 134 is connected, on the one hand, to the first input-output line 2 through a first buffer register transmission 135, and secondly to the second input-output line 3 through a second transmit buffer register 136. The concatenation module 131 and the two transmit buffer registers 135 and 136

  are controlled from the control and control logic circuit 133.

  This portion 130 further comprises a bursting module 137 whose block diagram of an embodiment is shown in Figure 9 described below. The output 138 of this burst module 137 is connected to the exchange memory 84 through the exchange interface module 91. The first and second input-output lines 2, 3 are connected to the input 139 of this bursting module 137 through, respectively, two receiving buffer registers 140 and 141. The bursting module 137 and the two receiving buffer registers 140 and 141 are driven by the control logic circuit and

command 133.

  As mentioned above, FIG. 8 represents the block diagram of an embodiment of the concatenation module 131. This module very schematically comprises, from a data bus 150 constituting its input 132, a module acting in transparent 151 and a module operating in Boolean mode 152, that is to say for performing a detection and coding of Boolean type information. These two modules 151 and 152 are connected in parallel on the bus 150 and their respective outputs 153 and 154 are connected to the input 155 of a data storage module 156. This data storage module essentially consists of a set of "n" flip-flops 157. The output 158 of this data storage module 156 is actually the output 134, defined above Cll

  FIG. 7, of the concatenation module 131.

  The two transparent mode 151 and Boolean mode modules 152 are controlled from a management module 159 which is synchronized and

  controlled from a logic counter 160 (modulo "n").

  FIG. 9 represents the block diagram of an embodiment of the burst module 137. This module includes a received data storage module 161 whose input 162 is connected to a data bus 163 which constitutes the input 139. defined above. This received data storage module 161 consists essentially of a set of "n" flip-flops 164. The output 165 of this module 161 is connected to the inputs 166 and 167 respectively of a module operating in transparent mode 168 and a module operating in Boolean mode 169. The outputs 170 and 171 of these two modules 168 and 169 are connected to an output data bus 172 which constitutes the output

  138, defined above with reference to FIG. 7, of the bursting module 137.

  The two transparent mode 168 and boolean mode 169 modules are controlled from a management module 173 which is synchronized and

  controlled from a logic counter 174 (modulo "n").

  The embodiment of the centralized logical management device

  described above contains only one central management unit 1.

  However, in order to obtain a device having an even greater reliability, it is possible to produce a device according to the invention comprising a second central unit coupled to the first with

  repeater means of the same type as those described above.

  It is specified that the various means used in the embodiment as described above, such as modules of different functions or logic circuits, are known in themselves and may be made, for example, based on elements. like those who are in commerce under the

blarque "ALT.ERA".

Claims (13)

  A logic device for centralized management of a plurality of elements to be managed (23, 24, 25), characterized in that it comprises: a central management unit (1) comprising two first (2) and second ( 3) input-output lines capable of transmitting and receiving at least data messages comprising an address, control input means (4), a plurality of signal repeater means (5, 6, 7), each of the repeater means comprising two first (8, 9, 10) and second (11, 12, 13) input-output terminals and branch input-output means (14, 15, 16) of said signals, said repeater means being connected in series between their first (8, 9, 10) and second (11, 12, 13) input-output terminals respectively to form a ring management circuit (17) between two ends (18, 19). ), the two said ends being respectively connected to the two first (2) and second (3) input-output lines of said unit plant (1), and a plurality of controllable automatic addressing means (20, 21, 22), each connecting means input-output shunt (14, 15, 16)   repeater means (5, 6, 7) to an element to be managed (23, 24, 25).   2. Device according to claim 1, characterized in that   said controllable automatic addressing means (20, 21, 22) are initialized so that the addresses for identifying the elements to be managed have increasing values in chronological order of said repeater means (5, 6, 7) on said ring management circuit (17) in the direction of rotation from the first input-output line (2) to the second line input-output (3).   3. Device according to one of claims 1 and 2, characterized by the   said repeater means (5) comprise: a first input-output terminal (8) consisting of a first transmitter (30) and a first receiver (31), a second input-output terminal (11); ) constituted by a second transmitter (32) and a second receiver (33), said first and second transmitters (30,32) being connected, through respectively first and second multiplexers (36,37), to a control logic ( 34) of which bypass inputs (35) belonging to the input-output means (14) are able to receive signals transmitted by said addressing means (20), a first dressing module (38) including an output is connected to an input of the first multiplexer (36) and whose other output is able to be connected, through a first logic gate (39), to said addressing means (20), the inputs of said first dressing module ( 38) being connected to an output of said control logic (34) and an output of the addressing means (20), a second cladding module (40) having an output connected to the second emitter (32) through the second multiplexer (37) and another output of which is connected to said addressing means (20) through said second first logic gate (39), the inputs of said second cladding module (40) being respectively connected to an output of the control logic (34) and to an output of the addressing means (20), and at the output two first and second receivers (31,33), first and second receiver logic modules (50,51) whose inputs and outputs are respectively connected to said control logic (34) and the addressing means (20) to through two second and third logical gates (41,42).   4. Device according to one of claims 1 to 3, characterized by the   said addressing means (20) comprises: a reception processing module (43) whose inputs are suitable   to be connected to bypass outlets (55) belonging to the input means-   output (14) and whose outputs are respectively connected to inputs of a first comparator (44) and control inputs of a first address extractor (45), an address memory (46) whose control inputs (47) are connected to the outputs of said first comparator (44) through said first address extractor (45), the outputs of said address memory (46) being respectively connected to the control inputs of a module transmission processor (48) whose outputs are connectable to bypass inputs (54) belonging to the input-output means (14) and to inputs of a state-building module signals (49), said elaboration module   the state of the signals (49) being also connected to said first comparator (44).   5. Device according to one of claims 1 to 4, characterized by the   said central management unit (1) comprises: a central management logic module (60) with two first and second input-outputs (61, 71), the first input-output (61) being connected to a third transmitter output (62) through a first transmit processing module (63) and to a third receiver (64) through a first receive processing module (65), the second input-output (71) being connected to a fourth output transmitter (72) through a second transmission processing module (73) and a fourth receiver (74) through a second reception processing module (75), an interface module (81), a maintenance and error module (82), an application interface module (83) and an exchange memory module (84), and a first bus line (80) connecting these last four modules and the inputs (88, 89) from said central management logic module (60) through a   control module (90) and an exchange memory interface module (91).   6. Device according to claim 5, characterized in that said exchange memory module (84) comprises two parts, a part "data" and a "frame" part.   7. Device according to one of claims 5 and 6, characterized by the   said central management logic module (60) comprises at least means for automatically defining the direction of propagation of said messages   in said ring management circuit (17).   8. Device according to claim 7, characterized in that said means for automatically defining the direction of propagation of said messages in said ring management circuit (17) comprise, from a second bus (103) able to convey said messages, a second address extraction module (104) whose output is connected to a first input (105) of a second comparator (106) whose other input (107) is connected to an output (108) an analysis and control module (109) capable of delivering a reference value to this output (108), said second comparator (106) being capable of delivering on its two outputs (110, 111) two types of signals according to whether the addresses of the messages applied to its input (105) are   less than, greater than or equal to, a so-called "break" address value.   9. Device according to one of claims 5 to 8, characterized by the   said central management logic module (60) comprises at least burst means (137), concatenation means (131) and association means (133, 134, 135, 140, 141) cooperating with said burst means and concatenation.   10. Device according to claim 9, characterized in that said burst means (137) break down "n" elementary bits z consecutive whose rank in the message is "modulo n" in "n" information   which can be stored in said exchange memory module (84).   11. Device according to claim 10, characterized in that said bursting means (137) comprises a first received data storage module (161) whose input (162) is connected to a third data bus (163). ) constituting the input of said burst means, said first received data storage module (161) consisting of a first set of "n" flip-flops (164), the output (165) of said first storage module receiving data (161) being connected to the inputs (166, 167), respectively of a first module operating in transparent mode (168) and a first module operating in Boolean mode (169), the outputs (170, 171). both of said last modules (168,169) being connected to a fourth output data bus (172) constituting the output (138) of said burst means (137), both so-called first transparent mode modules (168) and Boolean mode (169) being controlled at from a first management module (173) synchronized and controlled from a first logic counter (174).   12. Device according to claim 9, characterized in that said concatenation means (131) collect "n" information contained in said exchange memory module (84) in "n" elementary bits whose   rank in a message is "modulo n".   13. Device according to claim 12, characterized in that said concatenation means (131) comprise a fifth data bus (150) constituting the input (132) of these concatenation means, a second module acting in transparent mode ( 151) and a second module operating in Boolean mode (152), said two latter modules (151, 152) being connected in parallel to said fifth bus (1 50), their respective outputs (153, 154) being connected to the input (155) of a second data storage module (156), said second data storage module consisting of a second set of "n" flip-flops (157), the output (158) of said second module data storage device (156) constituting the output (134) of said concatenation means (131), both said second transparent mode (151) and Boolean mode (152) modules being controlled from a second management module (159) synchronized and controlled   from a second logic counter (160).