FR2693295A1 - Gaming machine including continuously operating timer - Google Patents

Abstract

The system has a timer consisting of an oscillator(10,12) which is coupled to a counter divider(15) with reader(30) access, so as to prevent falsification of data. The circuit is in encapsulated form and has an access protection circuit(50) which is connected between the access and the counter divider. In addition, a supervisory circuit(100,50) can be added to monitor the oscillator frequency.

Description

"Clock circuit for gaming device".

Description

  The present invention relates to a clock circuit

  for game device in particular, formed by an oscillator-

  clock frequency generator coupled to a counter circuit

  divider. This kind of circuit is well known and finds

important applications.

  However, there are certain applications where new requirements are imposed, in particular in the field of games. On this subject, we can consult the patent.

US 5,073,931.

  In this patent, players are offered a device which makes it possible to record bets on the outcome of an event which takes place before their eyes. The timing of the bet cannot therefore be later than this outcome If the amount of the 'stake is important, such a device risks being prey to frauds In particular it is important that the time of the bet is not falsified; a dishonest player may try to affect a time prior to his bet, when he has done so

knowing the outcome of the Game.

  The invention therefore provides a clock circuit which has

  for the purpose of opposing this kind of fraud.

  For this, such a circuit is remarkable in that it is integrated and that it is provided with a safety circuit.

  which protects its output data.

  The following description, accompanied by the drawings

  attached, all given by way of non-limiting example, will

  fully understand how the invention can be realized.

  Figure 1 shows the circuit diagram according to the invention. Figure 2 shows a variation of the circuit

according to the invention.

  The clock circuit proposed by the invention bears, in FIG. 1, the reference 1 It essentially consists of an oscillator 10 controlled by a quartz 12 and by a counter-divider 15 These components can be part of an integrated circuit 20 of the kind registered under the no PCF 8583 The content of this counter-divider provides various date information to a RAM memory 22 addressed by an addressing device 24 This output information is the year, the month, the day, the hours, minutes, seconds, etc. Other information can be contained in this memory: alarm, status information, etc. The information contained in this memory can be read on a line 26 connected to its output An interface allows communication of the 12 C type to the outside of the circuit 20 A logic member 32 makes it possible to control the entire operation of this circuit 20 This circuit 20 is supplied by

  a voltage applied to a terminal 33.

  In accordance with the invention, to prevent the information produced by this circuit 20 from being falsified, an integrated safety circuit 50 has been provided, in hybrid form

  or not, on the same substrate as circuit 20.

  Integration prevents intervention from taking place inside circuit 1 This integration can be accompanied by coating of the entire circuit, which makes

  any intrusion even more unlikely.

  The safety circuit is for example constituted by a circuit of the kind registered under the MC 6805 SC 24 This circuit is formed by a microprocessor 55 to which are attached a RAM memory 57, a ROM memory 59 which contains the operating instructions microprocessor 55 and also an EEPROM memory 61 which can contain various data which cannot be erased by cutting off

food.

  This circuit is usually used in smart cards of the kind described in the book

MICROCIRCUIT CARDS

TECHNIQUES AND APPLICATIONS

by F GUEZ, C ROBERT and A LAURET

  published in France by MASSON editions.

  To communicate, this circuit includes a set of accesses 65 and 66 of which a part 65 is assigned to communications inside the circuit 1 and the other part 66

  communications to the outside.

  According to a first embodiment, circuit 1 is supplied by two voltage sources 70 and 72 via two supply terminals 73 and 74 La

  source 72 is provided for supplying circuit 20 only.

  According to a second embodiment, circuit 1

  is supplied by the same two voltage terminals 70 and 72.

  But, preferably, it is the source 70 which supplies the circuits, even the circuit 20. If this source manifests a failure, this is detected by a supply voltage analyzer 80 (FIG. 2) which, in this case, connects a voltage switch 82 so that the circuit 20 is supplied

by the voltage source 70.

  The advantage of these measures is that we can guarantee a certain autonomy of this clock circuit (a few years given its low consumption) while powering the environment for which it works may require

  several battery changes (source 70).

  However, if the circuit supply voltage is interrupted, this is detected by another

  voltage analyzer 83 connected to the supply terminal 33.

  The voltage breakdown information can be reflected by the state of the data contained in the memory 22 The state of this supply voltage can also be analyzed by the circuit 50 by communicating to it the detection made by

  the analyzer 83 during its accesses I 2 C to circuit 20.

  To allow communication between this bus and the

  safety circuit 50, an interface circuit 90 has been provided.

  The program ensures communication on this bus while respecting the protocol defined by the measures relating to the I 2 C bus. Information concerning the clock is made accessible via circuit 50 on an access 92 Circuit 1 carries, in addition to the terminals d 73 and 74, two other accesses 94 and 96 for, respectively, the re-initialization of the circuit and the application of the clock signals necessary for

processor 55.

  The circuit 50 operates, according to a mode of

  preferential operation, according to the encryption algorithm-

  DES decryption, as defined, for example, in the publication: Federal Information Processing Standards Publication (FIPS PUB 46) of January 15, 1977 of the National Standards Bureau of the United States Department of Commerce. In the EEPROM memory is recorded an encryption key C. Thus, at access 92 the date DAT can be in clear, but it is accompanied by a DES code (C, DAT) Thus, one can verify the integrity of this date DAT, if of course we know C, every precaution being taken so that this key C

  remains unknown to any potential fraudster.

  It is possible to complicate the process by sending to the clock circuit 1 a random "a", so that the

  date is accompanied by a DES code (C, a, DAT).

Claims (4)

Claims i Clock circuit for a game device in particular, formed by an oscillator-generator of clock frequency coupled to a counter-divider circuit provided with read access, characterized in that this circuit is in the form of a protected housing, in that there is a protected access circuit connected between said accesses and the counter-divider circuit. 2 clock circuit according to claim 1, characterized in that the protected housing is produced by the integration of the entire clock circuit.   3 clock circuit according to claim 1, characterized in that the protected housing is produced by the hybrid integration of components available in the trade.   4 clock circuit according to one of claims i   to 3, characterized in that the protected access circuit is a smart card circuit.   Clock circuit according to claim 4 I, characterized in that the chip card circuit implements the DES algorithm.   6 Clock circuit according to one of claims 1.   to 5, characterized in that it includes a supply voltage presence detection circuit for supplying supply voltage interruption information if it occurs.   7 clock circuit according to one of claims i   to 6 characterized in that it comprises two terminals the oscillator and its associated counter circuit, when the other is failing.