FR2657475A1 - DIGITAL OSCILLATOR FOR OBTAINING A SIGNAL WITH A FREQUENCY THAT CAN BE CONTROLLED. - Google Patents

Abstract

a) Digital oscillator to obtain a signal with a frequency that can be controlled. b) digital oscillator characterized in that the carry signal (C) is capable of being delayed by a time depending on the corresponding content (O) of the accumulator. c) the invention relates to digital oscillators for obtaining signals with a frequency capable of being controlled.

Description

"Digital oscillator to get a signal with a

  frequency likely to be ordered ".

  The invention starts from a digital oscillator to obtain a signal with a frequency which can be controlled, an oscillator in which pulses of a reference rate can be applied to an accumulator which, after each impulse of the reference rate, is incremented by a predefined number of values of

  counting and who, when a predefined content is

  dyes, delivers a carry signal.

  In the field of communication technology,

  cations, oscillators are often needed whose frequency is likely to be controlled using

  of signals applied to these oscillators.

  are frequently used in

  frequency and phase control loops.

  Beside other oscillators likely

  to be ordered, such as for example oscilla-

  LC (Inductance-Capacitance) capacitors and RC oscillators,

  (Capacity Decrease) we know nu-

  These include an accumulator whose content is increased by a value that can be

  preset (increment) for each pulse of a

  dence of reference At the exit of carry

  then a signal that for an appropriate choice of

  capacitance of the accumulator and for an appropriate choice of the respectively predefined increment N, corresponds to

  a fraction of the frequency of reference

  In a similar way, the corresponding content of

  the battery can also be operated.

  Compared to LC and RC oscillators, digital oscillators have the advantage of high frequency constancy, since in general the reference rate is obtained with a quartz oscillator.

  the advantage of a greater range of variations.

  Known numerical oscillators have, however,

  the disadvantage that the carry-over signal is

  fluctuations in time (jitter)

  the known circuit devices are limited in

  regard to the relationship between the frequency of

  obtained and the frequency of the reference

this.

  The object of the present invention is to

  ask a digital oscillator to obtain

  whose frequency is likely to be

  mandated and whose fluctuations in time (jitter)

  be as small as possible.

  For this purpose, the oscillator conforms to the in-

  The invention is characterized in that the carry signal is capable of being delayed by a time dependent on the

  corresponding content of the accumulator.

  The digital oscillator according to the invention

  has the advantage that fluctuations in

  time can be avoided with reduced expense.

  In addition, the digital oscillator can take

  simple arrangements to widen the frequency zone

quence of the signal obtained.

  The signals produced by the digital oscillator

  according to the invention are, for the most part, used as synchronization signals for other digital circuits, for example in the video technique. In view of other applications and to differentiate them from the reference rate, the signals produced by the compliant digital oscillator

  to the invention will be in the following only

ignored by the term signals.

  Thanks to other characteristics of the

  vention, advantageous supplements and improvements

  of the invention indicated above are possible.

  ble. Thus, according to one characteristic of the invention, a transfer output of the accumulator is connected to the input of a switching delay device, and in that an output of

  accumulator, which represents the contents of the accumu-

  is connected to a control input of the device.

temporizing system.

  According to another characteristic of the invention

  a calculation circuit is arranged between the output

  of the accumulator and the control input of the

time delay.

  According to another characteristic of the invention

  an entry for the number of

  This input is connected, on the one hand, to the accumulator, and, on the other hand, to the calculation circuit.

  According to another characteristic of the invention

  a limiter is placed between the exit of the

  accumulator and the control input of the device of

  time delay that can be controlled.

  According to another characteristic of the invention

  at the output of the battery is connected

  register D which is synchronized by the signal of re-

Harbor.

  According to another characteristic of the invention

  the transfer signal is logically combined with

  the pulses of the reference rate.

  According to yet another characteristic of

  the invention, an AND circuit is provided between the output

  transfer of the accumulator and the device

  time delay that can be controlled.

  Finally, according to another characteristic of the invention, a passband filter is connected to the

  following the delay device likely to

to be ordered.

  Exemplary embodiments of the invention

  are shown in the drawings using several

  and will be explained in more detail in the

hereinafter.

  FIG. 1 is a block diagram of a known digital oscillator,

  Figure 2 shows diagrams according to

  time to explain the defects of the oscilla-

  FIG. 3 is a block diagram of a first exemplary embodiment, FIG. 4 is a block diagram of a second exemplary embodiment,

  Figure 5 shows diagrams according to

  time to explain the second example of

  realization. Identical parts are assigned

  same references in the figures.

  In the case of the known digital oscillator according to FIG. 1, there is provided a battery 1 whose synchronization input 2 is likely to be

  fed by a reference rate T with the frequency

  quence f R A magnitude N is likely to be ap-

  plicated to an entry 3 The contents of the accumulator 1

  is incremented by N for each pulse T of syn-

  A signal O corresponding to the contents of the accumulator can be taken from an output 4. In addition, another output 5 delivers a signal C, hereinafter referred to as a carry signal, which then comes to the level H

  when there is an overflow in the accu-

  emulator. The operation of the circuit device according to FIG. 1 will be explained by means of the diagram as a function of time in FIG. 2a. Suppose, in this case, that the accumulator comprises four binary digits so that it can take sixteen states, and that in addition, N equals 4 Figure 2a shows the

  respective content of the accumulator between two

  the reference rate T and shows the level

  of the transfer signal C During the period of time

  the contents of the accumulator is first incremented from 7 to 11 and for the next pulse to 15 When the next increment, the content

  accumulator O = 3 is obtained, in which case there is

  passing of the capacity, and the carry signal C takes during the next synchronization period

  level H Because of the integer ratio

  the capacity of the accumulator 1 and the counting increment N, the output signal is a succession

  pulses with uniform intervals.

  If, however, to obtain another frequency

  quence, another increment is chosen, the transfer signal then comprises intervals or non-uniform periods, which is represented in the example of

N = 6 in Figure 2b.

  To complete the discussion of the operation of the known digital oscillator according to FIG. 1, reference is made to FIG. 2c. It is based on N = 7. A transfer signal C appears, in the example represented respectively after a passing of capacity for accumulator contents 0, 5, 3, 1, 6 and 4 In addition to the encrypted representation of the content O of the accumulator, this content is represented graphically in FIG. 2 c. , as a sawtooth function, a signal of the frequency corresponding to the desired frequency f 0 of the signal to be obtained In the form of rectangles more or less wide, is represented the

  difference in teeth between the rising flanks of the

  Figure C and the rising edges of the signal SO to obtain On another line of Figure 2c, is in

  additionally represented the respective content O O after the de-

capacity pass.

  In the case of the digital oscillator con-

  form of the invention, the correlation specified at the end of

  2 c between the contents of the accumulator after the overflow and the time difference is used, then dt = O / N in many

  case of application, a good approximation is

  possible with approximately O / 8.

  The exemplary embodiment according to FIG. 3, comprises an accumulator 1 with inputs 2, 3 and

  outputs 4, 5, as already described in

  relationship with Figure 1 A computing circuit 12 is

  connected to output 4 via a regis-

  In addition, from an entry 13 of the provi-

  In FIG. 3, the value N is brought not only to the input 3 of the accumulator, but also to another input of the calculation circuit 12. The transfer output 5 of the accumulator 1 is on the one hand, connected to the synchronization input of the register D 11 and, on the other hand, to the input of a timing chain 14 The timing chain

  14 consists of eight elements The output of each

  that element being connected to an input of a multi-

  plexeur 15, whose output 16 constitutes the output of the circuit device The timing chain 14 and the multiplexer 15 constitute a device for

  time delay that can be controlled, thanks to-

  which the signals applied to the input 17 are delayed as a function of control signals which apply to

the order entry 18.

  With register D 11, the content O of the ac-

  accumulator is stored from the pulse of the

  report at any given time, up to

  the next impetus In accordance with the indi-

  above, the value dt is calculated from

  OO and N in the computing circuit 12, and the multi-

  plexeur 15 is set correspondingly Thus,

  the difference in time possibly existing

  The delay signal C is compensated, so that the signal SO at the output 16 is free of fluctuations in the

time (jitter).

  If the frequency f O needs to be modified

  only in a relatively small area, the

  Variation tensile of N is also limited, for example 7 <N '9 In this case, the calculation circuit can be replaced by a simple limiting circuit 22, which limits 00 to the range 0 to 7, which is

  represented inter alia in Figure 4.

  Two complements of the invention will be further exposed with the help of Figure 4 On the one hand, an AND circuit 21 is disposed on the path of the transfer signal C between the output 5 of the accumulator 1 and

  the input of the timing chain 14, circuit

  In addition, the output of the multiplexer 15 is connected via a bandpass filter.

23 at the exit 24.

  The advantages that can be obtained by the AND circuit 21 are represented below, with the aid of an encrypted example according to FIG.

  in the examples according to Figure 2, it is assumed that

  accumulator with 4 binary digits for an increment of N = 12 This value has the consequence, in the case of the embodiment according to FIG.

  the same frequency ratio as the value N = 8,

  see f O = 1/4 f R For N 2 8 the frequency of the carry signal C lowers again The maximum frequency is for a four-digit accumulator

at N = 8.

  Thanks to the introduction of the ET 21 circuit (

  4), a further increase in the frequency of

  signal 50 product is however possible in the re-

  presented in Figure 5, the capacity of the accumula-

  is exceeded for N = 12 for three successive periods of the reference rate T, namely when changing the content O of the accumulator to 11, 11 to 7, and 7 to 3 During this time, the

  signal C includes level H A combination of

  its AND with the reference rate T provides a

  gnal C * whose average frequency is 3/4 of the frequency f R of the synchronization signal For N <8, the circuit ET simply ensures a shortening of the signal of transfer C In general, one has for the frequency of the signal C * : f O * = (N / 16) f R for N = O

  16 The phase correction of the signal C * is effected

  kills in the same way, using the time

  can be ordered, that in the example

  embodiment according to FIG.

  Another addition to the invention makes it possible, in addition, to obtain a signal with a frequency higher than f 0. For this purpose, a bandpass filter 23 is connected after the multiplexer 15, a signal

  with a frequency f O = 2 (N / 16) f R being able to

  tible to be taken at the output 24 of this filter This signal represents the second harmonic of the signal 50

  with the frequency fo This can be achieved by

  a simple analog bandpass filter

  second order, from the signal SO instead of se-

  harmonic cond, it is also possible, with an appropriately sized bandpass filter, to obtain

  the third harmonic of the signal SO.

  When using a pass filter

  second-order band which is essentially

  staged by two oscillating circuits, a range of

  frequency of 1000 ppm or 0.1%

  is possible in all cases for a lowering

  multi-line additional lines of at least 40 d B. In the case of the numerical examples, it has been assumed for the sake of clarity, a four-fold

  binary digits For sufficient ventilation

  particularly fine, it can be expected that a

  larger number of binary digits.

  emulator can be easily realized with a 16-digit ALU, which is arranged on a chip The other digital functions of the circuit device

  according to Figure 4, can be integrated by a cir-

  programmable logic (PAL) on a second chip.

  In conjunction with the timing chain and the

  band-pass filter, we then have four building blocks

tive.

Claims (9)

  1. Digital oscillator to get a   signal with a frequency likely to be   an oscillator in which impulses of a   reference may be applied to an accumulator, which, after each pulse of the   reference rate, is incremented by a number   can be predefined counting values and which, when a predefined content is reached, delivers a transfer signal, digital oscillator characterized   in that the carry signal (C) is capable of being   delayed by a time dependent on the content (O) cor- respondent of the accumulator.   2. Digital oscillator according to the   cation 1, characterized in that a transfer output (5) of the accumulator (1) is connected to the input of a   delay device (14, 15) capable of   be switched, and that an output (4) of the accumula-   the battery (1), which represents the contents of the accumulator, is connected to a control input (18) of the device timing (14, 15).   3. Digital oscillator according to the   cation 2, characterized in that a calculating circuit (12) is arranged between the output of the accumulator (1)   and the control input (18) of the timer device tion (14, 15).   4. Digital oscillator according to the   cation 3, characterized in that an input is provided   (13) for the number likely to be predefined, this   the input being connected, on the one hand, to the accumulator   (1) and, on the other hand, to the computing circuit (12).   5. Digital oscillator according to the   cation 2, characterized in that a limiter (22) is arranged between the outlet (4) of the accumulator (1) and   the control input (18) of the delay device   tion (14, 15) which can be controlled.   6. Digital oscillator according to the   cation 2, characterized in that at the output (4) of the accumulator (1) is connected a register D (11) which is synchronized by the transfer signal (C).   7. Digital oscillator according to the   cation 1, characterized in that the transfer signal (C) is logically combined with the pulses of the reference rate (T).   8 Digital oscillator according to the   cation 2, characterized in that a circuit is provided   AND (21) between the carry out (5) of the accumula-   (1) and the delay device (14, 15) likely to be ordered.   9 Digital oscillator according to the   cation 2, characterized in that a bandpass filter   (23) is connected as a result of the delay device   tion (14, 15) that can be controlled.