FR2646541A1 - High-speed bus - Google Patents

Abstract

The subject of the invention is a high-speed bus linking transmitters/receivers 50 each including outputs or inputs 80. This bus includes bidirectional lines 20 for transmission of operating commands in parallel and means 30 for connection of the outputs or inputs 80 of the transmitters/receivers 50 in parallel to the command lines 20. According to the invention, the bus includes two lines 90, 91 each forming a single-directional closed loop for serial transmission respectively of the addresses and of the data; the bus also includes a common clock 95; H2 and an open, single-directional line 96 for transmission of clock signals; finally the bus includes relays 94; Ri, associated with each transmitter/receiver 50, cutting the two loops 90, 91 and traversed by the open line 96 and connecting these lines 90, 91, 96 to the outputs or inputs 80 of the transmitters/receivers 50.

Description

FAST BUS
The subject of the present invention is a fast bus having a flow rate greater than that of known buses while occupying a substantially equivalent volume.

 As is known, a computer comprises on the one hand a certain number of organs and on the other hand communication channels between these organs. These bodies are for example processors, memories, or input-output circuits.

An organ sending a communication is qualified as transmitter, while an organ receiving a communication is qualified as receiver. In practice, each member is capable of being a transmitter or receiver and is qualified as a transmitter / receiver in the following. These communication channels are called buses. Physically, transceivers and buses are located on printed circuits. According to a geometry conventionally used, the bus is produced on a printed circuit called "backplane" on which there are connectors, while the various transmitters / receivers are located on printed circuits substantially perpendicular to the printed backplane circuit simply perpendiculars in what follows, one side of which is plugged into said connectors.

 Current processors are very fast and the operating speed of a computer is often limited by the speed of information transmission on the buses.

To take advantage of the performance of processors, it is therefore essential to make very fast buses whose speed does not slow down the computer.

 As is known, a bus has a number of two-way and parallel channels for the transmission of addresses, data, operating commands, and if necessary signals for synchronization of the different clocks which can be installed on each of the perpendicular printed circuits.

These routes are called the bus lines. Physically, these are transmission lines produced on the backplane printed circuit and which connect the connectors intended to receive the perpendicular printed circuits. Each transceiver has a plurality of outputs or inputs which are respectively connected in parallel to the bus lines, the number of which is equal to that of the outputs or inputs of each of these transceivers.

 In other words, any of the transmitters / receivers can play the role of a transmitter and communicate with any of the other transmitters / receivers playing the role of a receiver. The parallel link obtained between the different transmitters / receivers is called N to N, where N is the number of transmitters / receivers.

 The frequency of the signals propagating on such a bus is limited.

In fact, to allow correct transmission, without degradation of the signals, on a bus line, the impedance of the backplane printed circuit must be as high as possible. However, this impedance is lowered by the connection of the transmitters / receivers on the bus, within the framework of an N to
N, and the characteristics of standard printed circuits do not compensate for this weakening of impedance.

This degradation of the signals is all the more critical the higher the frequency of the signals transmitted, which sets an upper limit for this frequency.

 In addition, the higher the frequency of the signals transmitted on a synchronous bus, the more the synchronization between the different clocks established on the perpendicular printed circuits: it is considered in practice that above a certain frequency, the clocks are no longer synchronized.

 The invention relates to a bus which overcomes the obstacles set out in the above and overcomes the disadvantages of known buses. To this end, the invention provides for replacing the two-way lines for the parallel transmission of addresses and data by a first line and by a second line respectively for the serial transmission of addresses and that of the data, these first and second lines each forming a closed one-way transmission loop; the invention also provides for replacing any clocks installed on the perpendicular printed circuits with at least one common clock and with at least one third line for the transmission of clock signals, this third line being open and one-way transmission; finally, the invention further provides relays cutting the first and second lines and crossed by the third line, ensuring the connection between on the one hand the outputs or inputs of the transmitters / receivers and on the other hand the first, the second and the third line.

The invention more specifically relates to a fast bus connecting a plurality of transmitters / receivers each comprising a plurality of outputs or inputs, the bus comprising
- two-way lines for parallel transmission of operating commands,
means for connecting said outputs or inputs to the control lines in parallel, the bus being characterized in that it further comprises
- a first line forming a closed, one-way loop for the serial transmission of addresses,
- a second line forming a closed, one-way loop for the serial transmission of the data,
- at least one first common clock,
- at least one third open and one-way line for the transmission of the signals of the first common clock,
- Relays associated with each transmitter / receiver cutting said first and second lines and crossed by the third line, ensuring the connection of said outputs or inputs to the first, second and third lines.

 The N to N link of the known buses is thus replaced by a so-called point-to-point link between the different relays.

 Such a point-to-point connection does not cause the impedance of the backplane printed circuit to drop, which makes it possible, while using standard printed circuits, to propagate signals over the bus at a high frequency without requiring significant currents on the part of the transmitter nor cause degradation of the signals transmitted.

 Furthermore, the bus according to the invention comprises at least one common clock whose signals follow the same path as the addresses and the data; the addresses, the data and the clock signals therefore remain synchronized whatever the propagation frequency on the bus.

The invention will be better understood on reading the following description made using the appended figures which represent
FIG. 1, part of a known bus,
FIG. 2, another part of a known bus,
FIG. 3, the structure of a known bus,
FIG. 4, an embodiment of a bus according to the invention,
FIG. 5, an illustration of the operation of the bus of FIG. 4,
FIG. 6, an embodiment of part of a relay of the bus of FIG. 4,
FIG. 7, an illustration of a writing cycle of a first variant of the bus of FIG. 4,
FIG. 8, an illustration of a reading cycle of a first variant of the bus of FIG. 4,
FIG. 9, an illustration of a writing cycle of a second variant of the bus of FIG. 4,
- Figure 10, an illustration of a read cycle of a second variant of the bus of Figure 4.

 - Figure 11, an embodiment of a bus relay of Figure 4.

 In these different figures, on the one hand the actual proportions are not respected and on the other hand the same references relate to the same elements.

 Figures 1 to 3 illustrate the configuration of a known bus.

 Figure 1 shows a portion of a backplane 1 printed circuit, on which lines 2 of the bus are made.

These lines are connected to connectors 3 intended to receive perpendicular printed circuits 4 on which are located in particular the transmitters / receivers which communicate via the bus.

 Figure 2 shows schematically one of the perpendicular printed circuits 4 comprising a transmitter / receiver 5. One of the sides 6 of this printed circuit 4 is intended to be plugged into a connector 3. For this purpose, this side 6 has zones 7 connected to the outputs or inputs 8 of the transmitter / receiver 5.

 FIG. 3 represents a section of the known bus. There are n parallel lines of the bus, and each of the transceivers 5 has n outputs or inputs 8. The connectors 3 (not shown in this figure) connect in parallel the n outputs or inputs 8 of each transmitter / receiver 5 at n lines 2 of the bus.

 An embodiment of the bus which is the subject of the invention is shown in FIG. 4.

 This bus provides communication between transmitters / receivers 50. It includes lines 20 for the parallel transmission of operating commands; these lines are produced in the same way as the lines 2 of the known buses, they pass through connectors 30 which provide a connection between outputs or inputs 80 of the transceivers 50 and the lines 20 of the bus. In other words, the bus control lines constitute an N to N link of the transceivers 50, where N is the number of transceivers 50.

 For the transmission of addresses and data, the bus according to the described embodiment of the invention also includes a line 90 forming a closed one-way loop for the serial transmission of addresses and a line 91 also forming a loop closed and also one-way for serial data transmission. The two lines 90 and 91 ensure signal transmissions in the same direction; this direction is indicated by the arrows 93.

These lines 90 and 91 are cut by relays 94 denoted R1, R2, R3, ... RN. These relays Ri have in particular the function of ensuring a connection between the outputs or inputs 80 of the transmitters / receivers 50 and respectively the transmission loop 90 of the addresses and that 91 of the data, while converting signals - parallel into signals - serial and vice versa
The bus also includes a clock 95, denoted H2 in the following, for serializing addresses and data.

This clock H2 is common to all the relays Ri and it is directly connected to one of the relays, such as for example to the relay R1. This relay R1 is connected to all the others, in series, by a line 96 for the transmission of the clock signals.

This line 96 is a one-way transmission and therefore crosses the various relays. The clock signals therefore follow the same path as addresses or data propagating from the relay R1 to the relay RN.

The bus according to the invention can be produced according to two variants: it can be synchronous or asynchronous. In the case where it is synchronous, it comprises a second clock 97, noted
H1 in the following, for synchronization of the read and write operations performed on the bus. This clock H1 is also common to all the relays; it is preferably directly connected to the same relay R1 as the clock H2 and this relay is connected to all the others, in series, by a line 98 analogous to line 96. In the case where the bus is asynchronous, it does not include not the H1 clock.

 FIG. 5 illustrates the effect of the selection of a transmitter R on the transmission loop 90 of addresses and that 91 of the data: these two loops are opened by this selection. The transmission lines 90 of the addresses and 91 of the data therefore form a loop from a structural point of view, but are open from a functional point of view, and the rupture of the loop occurs at a place which depends on the transmitter Rj chosen.

 Physically, the relays Ri are capable of being installed on the perpendicular printed circuits comprising the transmitters / receivers 50. The clocks H1 and H2 are installed on one of these printed circuits, as for example, according to the embodiment described, on the printed circuit comprising the relay R1.

 Figures 11 and 6 show the structure of a relay 94, Ri of the bus according to the invention.

As shown in FIG. 11, each relay 94,
Ri has two circuits 72 and 71, respectively denoted C a and Cd, respectively cutting the transmission loop 90 of the addresses and that 91 of the data. The line 96 for transmitting the signals from the clock H2 crosses the relay 94, Ri as follows: at the input of the relay 94, Ri, it separates at a bifurcation 70 into two sections 69 and 68 which pass through circuits 72, C a and 71, Cd respectively; at the output of relay 94, Ri, this line 96 is connected to any one of the two sections 69 or 68, such as for example to section 69; the end of the other section, that is to say the section 68 in the example chosen, is not used. Finally, in the case where the bus is synchronous, any of the circuits 72, 71 is crossed by the line 98 for transmitting the signals of the clock H1. By way of example, in FIG. 11, the line 98 crosses the circuit 72 cutting the transmission loop 90 of the addresses.

 FIG. 6 represents the structure of the circuit 72, C a cutting the transmission loop 90 of the addresses, crossed by the section 69 of the line 96 for transmission of the signals of the clock H2, and, according to the example chosen and for a synchronous bus, crossed by line 98 for transmitting signals from the clock H1.

If the transmitter / receiver connected to the relay comprising the circuit 72, C considered and noted (E / R) 1 in the following is not
has not actually been selected as transmitter (such a selection being transmitted by the bus control lines), the addresses propagating, in the direction indicated by the arrows 93 on the line 90, pass through the circuit 72, C a via the multiplexer 81. This multiplexer is in fact controlled by a signal 82 (supplied by the bus control lines) which is then placed in a first position such that the signals presented at the output 83 of the multiplexer 81 are those present at the input 84 of this multiplexer.

 If the transmitter / receiver (E / R) 1 is selected as the transmitter, the signal 82 is placed in a second position such that the signals presented at the output 83 of the multiplexer 81 are those present at input 85 of this multiplexer, this input 85 being connected to a transmitter block 86 of circuit 72, Ca This transmitter block 86 is connected by an input 87 to the output 80 of the designated transmitter (E / R) i for receiving addresses.

This address transmission is carried out after reception by the designated transmitter (E / R) 1 of a signal 79 (called "send data") sent by the transmitter block 86 and indicating that the latter is ready to receive addresses; this transmission of addresses is also validated by the sending, by the transmitter (E / R) 1 to the transmitter block 86, of a signal 88. The transmitter block 86 can then serialize the addresses received by means clock signals
H2 which are introduced into this block by an input 89. In a manner known to those skilled in the art, the transmitter block ensures parallel-series conversion with biphase coding by delimiting the packet of bits corresponding to the word by a mark of the start type -Stop.The recognition of this brand ensures synchronization by word. Such a conversion is for example described in the publication by N. MRABET, G. NOGUEZ, D.

TRECOURT, entitled: "Very high speed local area networks: the equivalent of the asynchronous transmission code" Start-Stop "n,
Proceeding of the international Conference on Performance of
Data Communication Systems and their Applications, PARIS,
FRANCE, September 14-16, 1981 (ENST-INRIA).

 If the transmitter / receiver (E / R) 1 is selected as the receiver, the addresses which are present at the input 78 of a receiver block 77 of the circuit 72, Ca, are introduced into this receiver block 77. These addresses are subject to then a series-parallel conversion; then the receiver block 77 signals their presence to the designated receiver (E / R) 1 by means of a signal 76 (called "take data"); these addresses are then sent via output 75 of receiver block 77, to input 80 of the designated receiver (E / R) 1. This series-to-parallel conversion is carried out, in a manner known to a person skilled in the art, with sampling of the signal by the signal itself delayed and does not require the use of the signals of the clock H2. Such a conversion is also described in the publication of N.

MRABET, G. NOGUEZ, D. TRECOURT, entitled: Very high speed local area networks: the equivalent of the asynchronous transmission code "start-stopt", Procreeding of the international
Conference on Performance of Data Communication Systems and
Their Applications, PARIS, FRANCE, September 14-16, 1981 (ENST-INRIA).

 Finally, the signals of the clock H2, and those of the clock H1 in the case of a synchronous bus, cross the circuit C a by passing through a buffer 74. This buffer ensures the reshaping and the amplification of these clock signals.

These are the amplified clock signals H2 (that is to say having passed through the buffer 74) which are sent to the input 89 of the transmitter block 86. On the other hand, in the case of a synchronous bus the signals of the clock H1 are sent, also after crossing the buffer 74, to the transmitter / receiver (E / R) i by a line 73.

cutting circuit 71, Cd cutting loop
The structure of the circuit 71, Cd transmission 91 of the data is similar to that of the circuit 72, Ca, except with regard to the section 69 which is replaced by the section 68, and with regard to the line 98 for transmission of the signals of the clock H1 and the line 73 going towards the transmitter / receiver (E / R) 1 connected to the relay comprising the circuits 72, Cl and 71, Cd considered: these lines 98 and 73 are useless in the circuit 71, Cd .To simplify the realization of circuits 72, C a and 71, Cd of relay 94, Ri, one can however manufacture two strictly identical circuits: in this case, circuit 71, Cd includes a transmission line similar to the portion of the line 98 which crosses circuit 72, C a and also includes a line similar to line 73 of circuit 72, Ca, but these two lines of circuit 71, Cd are not connected at the output of this circuit.

 The operation of circuit 71, Cd is deduced from that of circuit 72, C a by replacing the addresses with the data in the case of a write, and by further exchanging the roles of the designated transmitter and the designated receiver in the case of a reading.

 In order to obtain a maximum transmission frequency along the bus according to the invention, the circuits 72, C a and 71, Cd of each relay Ri are preferably made in AsGa technology with a VLSI integration ("very large scale integration") . For example, a circuit C a or Cd has about 2000 doors, consumes about 3.5 watts, can fit on a PGA ("Pin grid Array") of 64 pins, and occupies on a printed circuit the surface of four 20-pin MSI ("Medium Scale integration") circuits. According to the example chosen, the frequency obtained on the bus can reach approximately one gigabit per second. Knowing that the maximum frequencies obtained on buses of the known type, comprising a few tens of lines in parallel for the transmission of data or addresses, are of the order of a few tens of megabits per second and per line, the bus according to the invention makes it possible to gain an order of magnitude in frequency compared to known buses.

 Figures 7 and 8 correspond to a first variant of the bus according to an embodiment of the invention, namely in the case of a synchronous bus. FIG. 7 represents the transmitted signals brought into play during a write cycle, while FIG. 8 represents those brought into play during a read cycle. In the case of a synchronous bus, the read and write operations are in fact synchronized on the clock H1 of period T1.

T2 should be noted as the period of the serialization clock H2 of the addresses and of the data; we should also note e the maximum propagation time between a
p designated transmitter and a designated receiver, regardless of this designation; in other words e is the propagation time between
p the most distant potential transmitter and receiver, namely transmitter R. and receiver Rj # 1. With such notations, the maximum time required for the transmission of a p-bit word is equal to
Ct = 8 p + p .T2
The transmitters / receivers have no means of measuring this time Ct, they can only evaluate T11 the period of the clock Hî. So that there is no lost time, it is however advisable to synchronize the operations of reading and writing on C t. To do this, the period T1 of the clock H1 is chosen so that it is a sub-multiple of Ct.

In other words, we take
Ct = k T1
This integer k is chosen as a function of the reaction time of the transmitter alone in the case of a write and of that of the transmitter and of the receiver respectively in the case of a read.

 According to the example illustrated in FIG. 7, the integer k has been taken equal to 2, and it depends on the reaction time of the transmitter which is not necessarily the same for the addresses and for the data.

 According to the example illustrated in FIG. 8, the integer k has been taken equal to 4, and it depends on the reaction time of the transmitter for the addresses, that of the receiver for the data, and the choice that is made. made to transmit information in packets: a first reading cycle corresponding to address A1 and to data D1 and a second reading cycle corresponding to address A2 and to data D2 partially overlap. In this case, the three successive phases: sending of the address, access time to the receiver, return of the data can be pipelined in a manner known by a person skilled in the art.

 FIGS. 9 and 10 correspond to a second variant of the bus according to an embodiment of the invention, namely in the case of an asynchronous bus, and respectively represent the transmitted signals brought into play during a write cycle and those involved during a reading cycle. The transmission control signals, exchanged between the transmitter and the receiver, on this asynchronous bus, are integrated into the addresses and / or data and supplemented by an acknowledgment of receipt sent by the receiver to the transmitter in the case of 'a writing. These control signals are fully integrated with the addresses on the one hand and with the data on the other hand in the case of a reading.

 For a write, the transmitter sends an address, then a datum, and the receiver having recognized its address recovers the datum whose presence is signaled by signal 76 of the corresponding relay and then sends an acknowledgment of receipt to the transmitter.

 For reading, the transmitter sends only one address and the receiver returns the corresponding data which acts as acknowledgment of receipt.

Claims (8)

 1. Fast bus connecting a plurality of transmitters / receivers (50) each comprising a plurality of outputs or inputs (80), the bus comprising  - two-way lines (20) for parallel operation control transmission,  - Connection means (30) in parallel for said outputs or inputs (80) to the control lines (20), the bus being characterized in that it further comprises  - a first line (90) forming a closed, one-way loop for the serial transmission of addresses,  - a second line (91) forming a closed, one-way loop for the serial transmission of the data,  - at least a first common clock (95; H2) -,  - at least one third line (96) open and one-way for the transmission of the signals of the first common clock,  - Relays (94 ;; Ri) associated with each transmitter / receiver (50), cutting said first and second lines and crossed by the third line, ensuring the connection of said outputs or inputs (80) to the first, second and third lines .  2. Bus according to claim 1, characterized in that each relay (94; Ri) comprises two circuits (72, 71; cl, Cd) respectively cutting the first line - (90) and the second line (91), and in that the third line (96) separates at a bifurcation (70) into two parallel sections (69, 68) crossing respectively the two circuits (72, 71; Ca> Cd), one of the sections (69) being connected to the third line (96) leaving the relay (94; Ri) considered  3. Bus according to claim 2, characterized in that each of the two circuits (72; 71; C a ~ Cd) of the relay (94 Ri) comprises  - a transmitter block (86), a first input (87) of which is connected to the transmitter / receiver (50) associated with the relay (94; Ri) considered, receiving by a second input (89) the signals of the first clock common (95; H2), for serializing addresses or data from the transmitter / receiver (50) considered,  - A multiplexer (81), comprising an output (83) and two inputs (84, 85), the output (83) of this multiplexer (81) being connected to the line (90; 91) cut by the circuit (72; 71; Ca; Cd) considered and leaving the relay (94; Ri), a first input (85) of this multiplexer being connected to the output of the transmitter block (86), and the second input (84) of this multiplexer being connected to the line (90; 91) cut by the circuit (72; 71; C; Cd) considered and entering the relay (94; Ri),  - a receiver block (77), the input (78) of which is connected to the line (90; 91) cut by the circuit (72; 71; C a; Cd) considered and entering the relay (94; Ri), whose output (75) is connected to the transmitter / receiver (50) associated with the relay (94; King) considered, for the serial-parallel conversion of the addresses or data propagating on the line (90; 91) cut by the circuit (72; 71; Ca; Cd) considered.  4. Bus according to claim 3, characterized in that each of the circuits (71; 72; Ca; Cd) of the relay (94; Ri) further comprises a buffer (74) crossed by a section (69 68) of the third line (96) for shaping and amplifying the signals of the first common clock (95 H2) ~  5. Bus according to one of claims 1 to 4, characterized in that it further comprises a second common clock (97; H1) and a fourth line (98) open and one-way for the transmission of signals from the second common clock, the relays (94; R1> being crossed by this fourth line.  6. Bus according to claim 5, characterized in that the fourth line (98) crosses one of the circuits (72; 71;  Ca; Cd) of each relay (94; Ri ?.  7. Bus according to claim 6, characterized in that the fourth line (98) passes through the buffer (74) of the circuit (72; 71; Ca; Cd) which it crosses, this passage ensuring the shaping and amplification of the signals of the second common clock (97; H1).  8. Bus according to one of claims 5 to 7; characterized in that each relay (94; Ri) comprises means (73) for transmitting signals from the second common clock (97; H1) to the transmitter / receiver (50) associated with the relay (94; Ri) considered.