FR2644924A1 - Circuit for selecting a redundant column in an integrated memory with data column redundancy - Google Patents

Abstract

The invention relates to memories produced as an integrated circuit and more particularly to those which include redundant columns to replace defective columns. The invention resides in the fact that each routing circuit such as SCa, associated with a set Ea of columns is connected between the output conductors CSO, CS1 and CSa and the read-write circuits LE0 and LE1. The selection is obtained using the signals p0, p0 and p1, p1 supplied by the MPP circuit. Such an arrangement significantly reduces the number of circuits associated with the columns because the LE0 and LE1 circuits are used for the redundant columns in the event of a fault.

Description

SELECTION CIRCUIT OF A
REDUNDANT COLUMN IN AN INTEGRATED MEMORY
WITH REDUNDANCY OF DATA COLUMNS
The present invention relates to memories made in integrated circuit and, more particularly, in a memory of this type with redundancy of data columns, a circuit for selecting a redundant column.

The more the memories have a large capacity for storing information and the finer the integration technology, the more these memories are subject to manufacturing defects. Indeed, it is very difficult today to have a good manufacturing yield for memories of one megabit integrated on a silicon surface of one cm2. A single fault in a memory of one million cells leads to the disposal of the entire memory.

To increase the overall manufacturing yield, it has been proposed to use redundant memory networks, that is to say comprising more memory elements than is strictly necessary; in the event that one or more memory elements are defective, which is detected during the testing of the integrated circuit wafers, they are replaced by redundant elements so that the memory appears generally good and is not discarded. In this way, it is possible to recover memories comprising a limited number of faults.

A memory is organized in a matrix of rows and columns and it is on a column that the content of a cell is read which is at the intersection between this column and a row designated by a determined row address.

Depending on the types of faults that appear, either a defective row must be replaced by a redundant row, or a defective column by a redundant column.

The replacement of a defective row is generally easier to carry out because the space constraints due to the selection circuits to be added so that the replacement is transparent to the user are less severe.

The replacement of a defective column is more difficult than that of a row when the memory is organized in words of several bits because an entry address designates, on the one hand, a single determined row and, on the other share, a number of columns equal to the number of bits. Consequently, when a column is defective, all the columns corresponding to its address must be changed. Such a solution leads to the use of a large number of redundant columns with which the selection, read and write circuits are associated, hence a significant increase in the size not only at the level of the memory itself but also at the level peripheral circuits where the density of circuits is already very high.

In the French patent application filed by the applicant on February 24, 1987 under the number 87 02372, it was proposed an integrated memory with redundancy of data columns which is organized in a particular way. Figure 1 of the present request, which corresponds to the single figure of the aforementioned request, provides a better understanding of this organization. the memory is organized into y rows and k groups GO to G5 of p columns, k and p being different from the unit, each group corresponding to a respective input-output pad among k pads DO to D5. One column of each group GO to G5 can be linked to the corresponding pad DO to D5 to this group by selecting a column address common to all groups GO to G5.

the memory also has redundant columns
CRa a CRc to replace defective columns as well as column address storage elements (not shown> capable of memorizing the address of defective columns and a redundant column selection logic circuit CR1 coupled to the address storage elements column to select a redundant column when a faulty column address is applied to memory.

The k plots DO to D5 are distributed into m sets Ea to Ec of r plots DO, D1, m and p being different from the unit, and to each set Ea a Ec is associated at least one redundant column CRa to CRc.

MPP block position memory elements are provided for memorizing a block position corresponding to the group of columns in which a defective column is located, the memorized position being a position j among r possible positions of the set of blocks in which locates the plot considered.

A logic switching circuit (TO, T1, 10, 11, 20, 21, 30) is coupled to the MPP block memory elements to - authorize or inhibit the transmission of information
between the studs of the same position j of all
sets of plots and redundant columns
respective associated with each set Ea a Ec, - correlatively inhibit or authorize the transmission
information between position pads other than j
of all sets and groups of columns
corresponding to these studs.

The authorization and the corresponding inhibition is a function of the information memorized by the elements for memorizing the position of the MPP pad.

In the memory which has just been described, each redundant column is associated with a read amplifier ARa, ARb0..and a write control amplifier BRa, ... These amplifiers use an important place in that occupied by the circuits associated with the columns, that is to say in a part of the integrated circuit where the space available is very limited.

An object of the present invention is therefore to provide an integrated memory with redundancy of data columns of the type described in the aforementioned patent application but in which it is not necessary to associate with each redundant column a read amplifier and a write control amplifier.

Another object of the present invention is to provide a circuit for selecting the redundant column which makes it possible to dispense with the use of reading amplifiers and of writing control using the reading amplifiers and of control write associated with the defective column.

The invention therefore relates to a circuit for selecting a redundant column in an integrated memory with redundancy of data columns, said memory comprising - a network of memory elements organized in rows therein.
and k groups of p columns, k and p being different from
the unit, each group corresponding to a circuit
respective input-output or write-read from
k write-read circuits, one column from each
group can be connected to the circuit
of writing-reading corresponding to this group by
selection of a column address common to all
groups, - Redundant columns to replace columns
defective, - Column address memory elements
able to memorize the address of defective columns, - a logic circuit for selecting a redundant column
coupled with the address storage elements of
column to select a redundant column
when a faulty column address is
applied to memory, the k circuits
of writing-reading being divided into m sets of r
write-read circuits, m and r being different
of unity, and each set is associated with at least
a redundant column, - elements for memorizing a circuit position
write-read intended to memorize a position of the
write-read circuit corresponding to the group of
columns in which a defective column is located,
the memorized position being a position j among r
possible positions of the circuit assembly
write-read in which the circuit is located
write-read considered, and - a selection circuit coupled to the elements of
write-read circuit position memorization, characterized in that the selection circuit is associated with a set of write-read circuits and is connected between, on the one hand, the groups of columns of said set and the redundant columns associated with said set and, on the other hand, the write-read circuits.

The selection circuit is also characterized by the fact that it comprises a transistor per group of columns and r transistors per redundant column, said transistors being controlled by the signals supplied by the position-memorizing elements of the write-read circuit.

Other characteristics and advantages of the present invention will appear on reading the following description of a particular embodiment, said description being made in relation to the accompanying drawings in which: - Figure 1 is a diagram of the integrated memory with
redundancy of data columns as described in
the aforementioned patent application, and - Figure 2 is a diagram which shows, in addition to the memory
in Figure 1, the selection circuit according to the
present invention.

The diagrams of Figures 1 and 2 being identical except for the selection circuit, only one description of the common parts will be made.

To simplify this description, an exemplary embodiment has been chosen in which the parameters k, m and r defined above in the preamble have respective values.
k = 6
m = 3
r = 2
The memory therefore has six DO input-output pads,
D1, D2, D3, D4, D5 from which one can read and write information in the memory in the form of six-bit words.

The information is stored in a network of cells organized in y rows and k (k = 6) groups of p columns.

In the figure, the network proper has not been shown, and in particular not the rows and row addressing decoders which are conventional. Only groups of column conductors have been represented in syhEolic form, each group corresponding to a respective pad. The groups are designated by the references GO, G1, G2, G3, G4, G5.

Conventionally, a DC column decoder is provided; it receives a column A address and makes it possible to select a column from among p in each of the groups of p columns: the k columns of address A are selected simultaneously by the decoder DC. The figures show respective output conductors CSO, CS1, cS2, cS3, CS4 and CS5 for each of the column groups, which means that the application of an address A has the effect of connecting to each of these output conductors a determined column of the corresponding group.

The redundancy circuit has two parts, one of which is symbolically represented by the block CR1. This block is constituted in a known manner and comprises elements for memorizing addresses of defective columns, that is to say batteries of fuses blown at the time of the memory wafer test. This block has the following function: it receives address A and compares it with the information stored by the fuse banks. If there is a coincidence, it deactivates the output of the DC decoder and selects redundant columns instead. In other words, it prohibits the transmission of information between the output conductors CSO to CS5 and the columns of groups GO to G5, but it authorizes the transmission of information between the redundant columns, designated here by CRa, CRb, CRc, and respective output conductors CSa, CSb, CSc of these redundant columns.

More precisely, it will first be considered that there is only one possibility of repairing a defective column, and in this case, the block CR1 comprises a single battery of fuses allowing the location of the address of the column defective; the CRI block then selects all the existing redundant columns. It will be noted in this connection that there are not as many redundant columns here as input-output pads, but that does not change the conventional constitution of the circuit CR1 whose function is to designate all the redundant columns.

We will return later to the case where the circuit must allow the repair of several defective columns.

In the architecture presented in FIGS. 1 and 2, the input-output pads are distributed into m sets of r pads.

Here, DO, D1 form the first set; D2, D3 form the second set; D4, D5 form the third set.

To each set of plots is associated, on the one hand, a set of r groups of p columns and, on the other hand, a redundant column which can transparently replace any column of this set of groups.

 Here, to the set of pads DO, Dl are associated, on the one hand, the set Ea of the groups GO and Gl, which each include p columns and, on the other hand, the redundancy column CRa which can replace l any of the columns of the groups GO and Gl.

Similarly, to the set of pads D2, D3 are associated on the one hand, the set Eb of the groups of columns G2 and
G3, and, on the other hand, the redundant column CRb. Finally, to the set of pads D4, D5 correspond the set of groups G4, G5 and the redundant column CRc.

In each set of r plots (r = 2) we define a plot position among r.

Here, there are only two pads in each set, therefore only two possible pad positions which will be called position pO and position pi.

In the first set of two pads DO, D1, we will say that DO is the position pad pO and D1 the position pad pl. In the second set, we will say that D2 is the position pad pO and D3 the position pad pi.

Finally, in the third set, D4 is the position pad pO and D5 the position pad pi.

 When the wafer test is performed, if it detects that abnormal information appears and results from a column defect which can be repaired by replacing this column, not only do we locate the address A supplied to the decoder, but we also locates the pad on which an abnormal bit appears.

However, this pad is only identified by its "position in the set of r pads. In other words, in the example shown, instead of identifying that an abnormal bit has appeared on the pad D3 for example, we are satisfied with find that an abnormal bit has appeared on a pi position pad.

This information is stored in block position memory elements belonging to an MPP logic circuit. These elements consist of a battery of fuses. There are as many fuses as necessary to define a position among r. For two positions po and P1, a fuse is required. This fuse is blown during the edge test; the information it stores is used (such as the information stored in the fuses of the CRI circuit) during subsequent use of the memory.

In the example shown, the logic circuit MPP, which contains this fuse, has two output conductors identified by the same symbols which define the positions of the pad: the conductor pO has a logic state 1 if a defective bit has been detected at a position pO and a state O otherwise; the pi conductor has a logic state 1 if a defective bit has been detected at a pi position and a logic state O otherwise. Logical states 1 only appear under the control of circuit CR1 when a faulty column address A has been recognized by this circuit CR1; this is why a VAL connection has been shown between the circuit CR1 and the circuit MPP.

The logic states of the conductors pO and pi are applied as input signals to the switching circuits CAa and CAb in the case of the memory of FIG. 1 and to the switching circuits CA'a and CA'b in the case of the memory of FIG. 2, these latter circuits CA'a and CA'b constituting the specific part of the invention.

In the case of the selection circuit CAa of FIG. 1, associated with the assembly Ea, it includes, in a nested fashion, read amplifiers ARa, ALO and AL1, write control amplifiers BRa, BEO and
BE1, logic circuits 10, 11, 20, 21 and 30 and transistors TO, T1, Ta, T10 and T1.

In the case of the selection circuit CA'a of FIG. 2 associated with the assembly Ea, the read / write function is carried out in a conventional manner by circuits LEO and LE1 while the selection function is carried out by a circuit SCa connected between the output columns
CSa, SCO and CS1 and the LEO and LE1 circuits. In other words, the selection of the columns is carried out before entering the read / write circuits so as to connect the redundant column to the read / write circuit which is connected to the defective column. As a result, such an arrangement does not require the use of amplifiers associated with the redundant column.

the selection circuit SCa comprises the transistor TRO which is connected on the source side, to the output conductor
CSO of the GO group and, on the drain side, to the LEO circuit; it is controlled on its gate by the complementary signal pO.

It similarly includes the transistor TR1 which is connected, on the source side, to the output conductor CS1 of the group G1 and, on the drain side, to the circuit LE1; it is controlled on its grid by the complementary signal pi.

The complementary logic signals pO and pl are obtained by applying the signals pO and pl to inverters (not shown) which can be included in the MPP circuit.

It also includes a TROa transistor which is connected, on the source side, to the output conductor CSa of the redundant column and, on the drain side, to the drain of the TRO transistor: the TROa transistor is controlled on its gate by the po signal.

Similarly, it also includes a transistor
TRla which is controlled on its grid by the signal pi.

The operation of the selection circuit SCa is then as follows. If no column of groups GO and G1 is defective, pO and pl each have a logical state o which prohibits any transmission of information from the redundant column CRa to one or other of the circuits
LEO, LE1. On the other hand, the signals pO and pl are at logic level 1 and authorize the transmission of the information coming from the groups of columns GO and G1 to the read / write circuits LEO and LE1.

If an element of a column of the group GO is defective, the signal pO has a logic level 1 which authorizes the transmission of the information originating from the redundant column CRa to the circuit LEO. On the other hand, the signal pO has a logic level 0 # which prohibits any transmission of the information originating from the group of columns GO to the LEO circuit.

If an element of a column of group G1 is defective, the signal pl has a logic level 1 which authorizes the transmission of the information coming from the redundant column CRa to the circuit LE1.

On the other hand, the signal pl has a logic level O which prohibits any transmission of the information coming from the group of columns G1 column towards the circuit LE1.

The operation has been described in the case of a reading but it is clear that the same process takes place when writing information.

If only one redundant column is provided per set of columns Ea, only one defective column of the group
GO or group G1 can be replaced. Also, in practical embodiments, at least two redundant columns are provided per set Ea, Eb or Ec, each one being able to replace a defective column of each group of the set considered.

In the case where the circuit must allow the repair of several defective columns, the CRI circuit includes several fuse banks capable of memorizing each a defective column address.

The address A applied to the block CR1 is compared with all these addresses of defective elements. The redundant columns are split, i.e. there are several redundant columns CRal, CRa2, ... in place of the column CRa, several columns CRbl, CRb2, ... in place of the CRb column etc ... Each address storage battery is associated with a set of redundant columns: for example the first battery is assigned to columns CRal, CRbq, CRcl, the second battery is associated with the set CRa2, CRb2 ,
CRc2.

If the circuit CR1 recognizes a defective address Ai, memorized by the first battery, it selects the set of corresponding redundant columns CRal,
CRbl, CRcl and connects them to the respective output conductors CSa, CSb, CSc; on the contrary, if it recognizes a second defective address A2, it selects another set of redundant columns to connect them to the conductors CSa, CSb, CSc.

 In addition, for each defective address recorded in a battery of the circuit CR1, a plot position is also recorded in a battery of fuses of the MPP circuit. It is then necessary to provide an additional command of the MPP circuit by the circuit CR1 (command analogous to the command VAL) so that when a defective address is recognized by comparison with the nth fuse bank of circuit CR1, it is transmitted over the conductors PO, P1 the information generated by the nth fuse bank of the MPP circuit.

Claims (2)

1. Circuit for selecting a redundant column in an integrated memory with redundancy of data columns, said memory comprising - a network of memory elements organized in rows  and k groups of p columns, k and p being different from  the unit, each group (GO to G5> corresponding to a  input-output or write-read circuit  respective among k write-read circuits (LEO á  LE5), one column of each group that can be linked  to the write-read circuit corresponding to this  group by selecting a common column address  to all groups, - redundant columns (CRa to CRc) to replace  defective columns, - column address memory elements  able to memorize the address of defective columns, - a logic circuit (CR1) for column selection  redundant coupled to memory elements  column address to select a column  redundant when a faulty column address  is applied to memory, the k circuits  of writing-reading being divided into m sets of r  write-read circuits, m and r being different  of unity, and each set is associated with at least  a redundant column, - elements (MPP) for memorizing a position of  write-read circuit intended to memorize a  position of the write-read circuit corresponding to the  grcupe columns in which a column is located  defective, the memorized position being a position  j among r possible positions of the set of  write-read circuits in which the  write-read circuit considered, and - a selection circuit coupled to the elements of  write-read circuit position memorization, characterized in that the selection circuit is associated with a set of write-read circuits and is connected between, on the one hand, the groups of columns of said set and the redundant columns associated with said set and, on the other hand, the write-read circuits.  2. Selection circuit according to claim 1, characterized in that it comprises a transistor (TRO, TR1, TR2, TR3) per group of columns and r transistors (TROa, TRla) per redundant column, said transistors being controlled by signals (pO, pl, pO, pl) supplied by the write-read circuit position memorization elements (MPP).