FR2632092A1 - DELAYED ANTEMEMORY WRITE CONDITIONING CIRCUIT FOR A DUAL BUS MICROCALCULATOR SYSTEM COMPRISING AN UNIT 80386 AND A UNIT 82385 - Google Patents

Abstract

In an 80386/82385 microcomputer system, the timeline requirements for memory elements without cache possibility and placed by unit 82385 are more restrictive than the timeline tolerances placed on memory components without cache possibility by unit 80386. The present invention operates on the CWE write conditioning signals of cache memory 82385 and delays the signals in the event of a missed read. Delaying CWE signals expands the timeline tolerances placed on memory components without the possibility of cache memory and at the same time does not affect wait state parameters relating to missed read operations.

Description

WRITING CONDITIONING CIRCUIT

  DELAYED ANTEMEMORY FOR A SYSTEM

DUAL BUS MICROCULATOR

INCLUDING A UNIT 80386 AND

ONE UNIT 82385

  The present invention relates to a multi-bus microcomputer system with a cache memory subsystem and more particularly, an improvement to increase the tolerance of slow memory components in case of missed cache reading without affecting the parameters of waiting state. Information relating to the prior art relating to the 80386 unit, its characteristics and its use in microcomputer systems comprising cache memory subsystems, is described in the publications of Intel "Introduction to the 80386", April 1986 and "80386 Hardware Reference Manual (1986)". The characteristics and performance of using the 82385 unit are described in the Intel publication "82385 High Performance 32-Bit Cache

Controller "(1987).

  In microcomputer systems as in other computing systems, the speed of operations is an important criterion which in most cases must be considered in relation to the cost of the system. Many of the functions that were first introduced to speed up operations in the main computers and minicomputers are now applied in microcomputer systems. These include cache memory subsystems. The use of cache memory subsystems results in a multi-bus computer architecture. More particularly, in a clock microprocessor. Other operations that require more than two clock cycles are considered to have the number of wait states which is equal to the difference between the number of clock cycles required for the operation and the minimum of two cycles clock (which. we also refer to as a state

wait zero).

  Since the speed of operations is an important criterion, it is advantageous to ensure that, as far as possible, operations can be adapted to zero waiting operations as opposed to state operations

waiting one or two, etc ...

  Cache accesses are a type of stateful operation

waiting zero.

  Although it is desirable that as many memory accesses as possible be handled by the cache subsystem, it is of course necessary at times to access the main memory. One of the principles used for operating a cache subsystem is that in the case of a missed read, that is, a read operation in which the required information is not found in the cache subsystem, the information when read from main memory, is immediately written to the cache subsystem. Using this principle, the information read is then available in the cache subsystem (except in the case of overwriting) so that subsequent accesses to the same information do not require access to main memory. Thus, in the case of a missed read, two operations are required, (1) access to main memory to read the information required to make it available to the processor and (2) writing to the subsystem under - cache memory system, a first bus called a local bus CPU, connects the microprocessor (for example a unit 80386), a cache control unit (which can include a cache control unit 82385) and a random access memory serving as cache memory. The local bus CPU can be interconnected via an intermediate memory, to a second bus system called in a simplification, a system bus. Other components can be connected to the system bus (either directly or indirectly) such as a main memory, an input / output device, a memory

permanent, etc ...

  One of the main reasons for using a cache subsystem is to allow the acceleration of memory operations by conditioning the processor for reading from the cache memory subsystem since the required information is there. stored. The cache memory subsystem generally has a speed advantage over main memory. Because memory accesses can be limited to the cache subsystem, the processor does not require access to the system bus. This significantly frees up the system bus for its use in other operations, for example input / output operations, DMA, etc. This is another advantage of microcomputer systems at

  cache memory subsystems.

  In order to maintain an orderly sequencing of the various operations to be performed, the operations are divided into time units which are referred to as clock states. In a microcomputer system using for example the processor 80386 and the cache control unit 82385, the fastest memory operations require two clock cycles, each with two cache states of information read at 'instant in main memory. One of the peculiarities of the 82385 unit is that, in the case of a missed write state, the information to be accessed from the main memory, is necessarily rewritten in the front cache subsystem that they are not available for the processor. The manufacturer of the microprocessors recognizes this state and suggests one of the following two solutions: either the selection of a main memory fast enough so that the data can be accessed and made available for the 82385 unit within the period of time required for a fixed standby operation, i.e. increasing the cycle length over that which would normally be required by adding an additional standby state or states as necessary. Although both possibilities are practical, the first possibility affects the cost of the system since the faster memories required to meet the chronology requirements of the 82385 unit are more expensive and the second possibility introduces a delay in any operation of missed reading by imposing one or more

waiting states.

  An object of the present invention is therefore to eliminate the need to choose between these two possibilities so as to improve the tolerance of the system to slower memory components without affecting the wait state parameters.

  relating to missed read operations.

  The present invention satisfies this and other objects by providing a logic circuit for selectively delaying cache write conditioning signals in the case

of a missed read state.

  The logic circuit more particularly comprises means for detecting a missed read state. A missed read state is indicated when a system bus read signal (BUSRD) is active and a cache write conditioning signal (CWE) is also active. The logic circuit further includes means responsive to a cache write conditioning (CWE) output by the 82385 unit for delaying the active cache write conditioning signal in the case of a read operation.

missed is detected.

  In a particular embodiment of the present invention which will be described later, the cache memory subsystem is one. associative cache memory in two parts and thus comprising two memory banks. Unit 82385 makes a write conditioning signal available

  specific cache memory for each memory bank.

  The 82385 also generates a cache address conditioning conditioning signal (CALEN) as well as microprocessor selection signals (CS0, CS1, CS2 and CS3). The logic circuit according to the present invention operates on the cache write conditioning signals, that is to say the cache write conditioning signals for the two memory banks A and B. When an operation of missed read is detected, one of the two doors (cache write conditioning) is partially conditioned by the active signal of cache write conditioning signals (whether for bank A or bank B). The logic circuit detects the active BUSRD signal and also responds to cache write conditioning signals for the particular signal (for bank A or bank B) that is conditioned. The logic circuit delays the active signal of cache write conditioning signals and after application of the selected delay, fully conditions the appropriate gate which is assigned

  to the cache bench being written.

  The logic circuit of the present invention comprises a plurality of intermediate memories, one for each of the signals CALEN, CS0, CS1, CS2 and CS3 and these signals are connected to the cache subsystem through a

  appropriate intermediate memory.

  Thus, in the case of a missed read operation, the appropriate write conditioning signal is delayed. The intermediate memories provide an equivalent gate delay corresponding to the delay interposed by the cache write conditioning gate for the signals.

CALEN, CS0, CS1, CS2 and CS3.

  In the case where a cache write conditioning signal becomes active (for example to execute a cache write which is not associated with a missed read state), the logic circuit then naturally does not detect a state read failure so that no delay is imposed by the logic circuit on the cache write conditioning signal. However, the associated gate imposes a gate delay on this signal and the intermediate memories impose a delay practically equivalent to the

  associated signals CALEN, CS0, CSl, CS2 and CS3.

  Thus, one aspect of the present invention provides a multi-bus microcomputer system, cache memory and 80386/82385 units for selectively delaying cache write signals following a missed read in order to improve system tolerance. to slower memory components without affecting the wait state parameters relating to missed read operations, said microcomputer system comprising: a cache subsystem comprising said cache controller 82385, a cache memory and a local bus connecting said cache control unit 82385 and said cache memory to a processor 80386, and logic delay means responsive to a cache write state caused by a read failure to selectively delay signals cache write conditioning, said delay logic means comprising: (a) logic means with programmable networks, one input of which is c connected to write conditioning signals from said cache control unit 82385 to produce a delayed write conditioning signal at a write conditioning terminal in response to an active bus read, (b) a first gate logic a first input of which responds to said write conditioning signal from said cache control unit 82385 and a second input of which is connected to said write conditioning terminal and one output of which is connected to an input of

  write conditioning of said cache memory.

Brief description of the drawings

  Figure 1 is a general three-dimensional view of a conventional microcomputer system using the present invention. Figure 2 is a detailed schematic representation of the majority of the components of a microcomputer system

  conventional using the present invention.

  Figure 3 is a detailed schematic representation of the 82385 unit, the cache random access memory, the logic circuit and the intermediate memories of the present invention. FIG. 4 is a chronological diagram illustrating the various requirements relating to the chronology of the unit 82385 and of the unit 80386, and FIGS. 5A-5C show the operation of the present invention for writes of read cache memories thus missed than for cache writes not caused by

a missed reading.

  Figure 1 shows a microcomputer system

  in which the present invention can be used.

  As shown in the figure, the microcomputer system 10 comprises a number of components which are interconnected. More particularly, a system unit 30 is connected to and controls a control unit 20 (like a conventional video display unit). The system unit 30 is also connected to input devices such as a keyboard 40 and a mouse 50. An output device such as a printer

  can also be connected to system unit 30.

  Finally, the system unit 30 may include one or more disk control units such as the disk control unit 70. As will be described below, the system unit 30 responds to input devices such as the keyboard 40 and mouse 50 and input / output devices such as the disk control unit 70 for outputting signals to control output devices such as the control unit 20 and the printer 60. Naturally, the Those skilled in the art will recognize that other conventional components could also be connected to the system unit 30 in interaction therewith. According to the present invention, the microcomputer system 10 comprises (as will be seen more particularly below) a cache memory subsystem so that there is a local bus CPU interconnecting a processor, a control unit d cache and memory cache, which local bus CPU

  is connected by an intermediate memory to a system bus.

  The system bus is interconnected to and operates in interaction with I / O devices such as the keyboard 40, the mouse 50, the disk control unit 70, the control unit 20 and the printer 60. In addition, according to the teachings of the present invention, the system unit 30 can also comprise a third bus comprising a Micro Channel bus * to ensure the interconnection between the system bus and other input / output devices (optional), memory, etc ... * Micro Channel is a trademark of IBM Corporation Figure 2 is a schematic representation illustrating the various components of a conventional microcomputer system according to the present invention. A local CPU 230 bus (including data, address, and control components) connects a microprocessor 225 (such as an 80386 unit), a cache control unit 260 (which may include a control unit cache memory 82385) 'and a random access cache memory 255. An intermediate memory 240 is also connected to the local bus CPU 230. The intermediate memory 240 is itself connected to the system bus 250, also comprising address components, data and control. System bus 250 is located between the memory

  intermediate 240 and another intermediate memory 253.

  The system bus 250 is also connected to a bus control and chronology element 265 and to a DMA control unit 325. An arbitration control bus 340 connects the bus control and chronology element 265 and a central arbitration element 335. The memory 350 is also connected to the system bus 250. The memory 350 comprises a memory control element 351, an address multiplexer 352 and an intermediate data memory 353. These elements are interconnected with memory elements 360 to 364,

as shown in figure 2.

  Another intermediate memory 254 is connected between the system bus 250 and a planar bus 270. The planar bus 270 comprises address, data and control components, respectively. Various I / O adapters and other components such as the display adapter 275 (which is used to control the control unit 20), a clock 280, an additional random access memory 285, an RS 232 adapter 290 (used for serial I / O operations), a printer adapter 295 (which can be used to control the printer 60), a chronology unit 300, a floppy disk adapter 305 (which cooperates with the disk control unit 70), an interrupt control unit 310 and a permanent memory 315 are also connected to the planar bus 270. The intermediate memory 253 acts as an interface between the system bus 250 and an optional function bus such as the Micro Channel bus 320 represented by Micro Channel sockets. Devices like memory 331 can be

connected to bus 320.

  Although data for cache writes can be derived from memory 350, this data can also be derived from other memory such as the memory installed on the

Micro Channel bus.

  In a conventional 80386/82385 unit microcomputer system, the user is forced to select one of two unattractive possibilities relating to memory operations and more particularly to. operations

following a missed reading.

  In such a system, during a read cycle, the microprocessor 225 places an address on the address component of the local bus CPU 230. The cache control unit 260 responds to the address and determines whether the required information is contained in the cache memory 255. In the case where the information is found in the cache memory 255, the cache memory 255 is addressed, it places the data on the data component of the local bus CPU where it is available for the microprocessor 225. In the case where the required information is not in the cache memory 255, the cache control unit 260 then conditions the intermediate memory 240 so that the address can be passed from the local bus CPU 230 to the system bus 250 When the required address reaches the system bus 250, it is available for the memory 350 and after a period of time required by the characteristics of the memory 350, the addressed data appear on r the data component of the system bus 250. The data is connected through the intermediate memory 240 where it is available for both cache memory 255 and microprocessor 225. The information will be used in cache memory 255 to be written so that if the same information is required, another access to memory 350 is not required. Similar operations can take place with the memory on the planar bus 270 or on the function bus. In the case of the optional function bus, the address information is connected through the intermediate memory 253 to the memory on the optional function bus. Data from this memory is connected again through the intermediate memory 253, from the system bus 250 to the local bus

  CPU 230 through intermediate memory 240.

  However, as indicated above, the peculiarities of the 82385 unit require that the information extracted following a missed read be available on the local bus CPU for their writing in the cache memory 255 before this is done. required by processor 225 .. In other words, the chronology requirements placed on memory 350 or any other memory by unit 82385 are more restrictive than the chronology requirements dictated by unit 80386. The manufacturer of unit 82385 thus suggests that the user can: 1) either select memory elements (such as elements 361-364) in main memory 350 or in any other memory to be fast enough to meet the chronology requirements of unit 82385 with a specified wait state, or 2) ensure that the double operation initiated by a read

  missed occupies an additional waiting state.

  As will be described below, the present invention eliminates this selection requirement from one of two undesirable possibilities by effectively eliminating the restrictive chronology requirements dictated by unit 82385 so that the chronology requirements placed on the main memory 350 or any other memory is not more

  restrictive than those dictated by the 80386 processor.

  In order to implement the present invention, several logic elements have been added to the cache control unit 260, beyond the unit 82385 as illustrated in the

figure 3.

  FIG. 3 represents in schematic form the detailed components of the cache control unit 260 and of the cache memory 255. More particularly, the cache memory 255 is connected to the data element of the local bus CPU 230 and by the flip-flop 255L, to the address component

of the local bus CPU 230.

  The cache control unit 260 includes the memory unit

  cache control 82385 and a logic element 261.

  Figure 3 shows the output signals from the 82385 unit which

  are affected by cache write operations.

  These include the cache lock conditioning signal (CALEN), the cache write signals including CWEA (for bank A) and CWEB (for bank B) and the microprocessor selection signals CS0,

CS1, CS2 and CS3.

  As shown in FIG. 3, the logic 261 receives as inputs the signals CWEA and CWEB at the same time as two clock signals CLK and CLK2 (the first is exactly equal to half of the last) and the signal BUSRD (indicating a system bus reading). The BUSRD signal becomes active for operations that take place on the system bus 250. Any reading of memory (other than the cache memory) takes place (at

  less in part) on system bus 250.

  Logic 261 responds to its input signals and, when appropriate, generates the DCWEA signal (Delayed cache write conditioning A) or the DCWEB signal (Delayed cache write conditioning B). More particularly, in the case where the DCWEA signal is active and the BUSRD signal active (which thus indicates a missed reading without risk of error), the DCWEA signal will then be generated at the appropriate time. Similarly, in the presence of an active CWEB signal as well as a BUSRD signal

  active, the DCWEB signal will then be generated at the appropriate time.

  The DCWEA and DCWEB outputs of logic 261 provide

  each an input to the associated logic gate 263A or 263B.

  Each of these doors also receives a corresponding input from the associated output of unit 82385, that is to say that the other input of door 263A is supplied with CWEA and from the same

  way, the other input of gate 263B receives CWEB.

  In addition to logic gates 263A and 263B, the cache control unit 260 includes an intermediate memory 262 comprising intermediate memory elements 262a-262e, one for each of the signals CALEN, CS0, CSl, CS2 and CS3. As shown in FIG. 3, each element of the intermediate memory 262 is a logic gate which is permanently partially conditioned (by an input which is connected to the appropriate potential). The other input to the intermediate memory element comes from the corresponding output of the unit 82385. The output of the intermediate memory element 262a is applied as a control input to the latch latch 255L. The outputs of the intermediate memory elements 262b-262e are applied directly as input to the cache memory 255

in the form of CS0-CS3.

  Before describing the operation of the components of Figure 3, refer to Figure 4 for the illustration of the

appropriate timeline.

  Figure 4 is made up of three chronological diagrams.

  Each of the schemes begins at the moment when use of the system bus is initiated, ie when the signal BUSRD becomes active. The line referenced 80386 shows that at an instant MT1 following the start of a missed read, the data delivered as an output from the memory are valid. The instant MT1 is the chronology tolerance imposed on the memory by the

requirements of unit 80386.

  In the line of FIG. 4 referenced 82385, the chronology requirements imposed by the unit 82385 are illustrated. More particularly, the unit 82385 generates the signals CWEA and CWEB so that valid data are available from the memory at time MT2, that is to say at a time before valid data is required by the unit. 80386. Thus, Figure 4 represents the most restrictive chronology requirement (MT2) of unit 82385 compared to

  more flexible chronology (MT1) requirements of unit 80386.

  Figure 4 also shows the effects of logic 261. More specifically, the DCWEA and / or DCWEB outputs of logic 261 follow the more flexible timing requirements of unit 80386. More specifically, the DCWEA and / or DWCEB signals are delayed by the "delay" shown in Figure 4 by comparison with the CWEA and CWEB signals. Thus, by this delay, the more flexible chronology requirements of the unit 80386 are the only chronology requirements imposed on the main memory 350 in the case of a missed reading. This allows the use of cheaper memory components compared to the components that would be required for the 82385 unit in order to complete a missed reading within a

  specified number of wait states.

  The internal components of logic 261 implement the following logic equations:

  / DCWEA: = / BUSRD & / CLK & / CWEA / DCWEB: = / BUSRD & / CLK & / CWEB

  o the operator "&" is a logical AND, the operator "/" represents the negation and the other elements of the signal (apart from BUSRD) have

already defined.

  Figures 5A-5C are useful in explaining the operation of the element shown in Figure 3. More specifically, Figure 5A shows a typical CWE signal. The signal has two transitions, a first transition from low pass

  and a second transition from transition to high level.

  Cache 255 is arranged to perform a write operation at the high level transition of CWE as illustrated

in Figure 5A. Figure 5B shows typical CWE, DCWE signals and the output of the

  door (either 263A or 263B) for a missed read state. As shown on a first line, the CWE signal is generated by the unit 82385. In a missed read state, the logic element 261 generates the DCWE signal delayed from the CWE signal by an appropriate delay. The third line in Figure 5B (referenced DOOR) shows the output of the appropriate door (263A or 263B). More particularly, the output of gate 263 has a low level transition produced following the low level transition CWE signal. When the CWE signal is transitioned to the high level, the gate output remains at the low level due to the low level input of the DCWE signal. It is only when the DCWE signal goes high that the door output goes high so that the chronology of the writing operation is caused by the transition to the high level of the DCWE signal. As seen in the third line of Figure B, the write operation is delayed by the delay interposed by the logic element 261 by comparison with the transition to

high level of the CWE signal.

  FIG. 5C shows the operation during a cache write other than that caused by a missed read. The first line of FIG. 5C (referenced CWE) shows the CWE signal as generated by the unit 82385. Since FIG. 5C illustrates a cache write not caused by a missed read, the DCWE signal does not show any transition at all (BUSRD remains inactive). As a result, the gate output (263A or 263B) is synchronous with CWE so that the write operation is not

delayed at all.

  In one embodiment of the present invention, the duration of the

  DELAY is around 25 nanoseconds.

  The logic equations to which we have referred above, are reproduced immediately below. In these equations, the symbols have the following meanings: Symbols Definitions / Negation: = Recorded term A, equal to = Combinative term A, equal to & logical AND + logical OR

19 2 62 632 092

Logic equations

  / BUSRD: = BUSRD & BUSCYC385 & / BADS & / (BW / R) & CLK

  (1) + BUSRD & / PIPECYCLE385 & / (BW / R) & CLK + / BUSRD &

  BREADY + / BUSRD & / MISSl + / BUSRD & / CLK

/ BUSCYC385: = BUSCYC385 & / BADS & CLK

  (2) + BUSCYC385 & / PIPECYC385 & CLK + BUSCYC385 & / BT2 &

  CLK + / BUSCYC385 & BREADY + / BUSCYC385 & / CLK

  / PIPECYC385: = PIPECYC385 & / BADS & / BUSCYC385 & CLK &

  / BREADY (3) + PIPECYC385 & / MISS1 & BT2 & / BUSCYC385

  & CLK & / BREADY + / PIPECYC385 & / CLK

  / MISSl: = MISSl & BUSCYC385 & CPUNA & / BADS & / (BW / R) & CLK

  & NCA (4) + MISS1 & / BUSCYC385 & / BADS & / (BW / R) & CLK &

  NCA & / BREADY + JMISSl & / CLK + / MISSl & BREADY

  / CPUNA: = / MISS1 & CLK & CPUNA & / NACACHE

  (5) + / MISS1 & CLK & CPUNA & iBREADY & / BUSCYC385 + / CPUNA & / CLK + / CPUNA & / MISSl & CLK + JCPUNA & CLK & BREADY +

/ CPUNA & BUSCYC385 & NACACHE & CLK

  / BT2: = BUSCYC385 & PIPECYC385 & / BADS & CLK & BT2

  (6) + BUSCYC385 & / PIPECYC385 & BADS & CLK & NACACHE & BT2

  + MISS1 & / BUSCYC385 & / BADS & / (BW / R) & CLK & NCA &

  / BREADY + / MISS1 & / BREADY & / BUSCYC385 & CLK + / BT2 &

BREADY & NACACHE + / CLK & / BT2

  In the previous logic equations, the following signals have been referred to or described as indicated in the Intel publications cited above: BADS BREADY (BW / R) currently referenced as BW / R, parentheses are used to indicate that the full term is a single CLK BADS clock signal, when active, indicates a valid address on the system bus 250. BREADY is a "ready" status signal from the system bus 250 and which will to the local bus CPU 230. BW / R defines a write or read signal from the system bus 250. CLK is a processor chronology signal which is in phase

with processor 225.

  Equations (1) - (6) define: BT2 BUSCYC385 BUSRD CPUNA MISSl PIPECYC385 In terms of defined signals, the signals that have been described or to which we refer, are the signals indicated in the

  Intel publications cited above and NCA and NACACHE.

  BT2 reflects the state of system bus 250. State BT2 is a

  state defined in Intel publications cited above.

  BUSCYC385 also reflects the state of the system bus 250. It is high for bus states BTI, BT1, BT1P and low for bus states BT2, BT2P and BT2I (these are again bus states referenced in the publications of

Intel cited above).

  / BUSRD is active during readings appearing on the bus

of system 250.

  CPUNA is a signal applied to unit 80386 and allowing a

pipeline operation.

  MISS1 is active to define the first cycle of a double cycle for the manipulation of a 64-bit reading applied to

  cache memory devices.

  PIPECYC385 is active during BT1P (which is a bus state which is referred to in the Intel publications cited above. NCA is a signal created by the decoding of the address component on the local bus CPU 230 to reflect on the active state , access without cache possibility The cache possibility is determined by a label component (A31 to A17) and programmable information defining the labels (if any) which refer to addresses with possibility cache as opposed to addresses without

possibility of cache memory.

  NACACHE is a signal similar to the BNA signal. BNA is a signal generated by the system requesting a following address from the local bus CPU 230 and is referenced in the Intel publications cited above. NACACHE differs from BNA only in that BNA is created for a 32K cache while NACACHE is created for a 64K cache. As long as the cache memory is 32K as reported in Intel publications, the NACACHE signal referred to here could be replaced by the BNA signal. In one embodiment, the logic element 261 was in the form of a programmable logic network. It is obvious that other logic devices could be used to provide an identical function. Although a preferred embodiment of the present invention has been described here, it is obvious that modifications can be made thereto without departing from the scope of the latter which must be analyzed not in terms of

  of the example described here but according to the claims ci

attached.

Claims (11)

  A multi-bus microcomputer system comprising: a microprocessor and a cache subsystem connected together by a local bus CPU, said cache subsystem comprising a cache controller and a cache memory, and means logic connecting write conditioning signals from said cache control unit 82385 to said cache memory, said logic means comprising: logic delay means responding to a cache write state caused by a missed read and responding to a write conditioning output from said cache control unit and having a write conditioning terminal for producing a delayed write conditioning signal at said write conditioning terminal, and a logic gate with a first input connected to said write conditioning output of said cache control unit, a second input connected to the said write conditioning terminal, and an output connected to a write conditioning input of said cache memory. 2. A system according to claim 1 wherein said logic means also connects semiconductor element signals from said cache control selection unit to said cache memory, wherein said logic means further comprises - intermediate memory means for delaying the transmission of semiconductor element selection signals, said intermediate memory means having an input for each of said semiconductor element selection signals and an output for each of said semiconductor element selection signals, outputs of said semiconductor means intermediate memory being connected to the terminals of the element selection signals   semiconductors of said cache memory.   3. A system according to claim 2 wherein said intermediate memory means further comprises an input for a cache latch flip-flop conditioning signal from the cache control unit and an output connected to a latch flip-flop.   locking addresses of said cache memory.   4. A microcomputer system according to one of   previous claims wherein said memory   cache memory includes first and second memory banks, wherein said cache control unit has a first write conditioning output corresponding to said first memory bank and a second write conditioning output corresponding to said second memory bank , and wherein: said delay logic means responds separately to said first or second write conditioning output of said cache control unit and includes first and second write conditioning terminals for producing a first conditioning signal delayed write to said first write conditioning terminal corresponding to said first write conditioning output or a second delayed write conditioning signal to said second write conditioning terminal corresponding to said second conditioning output d writing, said logic gate having said first input connected e at said first write conditioning output of said cache control unit, a second input connected to said first write conditioning terminal, and an output connected to a write conditioning input of a first bank of said cache memory, said logic means comprising: another logic gate with a first input connected to said second write conditioning output of said cache control unit and a second input connected to said second write conditioning terminal , and an output connected to a write conditioning input   the second bank of said cache memory.   5. A system according to claim 1 further comprising: a system bus, a memory connected to said system bus, means connecting said system bus and said local CPU bus, 2632O92   said cache control unit comprising first means responsive to said missed read state for passing addressing information from said local bus CPU to said system bus to address said memory, said cache control unit comprising second means responsive to data on said system bus removed from said memory to connect said data to said local bus CPU, which allows data removed from memory to be written to said cache memory via said signal   delayed writing conditioning.   6. A system according to claim 5 in which said system bus is connected to an optional function bus, a memory device is connected to said optional function bus, so that the memory connected to said optional function bus is addressed and addressed data is sent back to said local bus CPU by   through said system bus.   7. A multi-bus microcomputer system comprising a microcomputer, a cache controller and a cache memory for selectively delaying cache write signals following a missed read in order to improve the system's tolerance to the components of slower memory without affecting the wait state parameters relating to missed write operations comprising: - logic means responding to a cache write state caused by a missed read to selectively delay conditioning signals d cache write comprising: means responsive to a system bus read with an input connected to write conditioning signals from said cache control unit to produce a delayed write conditioning signal to a write conditioning terminal, - a logic gate with a first input connected to a write conditioning output of said lad e cache control unit and a second input connected to said write conditioning terminal and an output connected to a write conditioning input of said cache memory, and - intermediate memory means for delaying the transmission of signals for selecting semiconductor elements from the cache control unit, said intermediate memory means having an input for each of said semiconductor element selection signals and an output for each of said semiconductor element selection signals, outputs of said intermediate memory means being connected to the element selection terminals   semiconductors of said cache memory.   8. A system according to claim 7 which further comprises: a system bus, a memory connected to said system bus, means connecting said system bus and said local bus CPU, said cache control unit comprising responsive means a missed cache read to pass address information from said local CPU bus to said system bus to address said memory, and means responding to data, on said system bus, removed from said memory to connect said data to said bus local CPU, so that data removed from memory is written to said cache memory via said signal   delayed writing conditioning.   9. A system according to claim 8, in which said system bus is connected to an optional function bus, a memory means is connected to said optional function bus, said memory means responding to an address connected from said local CPU bus, said system bus is connected to said optional function bus for removing data stored at said address and for controlling said optional function bus with said data, whereby data removed from said memory means is written to said cache memory by the by said signal   delayed cache write conditioning.   10. A system according to claim 9 wherein said intermediate memory means further comprises an input for a cache latch flip-flop conditioning signal from the cache control unit and an output connected to a latch flip-flop.   locking addresses of said cache memory.   11. A system according to claim 9 wherein said cache memory comprises first and second memory banks, said cache control unit having a first write conditioning output corresponding to said first memory bank and a second memory output write conditioning corresponding to said second memory bank and in which: said logical delay means respond separately to said first or second write conditioning outputs of the cache control unit and having first and second conditioning terminals d writing to produce a first delayed write conditioning signal at said first write conditioning terminal corresponding to said first write conditioning output or a second delayed write conditioning signal at said second write conditioning terminal write corresponding to said second write conditioning output, said door lo logic having a first input connected to said first write conditioning output of said cache control unit and a second input connected to said first write conditioning terminal, and an output connected to a write conditioning input a first bank of said cache memory, and comprising a second logic gate with a first input connected to said second write conditioning output of said cache control unit and a second input connected to said second conditioning terminal d writing, and an output connected to a writing conditioning input of a second bench of said cache memory.