FR2628923A2 - Stereoscopic video image viewing system - Google Patents

Abstract

The viewing system uses alternate views presented in alternation via electro-optical switches at double the frequency of the received signals. The latter are fed to 4 memory circuits each of which is used to hold the successively received video rasters. The corresponding image points of two successive rasters on the same side read-out simultaneously. The obtained image data is subjected to a real-time interpolation process, with a different processing cycle for the left-hand and right-hand views. Pref. the memory circuits and the data processing circuits are provided by respective IC's.

Description

(FRENCH REPUBLIC Publication No. 2,628,923 to use only for

  INSTITUTE NATIONAL Reproduction Orders)

OF INDUSTRIAL PROPERTY

  DE * LAPYRIDS L N national registration: 88 03365 PARIS

  Int Cl4: H 04 N 13/04.

    APPLICATION FOR A A2 CERTIFICATE OF ADDITION

A PATENT OF INVENTION

  ) Date of deposit: 16 March 1988. (Applicant (s): CAHEN Olivier - FR.

) Priority:

@ Inventor (s): Olivier Cahen.

  (Date of the public availability of the

  application: BOPI "Patents" No. 38 of 22 September 1989.

  (References to other national documents

  2nd addition to patent 87 06499 taken on May 7, 1987. (Owner (s)

  G Attorney (s): Cabinet Armengaud Senior.

  Processor stereoscopic presentation of video images.

  (Apparatus for the observation of stereoscopic video

  transmitted or recorded according to the technique of views 36 40 37 44 59 32 33

  alternate, and presented by means of electronic switches --.-.....

  at the double frequency of the reception, Variants implement the principle using also

  other known technical means. in particular, me- -.

  moires organized into words containing only one or two

components of the video signal.

  The subset 9 of the interpolation circuits does not include

  whereas one or two interpolators 43, 44, and at least one

  switching circuit 59 distributing the signal to the three

  I output channels of the converters 31 to 33.

  The invention is applicable to televisions. 3 3 31 9 N 3O e0 N <o oe L D Sales of the fascicles to the NATIONAL PRINTING. The present invention relates to a certificate of addition to the main application No. 8. 06499 filed on 7O? 05 87, and at a first

  addition, no. 87 16002 filed on 19 11 8 ?.

  The main application concerns a processor whose purpose is to allow, by asymmetrical data interpolation in real time, a comfortable observation, free of spatio-temporal distortions, of stereoscopic video images transmitted or recorded according to the technique of alternating views. , and presented by means of switches

  electro-optical, at the double frequency of the reception.

  The first addition relates to organizational variants of the memories (11) to (14) and their interface circuits designated as "multiplexers", of interpolator structure, and control circuits of these interpolators for the purpose of observation. , by the same

  * equipment, programs without relief.

  A first object of the present addition is the adaptation of the

  device to other organizations data in the memories.

  A second object of the present addition is a device for interpolation between successive lines, allowing a better

  presentation without relief of programs broadcast in relief.

  Another object of the present addition is the combination of certain means set forth in the main application and the first addition with other known technical means for performing interpolations.

more precise temporal

  The invention will be better understood from the description given above.

  after various embodiments, and the accompanying figures, o: Figure 1 shows, in schematic form, the main elements of the entire TV including the invention; FIGS. 2, 3, 4, 5 represent, in schematic form, the main elements of the subset (9) of the circuits which receive the data read in memory for processing them until they are transformed into analog control signals of the cathode ray tube, according to several variants included in the invention; FIG. 6 represents, in schematic form, a subset (100) to be inserted between one of the buses (36) or (37) and an interpolator (43) for improving the images for the viewer who wishes to observe without

  relief a program broadcast in relief.

  FIG. 7 shows, in schematic form, an exemplary embodiment of an interpolator variant, which is more efficient in the case where

  available data concerning the movements in the image.

  FIGS. 8 and 9 represent, in schematic form, two embodiments of a device by which, depending on the

  result given by a motion detector, a switch changes the.

  response of a filter to attenuate the resolution of the images of the edges of moving objects, the harmful effect of the interpolation, without however

  degrade the sharpness of the edges of immobile objects.

  The realization of the processor was described in the main application and in the first addition on the assumption that each point of the image is defined by three components (red, green, blue, or luminance and two color differences) and that each of these three components, relating to the same point of the image, is stored in memory, then read and conveyed by the reading buses (36) and (37), and then processed

  by the interpolators, simultaneously.

  Other organizations may be retained; the application of the principle of the invention in the case of such

  memory organizations involves other structures, described below.

  below, interpolation circuits.

  Figure 1 recalls the main elements of the television including the invention. It includes: - gathered in a subset (8), reception circuits, demodulation and digitization of the received video signal; the subsets (11), (12), (13), (14) of memory; the subset (41) of the synchronization generators; - the cathode ray tube or display screen (34); - gathered in subset (9), the circuits that transform the

  data read in memory to compensate for spato-

  which include interpolators (43) to (45) and

  the digital-to-analog converters (31) to (33).

  The present addition more specifically relates to variants of the structure of this subset (9), in particular in the cases where only one, or two, of the components of the video signal, and not three, are simultaneously stored in each of the words of memoirs (11),

  (12), (13), '(14) and transmitted by the buses (36) and (37).

  FIG. 2 shows an exemplary embodiment of the subassembly (9) according to the invention, assuming that the received and stored signal consists of two simultaneous components: on the one hand the luminance signal on the other hand, a single chrominance signal; alternatively representing blue and red color differences. It is mentioned for memory the processor (39) defined in the main application, which comprises the synchronization generator (41) and

  the interpolators (43) to (45), but not the converters (31) to (33).

  In the case described here, the subset (9) comprises only two interpolators (43) and (44), which are respectively connected, upstream, to the first eight and to the last eight conductors of each of the data buses read ( 36) and (37). The luminance signal from the interpolator

  (44) is directly transmitted to the input of the converter (33).

  The alternating chrominance signal, at the output of the interpolator (43), is addressed alternately, by means of a switching circuit (59>, controlled by a synchronization signal emitted by the generator (41), and acting simultaneously on all the drivers of the output bus of this

  interpolator, to both converters (31) and (32).

  The converter (33) establishes, as in the main application, the

  luminance signal Y directed to the control of the cathode ray tube (34).

  The converters (31) and (32) establish the same signals of

  chrominance Q1 and Q2 for the control of the cathode ray tube (34).

  Figure 3 shows another embodiment of the same subset

  together (9). The interpolated digital signals, at the output of the interpolators (43) and (44), are directly transmitted to the digital-to-analog converters (31) and (33). An analog switching circuit (78) alternately distributes the analog signal from the converter

  (31) to the two output channels Q1 and Q2 of the chrominance signals.

  FIG. 4 represents an exemplary embodiment of the subset (9) assuming that the memory is organized in eight-bit words, which contain only one component of the signal; this one then represents alternately the luminance and the chrominance, this one being composed

  alternatively color differences in red and blue.

  The subassembly (9) then comprises a single interpolator (43), at the output of which a digital switching circuit (80) alternately distributes either the luminance signal to the converter (33) or the alternating signals of chrominance to the second switch

  digital (59). This has the same role as above according to Figure 2.

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_

  The control terminals of this interpolator (109) are powered by means that are not original and therefore not described, so that it only interpolates the data read in the memories (107) and (108) when the data is read. reading

odd lines.

  When reading the even lines, the interpolator (109) transmits to the interpolator (43) alternately data from the

  memory (107) and memory (108).

  Thus, every other line on the screen is obtained by interpolation

  between two superimposed lines, and the image has a more continuous appearance.

  Another object of the present addition relates to means for making interpolators that perform better than those described above.

in the main application.

  The principle of the compensation of spatio-temporal distortions, which is the subject of the main request and its additions, consists in presenting interpolated frames between two successively received frames I (x, y, t) and I (x, y , t + T), where T is the time interval between two successively received frames of the same side, ie 40

  milliseconds according to European standards.

  The frames presented on the screen are defined, according to the principle of the invention, as I (x, y, t + KT), where the value of the coefficient K varies from one frame to the other, these values being different for the views of

left and right.

  The values of the parameter K are related to those of the two control signals C2 and C3 of the interpolators, since these control signals are precisely defined to enable the interpolators to perform the operation defined above:

K = (C2 / 2) + (C3 / 4)

  The means described in the main application, in the first addition and above, allow an estimation of the frames to be presented, according to the following equation: I (x, y, t + KT) = (1-K) I (x The means already described actually make it possible to calculate each frame in real time, with the values of K chosen for each frame according to the rules described above. always calculated according to the equations above, by interpolation between

  points of the same position in successive frames on the same side.

  The variant described below makes it possible, with coefficients K, defined in the same way, to calculate each frame by the equation I (x, y, t + KT) = I (x + KP, y, t ) where P is the value chosen to best approximate the expression I (x + P, y, t) = I (x, y, t + T). The variable P represents the horizontal component of the movement of objects neighboring the position (x, y) between the two frames defined at times t and t + T. Many studies have been devoted to the extraction of data concerning the movement between two successive frames. These studies

  resulted in the publication of various "motion detector" schemes.

  The motion detector used here will be assumed to be part of known techniques and will therefore not be described in detail. Only will

  describe the means by which it is i-granted to the invention.

  Fig. 7 shows how a motion detector (111) is

  incorporated in the processor according to the invention.

  The motion detector (111) receives signals routed simultaneously through the read data buses (36) and (37). In general, it uses only the most significant bits of the luminance signals. The detector (111) delivers in real time a digital signal representing the value of the variable P defined by the equations above. This signal is introduced at one of the input terminals of a digital multiplier (112) which receives on its other input the digital signal representing the coefficient K, periodic according to a cycle of four frames, defined from

control signals C2 and C3.

  The result R of the multiplier (112), which represents the delay to be given to the signals received by the bus (37), is introduced on variable delay shift registers (113). Each of these registers (113) is substituted, in the subset (9), with one of the interpolators (43), (44), (45). The processor comprises, as above, as many registers (113) as video signal components recorded in the same word of the

memories (11), (12), (13), (14).

  The register (113) is of variable delay because it comprises several inputs (114), several outputs (115) or at the same time several inputs and several outputs, switched according to the same control signal R emitted by the multiplier (112 ). This register processes in parallel all the bits of each luminance or chrominance signal, as were

  the interpolators (43), (44), (45).

  The output signal of the register (113), accessible on the active output terminal (115) selected according to the value of R, is transmitted either to one of the digital-to-analog converters (33) for example, either to one of the

  switches (59) or <80) previously defined.

  The subset (9) may also comprise digital filters & variable coefficients as a function of the difference between the intensities of the signals present on the successive frames, or of the coefficient P delivered by a motion detector, so that the signals

  are more strongly smoothed in case of faster movement.

  FIG. 8 thus shows, in schematic form, an exemplary embodiment of such a device. The motion detector, in this case more simplified, comprises two shift registers (116) and (117), each processing in parallel the four most significant bits of the luminance signal. The register (116) is traversed by the signals from the bus

  (36), the register (117) by those of the bus (37).

  The motion detector also comprises a correlator (118), a combinational logic circuit according to techniques known to be known, whose purpose is to determine whether the two sequences of values present simultaneously in the registers (116) and (117) are, or not, similar with an offset that does not exceed a given number of elements. For example, to verify an offset with two elements, the correlator examines the signals present on one of two of these registers; to check for an offset with four elements, it processes the signals one in four squares. Such a motion detector is insufficient to calculate the parameter P defined above, but acceptable to define whether this parameter P is lower or not, in the vicinity of a given point of

the image, at a given threshold.

  The output signal of the detector, possibly composed of several pieces of information in parallel, signifying the results of comparison of the offset with several given thresholds, controls a switch (119) which, towards the corresponding digital-analog converter (33), supplies the signal delivered by the corresponding interpolator (4S) and corrected by

  digital filters (120), (121), or (122).

  These digital filters have a function of low-pass filters, the effect of which is to smooth the values representing the successive points of the line represented in the image. They can be made according to any known technique. Other provisions of the filters, for example downstream of the

  switch, can be chosen.

- 8 -

  FIG. 9 represents a device similar to that of FIG. 8, but in which the digital filters are replaced by analog filters (123), (124), (125), each consisting for example of a resistor, a capacitor and a stage of amplification and decoupling. In this case, the switch (119) and its filters are placed

  downstream of the digital-to-analog converter (33).

  Filters of the same type are also inserted on the path of chrominance signals, or color components. They are controlled, in this embodiment, by the same signal defined by

  the correlation on the luminance signal.

  The principle of the device is the same as in FIG. 8: the filtering applied to the interpolated signal is a function of the responses of the motion detector. For example, the device does not introduce filtering for image areas that are known to be nearly immobile, broadband filtering for low-mobility objects, narrow-band filtering for objects that are not recognized as similar

between the two successive frames.

  The filter system described above can also work without the motion detector, in the case where motion information is transmitted at the same time as the image, by known methods such as the ANTIOPE system for transmitting digital signals. during frame head deletions, or the D2-XAC system that leaves room for a few bytes per line in the reserved channel

  digital sound and various data.

  The subassembly (9) may further comprise known and therefore undescribed elements, such as filters, "gamma" correction circuits, as well as digital or analog mixers which establish, from the signals luminance and chrominance, the signals corresponding to the three colors blue, red, green, etc. In the latter case, the output channels of the subassembly (9) conduct the control signals B, R, V of the cathode ray tube, and not the signals Y, Q1,

  Q2 as indicated, by way of example, in the figures.

Claims (16)

REVEND I C A T I 0 N S   1 Device for improving video images in relief:   * according to claims 1 and 2 of the main application n '   87 06499 filed May 7, 1987; * used in the following hypotheses: the signals representing the images come from a transmission on a normal television channel or a normal video recording; the respective left and right views come from the even and odd order frames received from the transmission or recording respectively; these left and right views are presented to each of the eyes of the viewer by means of electromechanical or electro-optical switches operating at the double frequency, that is to say having two frames for the duration of one; * whose object is to eliminate a "spatio-temporal distortion" by which, due to the above conditions, any lateral movement of an object corresponds to an undesirable and annoying offset of the relative positions of its left and right images ; characterized in that it comprises a subset (9) of   circuits by which the data read simultaneously in the sub-   memory assemblies (11i) and (13), or (12) and (14), and respectively conveyed by the sets (36) and (37) of conductors, are interpolated in real time differently depending on whether it is data representing the left and right views and then converted to analog data.   2 Device according to claim 1, characterized in that this sub-component   set (9) comprises as many interpolators (43) to (45) as components of the video signal carried simultaneously by the sets conductors (36) and (37).   3 Device according to claims 1 and 2, characterized in that the   subassembly (9) comprises switching means (59), (78), (80) or <87), in a number complementary to three of the number of interpolators, by which the interpolated signals are successively directed to the   three output channels of the luminance and chrominance signals.   eapTdv snld is e2imFT, l ep% uTod eo ep eSvuTsToA nu nuamaAnom el 'anb ea; oag snld% u; ng, p aumssed epduq aun oeweAî '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' '' you have the ene eios elEta ep (9T) (OZI) <se'ltT; Duo; el epuemoo eBTços ep Itu2Ss el; uop; (IT>); e 5z (911) saelsT.9a seo ep unoîqo ep saeSie sjeATp ep uueumAod xnvuBTs sep ted, p seumoq ans his years% uiAeoa. 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