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FR2626692B1 - MULTIPROCESSOR PARALLEL ARCHITECTURE - Google Patents

MULTIPROCESSOR PARALLEL ARCHITECTURE

Info

Publication number
FR2626692B1
FR2626692B1 FR8801467A FR8801467A FR2626692B1 FR 2626692 B1 FR2626692 B1 FR 2626692B1 FR 8801467 A FR8801467 A FR 8801467A FR 8801467 A FR8801467 A FR 8801467A FR 2626692 B1 FR2626692 B1 FR 2626692B1
Authority
FR
France
Prior art keywords
parallel architecture
multiprocessor parallel
multiprocessor
architecture
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8801467A
Other languages
French (fr)
Other versions
FR2626692A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to FR8801467A priority Critical patent/FR2626692B1/en
Publication of FR2626692A1 publication Critical patent/FR2626692A1/en
Application granted granted Critical
Publication of FR2626692B1 publication Critical patent/FR2626692B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR8801467A 1988-02-01 1988-02-01 MULTIPROCESSOR PARALLEL ARCHITECTURE Expired - Fee Related FR2626692B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8801467A FR2626692B1 (en) 1988-02-01 1988-02-01 MULTIPROCESSOR PARALLEL ARCHITECTURE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8801467A FR2626692B1 (en) 1988-02-01 1988-02-01 MULTIPROCESSOR PARALLEL ARCHITECTURE

Publications (2)

Publication Number Publication Date
FR2626692A1 FR2626692A1 (en) 1989-08-04
FR2626692B1 true FR2626692B1 (en) 1995-01-13

Family

ID=9363057

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8801467A Expired - Fee Related FR2626692B1 (en) 1988-02-01 1988-02-01 MULTIPROCESSOR PARALLEL ARCHITECTURE

Country Status (1)

Country Link
FR (1) FR2626692B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412313A (en) * 1981-01-19 1983-10-25 Bell Telephone Laboratories, Incorporated Random access memory system having high-speed serial data paths
US4616310A (en) * 1983-05-20 1986-10-07 International Business Machines Corporation Communicating random access memory
EP0166192B1 (en) * 1984-06-29 1991-10-09 International Business Machines Corporation High-speed buffer store arrangement for fast transfer of data
US4633440A (en) * 1984-12-31 1986-12-30 International Business Machines Multi-port memory chip in a hierarchical memory

Also Published As

Publication number Publication date
FR2626692A1 (en) 1989-08-04

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Legal Events

Date Code Title Description
ST Notification of lapse