FR2611938A1 - Memory access control system - Google Patents

Abstract

a) Memory access control system. b) A memory access control system includes a set of addresses 9-10 which exhibits a bit representing the validity of contents of a pre-memory 18 and a bit representing a coincidence between the contents of the pre-memory 18 and the contents of the main memory unit 23, a circuit 13 making a hit/miss judgment in order to give judgment on a hit/miss of the pre-memory 18, a circuit 14 for determining the level to be replaced in order to determine a level to be replaced of the pre-memory 18 when a miss by the pre-memory occurs, a judgment circuit 16 concerning the replacement in order to detect the validity of the data of the block at the level to be replaced and to detect a non-coincidence between the contents of the pre-memory 18 and the main memory unit 23 and to judge the necessity for writing the data from the pre-memory block 18 into the main memory unit 23. c) In a pre-memory system, the invention makes it possible to process the read and write operations with a single request.

Description

FIEMORY ACCESS CONTROL SYSTEM
The present invention relates to a memory access control system comprising a cache memory with conservation of the stored data.

 In a conventional memory access control system comprising a cache memory with storage of the stored data, there is a non-coincidence of the data between a cache memory and a main memory unit (MMU). When a "miss" occurs for the cache, the contents of the cache should be returned to the main memory unit MMU. For this purpose, a back and forth request (swap; from the main memory unit M.MU must be generated and executed, then a block transfer request must be sent to the MMU, which therefore requires a two-phase treatment.

 In the conventional technique above, when there is a "miss" for the cache memory, and a back and forth request (swap) is generated, a request for memorization and a request for reading for MMUs are processed separately, so ordering is undesirably complicated.

 An object of the present invention is to provide a memory access control system to eliminate the above conventional drawback.

 A memory access control system connected between a request source (for example an arithmetic unit and an input / output unit) and a main memory unit by providing a cache memory with data retention comprises a means forming set of addresses which presents a bit representative of the validity of a content of the cache memory and a bit representative of a coincidence between the content of the cache memory and the main memory unit; means for judging a successful hitZa failed hit from the cache in accordance with an output signal from the address set means; means for determining a level of the cache to be replaced when a failed cache hit occurs; means for detecting the validity of the data of the block of the level to be replaced and for detecting a non-coincidence between the contents of the cache memory and of the main memory unit in accordance with an output of the means forming an address set corresponding to the level to be replaced, and to judge the necessity of writing the data of the block of 1 cache memory in the main memory unit; and means for processing the write and read operations of the main memory unit using a single request when the need arises to write to 1 main memory unit the data of the block of 1 year - memory.

FIG. 1 is a block diagram of the memory access control system according to an embodiment of the invention;
Figure 2 is a block diagram of a control unit of the main memory unit
MMU shown in Figure 1;
Figures 3 (A) to 3 (N) and 4 (A) to 4 (I) are timing charts of the signals to explain the operations of the circuits shown in Figures 1 and 2;
Figure 5 is a block diagram of a memory access control system according to another embodiment of the invention;
Figure 6 is a block diagram of a control member of the main memory unit shown in Figure 5; and
FIGS. 7 (A) to 7 (J) are timing diagrams of the signals to explain the operations of the circuits represented in FIGS. 5 and 6.

 Preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

FIG. 1 represents a memory access control member according to an embodiment of the invention. The memory access control device in FIG. 1 is connected to a request source (for example an arithmetic unit (not shown) and an input / output unit (not shown) and to a main unit of memory (MMU.) 23. In this embodiment, the request source comprises three units, that is to say a unit A, a unit
B, and a unit C. The memory access controller comprises an access register section 30 for receiving a storage request to store data in the MMU 23 and a read request for extracting from the MMU 23 the data, as well as a section 40 for processing the request. The access register section 30 comprises a buffer register or access register A 1 for receiving a request from. of unity
A, an access register B 2 for receiving a request from unit B, an access register C 3 for receiving a request from unit C, an occupancy verification device 4 and a selector 5 .

The occupancy verification unit 4 receives information associated with an occupancy state of the main memory unit MMU 23. This information is provided by a control unit 17 of the unit MMU (to be described below) via a line 35. The occupancy verification unit 4 sends a selection signal to the selector 5 in accordance with an order of priority of the units A, B and C. The selection signal is used to select these units. The selector 5 selects a correct unit in accordance with the selection signal supplied by the occupancy verification member 4. As long as a request results in a successful hit, or successful hit of the cache memory, it is i.e. as long as an address requested from a cache 18 (to be described later) is there, the request is sent by the selector 5 to the section 40 for processing the request via a line 41 each clock period T. On the other hand, if a missed attempt or missed attempt in the cache occurs, that is to say if the requested address is not found in cache 18, a block of data is transferred from 1 main MMU 23 to cache 18 and the MMU 23 is placed in the busy state. The occupancy verification unit serves to avoid the loss of a request during the state of occupation of the MMU 23 unit.

 An address signal, forming part of the information concerning the request, sent by the selector 5, is stored in an address register 6 and a data signal, forming part of this same information, is stored in a register data 7.

 If a failed hit occurs, the register 8 stores the data (i.e. the data constituting the response of the MMU) transferred from the MMU 23 to the cache 18 .

When the cache hit occurs, the data stored in register 8 and the data (i.e. the portion rewritten in the block) stored in data register 7 are merged and sent to the cache 18. On the other hand, if a successful hit of the cache occurs, the data sent to cache 18 is the output signal from the data register 7.

The registers 7 and 8 selectively send the output signals to the cache memory 18 in accordance with an output signal coming from a hit / miss judgment judgment circuit 13 (to be described below) controlled by an instruction coming from the control unit 17 of the MMU unit.

 The address signal stored in the address register 6 consists of a block address signal and a column address signal. The block address signal is sent to N + 1 sets of addresses, that is to say to the various sets ranging from the set of address 9, of level 0, to the set of address 10 , level N, via a line 44. At the same time, the block address signal is sent to one of the input terminals of each of the N + 1 comparators, this is -to say to the different comparators going from comparator 11 of level O to comparator 12 of level N, via a line 47. A signal sent by each of the sets of addresses, of the set 9 of level O to l the set 10 of level N, is also sent to the other input terminal of one, corresponding, of the N + 1 comparators.

The column address signal from the address register 6 is sent to the different sets of addresses from level 9
O to set 10 at level N, as well as to memory 18.

 The cache memory 18 has memory positions going from level O to level N, corresponding respectively to the different sets of addresses going from the set of addresses 9 of level O to the set of addresses 10 of level N. Each set of addresses in memory 9 or 10 includes areas for a corresponding block address signal for cache 18, a bit V representing the validity of each block data and a bit M representing a non-coincidence between the contents the main memory unit 23 and the cache memory 18.

If a request is a storage request, the content of cache 18 is updated and the bit
M takes the logical value "1".

 The comparators, going from the level II comparator II to the level comparator 12, compare the block addresses sent by the address sets, going from the level 9 address set 9 to the address set 10 of level N, with block address signals from address register 6 through line 47, respectively.

For example, the comparator 11 at level O compares the output signal from the set of addresses 9 at level O with the block address signal which is located in the address of the request.

If the block address signal from the level O address set coincides with the block address signal found in the request address and if bit V has the logical value c, is that there has been a successful hit "at level O in cache 18. We then access the block at level O for requests to read and store from cache 18.

 The hit / miss judgment judgment circuit 13 receives the signals sent by the comparators, going from comparator 11 at level O to comparator 12 at level N. If all the signals coming from the comparators, from comparator il at level O to comparator N at level 12, have the logical value "O", it means that a failed hit of the cache memory is detected. On the other hand, if any of the signals transmitted has the logical value "1", it is that a successful hit of the cache memory is detected at the corresponding level.

If it is the cache miss which occurs, a miss signal MISS is sent to the control unit of the main memory unit MMU 17 via a line 49.

 The failed cache hit is subdivided into two cases. In the first case, although the bit V takes the logical value "1", the block address signals which are in the different comparators, from comparator ll of level O to comparator 12 of level N, are different from signal d block address from the address register 6. In the second case, all the bits V of the address sets 9-10 have the logical value "0", that is to say that the validity data does not are not saved in cache 18.

 The output signals from the different comparators, from comparator 11 at level O to comparator 12 at level N, are also sent to a circuit 14 for determining the level to be replaced, that is to say the level of the block to be replaced. assign new data when a missed cache hit occurs. It is usually the Least Recently Used (LRU) algorithm which has not been used for the longest period of time) which determines which level to replace.

In addition, the cache 18 with conservation of the stored data used in this embodiment is different from a cache without conservation of the stored data, in that the writing of the data (called swap, back and forth) from the cache 18 to main memory unit
MMU 23 takes place in the form of allocation of new data. s.

 An output signal, in the form of a control signal coming from the circuit 14 for determining the level to be replaced, is sent to a block address generator 15 located at the level to be replaced and to a circuit 16 for judging the replacement. The block address generator 15 located at the level to be replaced receives the block address signals from the address sets, from the address set 9 at level O to the address set 10 at level N , selects the block address signal from a given set of addresses designated as the level to be replaced and sends the selected block address signal to the controller 17 of the main memory unit MMU, by l line 56.

The replacement judgment circuit 16 receives as bits V and
M coming from the sets of addresses, from the set of addresses 9 of level O to set of addresses 10 of level N and selects the bits V and M of the given set of addresses designated as the level to be replaced. The selected bits V and M are sent to the control unit 17 of the unit MMU via a line 57. If the bit V of a block located at the level to be replaced has the logical value "O" , or if the bit V has the logical value "1" and if the bit M has the logical value "O" the back-and-forth operation (swap) is not performed. The block data transferred from the MMU 23 to cache 18 are assigned to the block at the level to be replaced.

On the other hand, if the bits V and M of the block located at the level to be replaced both have the logical value "1", the back-and-forth operation (swap) is carried out since it is the most recent data which are stored in cache 18.

 The signals sent to the control unit 17 of the MMU unit are a MISS signal (missed shot) coming from the circuit 13 for judging a successful shot / missed shot, via a line 49, a REPLACE signal ( to be replaced) coming from the judgment circuit 16 concerning the replacement, via line 57, of a block address signal located at the level to be replaced coming from the block address generator located at the level to be replaced, by through line 56, and a response signal from the main MMU memory unit from the MMU 23 through a line 58.

The signals coming from the control unit 17 of the MNU unit are a busy signal sent to the busy verification unit 4 via a line 35, read and write signals and the address signal (on the occurrence of a miss) sent to cache 18 via the corresponding lines 51, 52 and 53 and a request address signal in memory MMU and a request in memory
MMUs sent to the MMU 23 via the corresponding lines 59 and 60.

 The control unit 17 of the MMU unit will be described in detail below.

 The cache memory 18 comprises blocks ranging from level O to level N, generally each comprising approximately 64 bytes. A read / write address signal for the cache memory - 18 is sent by the address register 6 when there is a successful hit from the cache memory but sent by the control unit 17 of the MMU unit when 'a cache hit occurs. The address signals sent by the control unit 17 of the MMU are different from each other in block transfer mode and in back-and-forth mode (swap).

In this embodiment, a read / write data length corresponds to 8 bytes.

The data read / write operation is performed in block transfer mode and in back and forth mode by block units. The write data for cache memory 18 is supplied by data register 7 when successful 1 cache memory occurs. On the other hand, if a failed hit of the cache memory occurs, the block transfer data (8 bytes x 8) coming from the MMU 23 are sent via the register 8. An output signal coming from from cache 18 is sent to response registers A, B and C 19, 20 and 21 to store respectively the response data for units A, B and C. In back-and-forth mode (swap), the signal sent by cache 18 is sent to a register 22 in the form of data (8-bytesx 8).

In read request mode, the response registers A, B and C, 19, 20 and 21 receive a signal from cache 18 or a signal from register 8 via a path 55 and send the data response to units A,
B, and C as the source of demand, respectively.

The path 55 coming from the register 8 is provided to shorten the access time when a failed hit of the cache memory occurs. The path 55 is provided for memorizing in the cache memory 18 the data coming from the MMU 23 and at the same time for sending the response data to the request source.

In storage request mode, no response data is generated.

 Ol will describe the request operation of the memory access control member shown in FIG. 1 in the event of a missed shot of the cache memory.

(A) Read request without back and forth (swap)
A request to transfer a unit block
MMU 23 to cache 18 is generated. The block is assigned to cache 18 and at the same time the response data is sent, in feedback, to the request source.

(B) Swap read request
After the level block to be replaced from cache 18 is stored in the MMU 23, a block is transferred from the MMU 23 into cache 18. The block is stored in cache 18 and , at the same time, it is sent to the request source as response data. In read request mode with back and forth, the bits V and
M of the address set that includes the recently assigned level have the logical value "1" and "O", respectively.

(C) Memorization request without back and forth (Swap)
A request to transfer a block, from the MMU 23, to cache 18, is generated.

The block is allocated in cache 18.

(D) Memorization request without back and forth (Swap
The block located at the level to be replaced of the cache memory 18 is stored in the MMU unit 23. A block is transferred, from the MMU unit 23, to the cache memory 18 and it is allocated in the cache memory 18. In mode storage request without back and forth, the bits V and M of the set of addresses having a recently assigned level have all the logical values "1".

The characteristic attribute of the invention resides in that a processing of missed hit of the cache memory or processing of missed hit is carried out by a request to read in main memory MMU 23, independently of the presence / absence of the swap operation
Figure 2 is a circuit diagram of the controller 17 of the main MMU memory unit shown in Figure 1. Figures 3 (A) to 3 (N ') and 4 (A) to 4 (I ) are time graphs of the signals generated in the circuit shown in Figure 2. We will describe in detail the treatment of a failed shot with reference to Figures 2, 3 (A) to 3 (N) and 4 (A) to 4 (I).

 Referring to FIG. 2, a MISS signal (missed shot) sent via line 49 and representing a missed shot from the cache memory and a REPL signal (to be replaced) sent via line 57 and representing the presence of a replacement request are sent to a detector 100 of the back-and-forth operation (swap) and to a block transfer detector 110. If the MISS signal has the logical value "1", that is to say if there is detection of a missed shot. of the cache memory, and if the REPL signal has the logical value "1", that is to say if there is a replacement request, a signal of logical value "1" representing the presence of a back-and-forth operation (swap) is sent by the detector 100 of the back-and-forth operation. In this case, the treatment of the missed shot consists of the transfer of the block and the back-and-forth operation.

 If the signal MISS has the value "1" and REPL the value "0", a signal emitted by the detector 100 of the back-and-forth operation takes the logical value "0" and a signal emitted by the detector 110 block transfer takes the logical value "1".

In this case, the treatment of the missed shot consists only of the transfer of the block.

The signals emitted by the detector 100 of the back-and-forth operation and the block transfer detector 110 are sent to a member 130 for checking the occupancy of the MMU unit. The occupation verification unit 130 of the MMU unit performs an occupation verification, that is to say gives an output signal the logical value "1" (occupation verification signal) or " O "in accordance with an occupancy indicator of the MMU unit sent by the indicator register 120. If a previous request is subjected to a missed shot processing, the occupation verification signal cannot be sent. corresponding to the signal coming from the back-and-forth operation detector 110 and generated by the unit 130 for verifying the occupancy of the MMU unit is then sent to a generator 140 of occupancy signal by back-up operation and- ~~ comes and to a memory request generator 160
MMU, via a line 131. A signal corresponding to the signal sent by the block transfer detector 110 and generated by the device 130 for checking the occupancy in the MMU memory is sent to a signal generator 150 occupation by transfer of blo and to a generator 160 of request in MMU memory via a line 132.

The signals sent by the busy signal generator 140 by back-and-forth operation and by the busy signal generator 150 by block transfer are sent to the busy indicator register 120. If the previous request is submitted upon verification of occupancy and if the request in MMU memory 23 is generated, the occupancy indicator register 120 is validated and it is invalidated in response to the response data supplied by the MMU memory 23 via a line 58. In this embodiment, the occupancy indicator register 120 is invalidated in response to the response data from the memory MMU. However, the occupancy indicator register 120 can be invalidated by itself by monitoring a constant number of periods
T. The occupancy indicator register 120 sends the BUZY occupancy signal to the occupancy verification member 130. A new request from section 30 of the access registers can be deleted by the busy signal.

 When the occupancy indicator is disabled and the request is submitted to the occupancy check, a request command is sent to the memory MMU 23 in accordance with the presence / absence of the back-and-forth operation. - comes (swap).

Because different request commands are used in accordance with the presence / absence of the back-and-forth operation, the block transfer address signal is sent simultaneously to the memory MMU 23. We will describe below the operations with and without back-and-forth operation with reference to the timing graphs of Figures 3 (A) to 3 (N) and Figures 4 (A) to 4 (I).

(A) Operating mode with back-and-forth operation (Swap) (Figures 3 (A) to 3 (N))
The busy signal generator 140 by back-and-forth operation validates an occupancy indicator in the occupancy indicator register 120 and prohibits subsequent requests as shown in FIG. 3 (B).

in organ 170 for sequencing the back-and-forth operation in the cache memory sends, to a cache memory 18, a read signal RD (FIG. 3G), by a line 51, and a chronometric signal of address of back and forth operation, FIG. 3 (I), by a line 173 and by a selector 230. The member 170 for sequencing the back and forth operation in cache memory sends, to the unit main memory
MMU 23, a back-and-forth operation timing signal, via a line 172, and to a selector 220, in response to a back-up operation address request timing signal back and forth shown in Figure 3 (H). Consequently, the back-and-forth operation between the cache memory 18 and the main memory MMU 23 takes place. A block transfer sequencing device 190 sends a write signal WT (FIG. 3 ( K)) and a block transfer address signal to cache 18 in response to a timing signal following which the block transfer data from the memory
MMU 23 are returned as shown in Figure 3 (M). The sequencing members 170 and 190 consist of a shift register and the like.

(B) Operating mode without back-and-forth operation (Swap) (Figures 4 (A) to 4 (I))
The block transfer busy signal generator 150 validates a busy flag in the busy flag 120 and prohibits subsequent requests. A dummy cycle generator 180 performs a dummy operation to match the timing signals before starting the block transfer. The block transfer sequencing unit 190 sends a write signal WT and a block transfer address signal to the cache memory 18 at the moment when the block transfer data originating from the memory MMU 23 are returned.

 As described above, the above operation and the sending, to the request source, response data is performed simultaneously.

 In FIG. 2, the reference 200 designates a back-and-forth operation address generator which has the function of synthesizing a block address signal of the level to be replaced and a column address signal of the data address of the request.

Reference 210 designates a block transfer address generator. The request address signal sent over line 48 serves, without modification, as a block transfer address signal. The block address signal and the column address signal are sent to the MMU 23. Only the column address is sent to cache 18. The mark 220 designates a selector to send to the unit.
MMU 23 read / write signal. According to this embodiment, in normal operating mode, the selector sends the block transfer address signal.

 In operating mode with a back-and-forth operation, the selector 220 sends the back-and-forth operation address signal at a fixed chronometric instant. The reference 230 designates a selector for sending a read / write address for the cache memory 18. According to this embodiment, in normal operating mode, the selector 230 sends the block transfer address signal. In operating mode with the back-and-forth operation, the selector 230 sends the back-and-forth operation address signal at a fixed chronometric instant.

 In the embodiment described above, if a cache miss occurs and a back-and-forth operation is required, the read and write operations for the main memory unit can be made by a single request, thus simplifying the order.

 Figure 5 is a block diagram showing another embodiment of the invention. The same references as in FIG. 1 designate the same parts in FIG. 5 and the detailed description will be omitted.

 The arrangement of FIG. 5 differs from that of FIG. 1 in the sense that a write invalidity signal is sent by a control member 17 ′ from the MMU unit to the MMU unit by a line 61.

 The detailed arrangement of the control unit 17 'of the MMU unit shown in Figure 5 is shown in Figure 6. The same references as in Figure 2 denote the same parts as in Figure 6 and we will omit one detailed description.

The control unit 17 ′ of the MMU unit in FIG. 6 differs from the control unit 17 of the unit
MMU of FIG. 2 in the sense that a block transfer occupancy verification path 132, starting from the occupation verification member 130, is connected to a synchronization circuit 240 to generate the invalidity signal writing.

 The circuits of Figures 5 and 6 are summarized below.

When a busy check in memory
MMU occurs in the occupation verification member 130 which is part of the MMU memory control member 17 ′, the read and write requests are sent to the MMU memory 23. A generator 160 for requesting MMU memory simply has an OR gate. In this embodiment, simultaneously, a block transfer address signal is sent to the memory MMU 23. A block transfer occupancy signal is sent to the synchronization circuit. When a predetermined period of time has elapsed, the write invalidity signal is sent to the MMU memory 23. When the write invalidity signal is received by the MMU memory 23, this MMU memory 23 does not performs a block transfer in cache 18 only on receipt of a request.

 Figures 7 (A) to 7 (J) are time graphs of the signals of this embodiment.

Figure 7 (J) shows the write invalid signal.

 In this embodiment as described above, the write and read signals are simultaneously sent to the memory MMU 23 independently of the presence of a back-and-forth operation (swap). Only the write request previously sent is invalidated, thus simplifying the command upon the occurrence of a missed shot of the cache memory.

Claims (2)

 1. Memory access control system, comprising a cache memory (18) with storage of the stored data, connected between a request source and a main memory unit (23), characterized in that it comprises:  means (9-10) forming a set of addresses which presents a bit representative of the validity of a content of said cache memory (18) and a bit representative of a coincidence between the content of said cache memory (18) and of the 'main memory unit (23);  means (13) for judging a successful hit on a failed hit of said cache memory (18) in accordance with an output signal from the address set means (9-10);  means (14) for determining a level of said cache memory (18) to be replaced when a failed hit of the cache memory occurs;  means (16) for detecting the validity of the data of the block of the level to be replaced and for detecting a non-coincidence between the contents of said cache memory (18) and said main memory unit (23) in accordance with an output signal means (9-10) forming a set of addresses corresponding to the level to be replaced, and for judging the need to write the data of the block of said cache memory (18) in the main memory unit (23); and  means (17) for processing the write and read operations of the main memory unit (23) with a single request when the need arises to write to the main memory unit ( 23) the data of the cache block (18).  2. Memory access control system, comprising a cache memory (18) with conservation of the stored data, connected between a request source and a main memory unit (23), characterized in that it comprises:  means (9-10) forming a set of addresses which presents a bit representative of the validity of a content of said cache memory (18) and a bit representative of a coincidence between the content of said cache memory (18) and of the 'main memory unit (23);  first means (13) for judging a hit / miss from said cache (18) in accordance with an output from the address set means (9-10);  means (14) for determining a level of said cache memory (18) to be replaced when a failed hit of the cache memory occurs; ;  second judgment means (16) for detecting the validity of the data of the block of the level to be replaced and for detecting a non-coincidence between the contents of said cache memory (18) and said main memory unit (23) in accordance with a output signal of the means (9-10) forming a set of addresses corresponding to the level to be replaced, and for judging the need to write the data of the block of said cache memory (18) in the main memory unit (23) ; and  means (17 ') for simultaneously sending to said main memory unit (23) write and read requests from said first means (13) for passing judgment; and  means (17 ') for invalidating a previous write request which is one of the previous write and read requests from said determining means (14) and said second judgment means (16).