FR2605162A1 - METHOD AND DEVICE FOR ASSISTING THE ACQUISITION OF A PHASE LOCKED LOOP - Google Patents

Abstract

THE PROCESS CONSISTS OF USING A SAWTOTH SIGNAL OUTPUT FROM A LOW PASS FILTER OF A PHASE LOCKING LOOP, IN MULTIPLYING IT BY A LOW FREQUENCY SQUARE SIGNAL, INTEGRATING THE MULTIPLIED SIGNAL OBTAINED, TO OBTAIN A SIGNAL SCAN AND TO BE CONTROLLED BY THE SCAN SIGNAL, AN OSCILLATOR CONTROLS THE VOLTAGE OF THE PHASE LOCKING LOOP. THE DEVICE INCLUDES A MULTIPLIER 7 AND A LOW FREQUENCY GENERATOR 8; IT MAY ALSO HAVE BEFORE THE MULTIPLIER, A HYSTERESIS COMPARATOR 5 AND A HIGH PASS FILTER 6; THE MULTIPLIER 7 IS CONNECTED AT OUTPUT S7 TO A LOOP FILTER 3 OF THE SAID LOOP, FOR INTEGRATION OF THE MULTIPLIED SIGNAL.

Description

Method and device for assisting the acquisition of a locking loop

phase

  The present invention relates to the field of locking loops.

  phase and, more particularly, a method and a device for assisting the acquisition allowing faster looping of the loop.

  and in a wider frequency range.

  In the context of the transmission of digital data at very high speed, it is necessary to periodically regenerate, amplitude and phase, the signal. For this, the clock is necessary and it must be extracted from the transmitted data, which poses a problem of delicate filtering when

  the codes used are of the NRZ or RZ type because there are few transitions.

  Apart from passive filtering devices, such as surface wave filters for example, phase locked loops are used. In this application, which consists in isolating a spectrum of a particular frequency component, the loops are said to be narrow (small pulsation small in front of the central pulsation), which

  leads to a weak attachment band and a long hanging time.

  To overcome these drawbacks, several devices are known: Use of a voltage controlled crystal oscillator which allows a central frequency accuracy sufficient to be in all cases inside the fastening strip. The snap time is short since the initial frequency difference is small. But the use of quartz at high rates (above 34Mbit / s) implies costs

  high and furthermore does not exclude any setting.

  Addition to the initial phase locked loop of a frequency locked loop. Such a system is described in French Patent 2,322,490 of August 19, 1977: circuit for correcting synchronization errors. It generates an error voltage, proportional to the frequency difference between input and output, which is used to

  perform the frequency snap. This device leads to a realization

  complexity and delicate phase adjustments.

  Another method is to use an external tooth generator of

  whose output is added to the control voltage of the oscillator

  controlled voltage transmitter. The frequency 2 of this is then scanned; passing through the snap is detected using a second phase comparator, working in quadrature with the first, a low-pass filter and a level comparator. The hanging is reflected

  at the output of the second phase comparator by the appearance of a composition

  Continuous health detected by the low-pass filter and the level comparator, it then removes the scan saw tooth. This device requires a large number of external components and more

  does not have a high immunity to the jitter of the input signal.

  The object of the invention is to overcome the drawbacks of known solutions, and to obtain a device for simple realization and implementation.

easy work.

  The subject of the invention is a method of assisting the acquisition of a phase-locked loop receiving an input signal of frequency f1 and comprising a phase comparator, a low-pass filter, a loop filter and a voltage-controlled oscillator delivering a frequency signal f2 before hooking, said low-pass filter

  delivering to the slug filter a sawtooth signal of frequency f1-

  f2, characterized in that said sawtooth signal is shaded out of the phase-locked loop by a hysteresis comparator, and the shaped signal is filtered for elimination of the lower frequencies. at a capture frequency of the phase-locked loop, that a multiplication of the signal thus filtered by a low frequency square signal is performed to obtain a multiplied signal, that said multiplied signal is integrated in order to obtain a scanning signal as long as the acquisition is not obtained, and that said oscillator is controlled by said scanning signal to vary the frequency thereof, said scanning signal having a frequency equal to that of said low frequency signal and passing linearly from a value

  positive peak at a negative peak value and vice versa.

  The invention also relates to a device implementing the method of the invention, and comprising a hysteresis comparator, a high-pass filter, a multiplier, and a low-frequency square-wave signal generator, the hysteresis comparator being connected in output of the low-pass filter of the phase-locked loop, the filter

  high-pass being connected at the output of the hysteresis comparator, the multi-

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  Binder having an input connected at the output of the high-pass filter, an input connected at the output of the generator and an output connected to the filter of

  loop of said phase locked loop.

  A phase-locked loop receiving an input signal is conventionally constituted by a phase comparator, a low-pass filter, a loop filter and a voltage-controlled oscillator, the low-pass filter delivering a signal to the loop filter. serrated. According to the invention said sawtooth signal is, outside the phase-locked loop, multiplied by a low-frequency square signal, and the signal obtained by multiplication is

  integrated to obtain a scan signal that is applied to the oscilla-

  to vary the frequency between two extreme values.

  When the latching of the phase locked loop is obtained, the scanning signal disappears; however, to avoid after latching that during a jitter of the input signal, or when the input signal has a long sequence of "0" or "1", a scan signal appears, the signal in teeth of saw shaped by a hysteresis comparator, before multiplication. Finally, again according to the method, the signal resulting from the comparison is filtered in order to eliminate the frequencies lower than the capture frequency of the loop.

phase lock.

  The method of the invention is implemented in a device for assisting the acquisition of the phase-locked loop; this device has the following advantages;

  - The collision is reached, the aid for acquisition is totally

  inhibited and therefore does not disturb the functioning of the

  phase locked loop only.

  - It is fully integrable and requires the addition of a small number of elements to the initial phase locked loop. We

  thus minimizes additional consumption.

  - The external components are traditional so low cost (no

  quartz or surface-wave filter).

  - No adjustment shall be made when putting into service the

  tif. - It is likely to be able to extract the clock signal from a signal

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  - 4 - binary having long "0" or "1" sequences and disturbed by a

significant jitter.

  The invention will be well understood in the following description

  an exemplary embodiment illustrated by the appended figures in the

  which: - Figure 1 is a diagram of a device of the invention, - Figure 2 shows the appearance of different signals at various points of the device of Figure 1,

  FIG. 3 is a diagram of certain members of FIG.

  FIG. 1 represents a BVP phase-locked loop,

  conventional and a DA acquisition aid device of the invention.

  The phase lock loop BVP comprises a phase comparator 1 having a triangular, sawtooth characteristic (of the exclusive OR type) having a first input E 11 which receives an input signal E, a low-pass filter 2 having an input connected at the output of the phase comparator, a loop filter 3 having a first

  input E 31 connected to the output S2 of the low-pass filter 2, and an oscillator-

  4, voltage controlled, having an input connected to the output S3 of the loop filter 3 and an output S4 connected to a second input E 12 of the phase comparator 1; the output S4 delivers an output signal S. The acquisition aid device DA comprises a hysteresis comparator 5 connected at input to the output S2 of the low-pass filter 2, a high-pass filter 6 having an input E6 connected in output of the hysteresis comparator 5, a multiplier 7 with two dials and a generator 8 of low frequency square signals of period T, the multiplier 7 having a first input E 71 connected at the output S6 of the high-pass filter 6, a second input E 72 connected to the output S8 of the generator 8, and a

  output S7 connected to a second input E 32 of the loop filter 3.

  We will now give the operation of the PLL phase lock loop assembly and DA acquisition aid device, assuming firstly that the phase lock flask is open between the loop filter 3 and the control unit. oscillator 4. The input signal E has a frequency f1 and the output signal S has a frequency f2, different

of fl.

  The phase comparator 1 delivers a signal comprising the

  -5 s sum sum fl + f2 frequencies, and difference fl - f2 frequencies; for example if the frequency fl is greater than the

  frequency f2, the sum f1 + f2 is eliminated by the low-pass filter 2.

  As a result, the output signal S2 of the low-pass filter is the image of the characteristic of the sawtooth signal delivered by the comparator.

  phase 1, that is to say a triangle of frequency f1-f2 and ampli-

  A. The hysteresis of the hysteresis comparator 5 is adjusted to a value A-ú slightly lower than A so as to trigger on the

  signal delivered by the low-pass filter. At the output of the hysteresis comparator

  resis therefore at the input E6 of the high-pass filter is obtained a square signal of low level 0 and high level A, always of frequency f1-f2, shown in FIG. 2, which is transmitted at the output S6 of the high-pass filter 6

  which is supposed to be transparent at the frequency fl - f2. The multi

  Folder 7 receives on its first input E71, unipolar, the signal delivered by the high-pass filter 6 on its output S6, Figure 2, and on its

  second input E 72, bipolar, a square signal delivered by the general

  8 at the output S8, FIG. 2, said square signal having a frequency 1 / T chosen small in front of the capture frequency of the phase-locked loop; this capture frequency is the maximum frequency deviation from which the latching is performed without phase jump, and therefore without triggering the hysteresis comparator 5. Other

  the square signal delivered by generator 8 consists of

  positive and negative, the sign of the voltage of this signal changing with each tilting of the square signal. Consequently, the signal delivered by the output S7 of the multiplier and represented in FIG. 2 is: square, of low level O, of high level I, of frequency fl - f2 during the positive half cycle of the signal delivered by generator 8, and square of

  low level -I, high level 0 and frequency fl - f2 during the alter-

  The signal delivered by the multiplier 7 is then integrated by the loop filter 3, as will be explained below. At the output S3 of the loop filter, the delivered scanning signal is constituted, as represented in FIG. 2, by a ramp of positive slope of amplitude + U corresponding to the integration of the positive part of the signal on the output S7 of the multiplier, then by a ramp of negative slope of amplitude -U corresponding to the integration

2605 1 6 2

  -6- the negative part of the signal on the output S7; the signal delivered by the loop filter 3 is therefore a triangular voltage of period T,

  passing through the value O in the middle of each positive and negative ramp.

  Oscillator 4, which is voltage-controlled by the scanning signal delivered by the loop filter, is thus scanned linearly.

  frequency when the loop is closed. -

  The frequency difference between the signals delivered by the outputs S6 and S8, FIG. 2, is in fact much greater than the one represented

  in this figure, but the operation remains obviously the same.

  Similarly, the scanning signal delivered by the output S3, FIG. 2, should have a step-stair step, each step corresponding to the integration of a signal pulse on the output S7, but the frequency difference is big plus the steps are small. It can therefore be considered that the scanning signal varies linearly between + U and - U. It will be observed that the loop filter 3 also receives the sawtooth signal delivered by the low-pass filter 2, and that this signal is superimposed, at the output S3 of the loop filter, at the scanning signal; the level of this sawtooth signal, of frequency f1 - f2, being much lower than that of the scanning signal, it has not been

  Figure 2. It should be noted, however, that after the

  the scanning signal is deleted, as explained below.

  after that, and that only the sawtooth signal remains, this signal being

  that of the phase locked loop in normal operation.

  We will now describe the operation in closed loop. At the initial moment of closing the loop is not hooked; therefore the frequencies of the input signals E and output S are

  different, which corresponds to the case described previously. The comparison

  phase 1 delivers a sawtooth signal at the beat frequency fl - f2 between the frequency f1 of the input signals and the

  frequency f2 of the output signal. As indicated above, the

  tif help DA will generate, from the sawtooth signal, issued by the low-pass filter 2 which is the image of the sawtooth signal delivered by the phase comparator 1, a signal which is applied to the loop filter 3, which delivers the scanning signal controlling the oscillator 4. At the output S3 of the loop filter, at the signal

2605 1 6 2

  The scanning signal is superimposed on the signal delivered by the low-pass filter 2, on its output S2, which is the natural latching signal of the phase-locked loop BVP; but as long as the frequency difference fl - f2

  is greater than the capture band, the scan signal is preponder-

  rant and intervenes alone. Conversely, at the moment of the passage inside the capture band the phase jumps disappear and therefore the signal

scan also disappears.

  So, at output S3 of the loop filter, there remains only the natural snapping signal which will lead to synchronism very quickly since the operation is in the capture band. Whatever

  the initial frequency deviation, the snap time will therefore be less than

  3 T / 2, where T is the period of the low frequency square wave generator 8. This maximum time corresponds to a jump between the two extreme operating frequencies occurring just after a

switching of the generator 8.

  Indeed, at the next switchover, when the voltage of the square signal changes sign, the scanning signal will not have reached the extreme frequency since the scanning is constant slope and it has lasted less than T / 2; it will then be necessary to wait for a new

  period of the scan signal to get the snap.

  FIG. 3 represents the loop filter 3, the filter

  high pass 6 and the multiplier 7 with two dials.

  The high-pass filter 6 comprises a capacitor C3 between its input E6 and its output S6 and a resistor R5 between the output S6 and a

negative voltage -V.

  The multiplier 7 comprises seven transistors Q1 to Q7 and a

  resistance R6. The transistors Q1, Q2, Q3 are of the NPN type, the transistors

  Q4 to Q7 being of the PNP type. The transistors Q2 and Q3 are connected by their emitter and a point common to these emitters is connected to the collector of the transistor Q1, whose emitter is connected by the resistor R6 to the negative voltage -V; the base of transistor Q1 is connected to

the input E 71 of the multiplier.

  The base of the transistor Q2 is connected to an input E 72a of the multiplier and the base of the transistor Q3 is connected to an input E 72b; the inputs E 72a and E 72b constitute the input E72 of FIG. 1,

2605 1 6 2

  - 8 - this entry being two-wire. The collector of transistor Q2 is connected to the collector of transistor Q5, and the collector of transistor -Q3 is connected to the collector of transistor Q6. Transistors Q4 and Q5 are

  connected by their base and a common point to these bases is connected to the

  transistor Q5. The emitters of transistors Q4 and Q5 are connected to a + V positive voltage. The transistors Q6 and Q7 are connected by their base and a point common to these bases is connected to the collector of the transistor Q6. The emitters of transistors Q6 and Q7 are connected to the positive voltage + V. The collector of the transistor Q4 is connected to an output S7a of the multiplier and the collector of the transistor Q7 is connected to an output S7b of the multiplier; these two outputs S7a and S7b constitute the output S7 of Figure 1, which is two-wire. Positive voltages + V

  and negative -V are those of a continuous supply.

  The loop filter 3, of known type, comprises an operational amplifier AO, four resistors R1 to R4 and two capacitors C1 and C2. The operational amplifier has an output connected to the output S3 of the loop filter, a negative input connected on the one hand to the output

  by a series circuit constituted by the resistance R2 and the condensation

  C1 and other -part to an input terminal E 31a by a resistor R1, and a positive input connected on the one hand to another input terminal E 31b by the resistor R3 and on the other hand to the mass by a series circuit consisting of the resistor R4 and the capacitor C2. The inputs E 31a and E 31b constitute the input E 31 of FIG. 1, which is two-wire. A point common to the resistor R2 and the capacitor C1 is connected to an input E 32a itself connected to the output S7a of the multiplier; a point common to the resistor R4 and the capacitor C2 is connected to another input E 32b itself connected to the output S7b of the multiplier; the inputs E 32a and E 32b of the loop filter 3 constitute the input E 32 of FIG. 1, which is bifilar. The resistors R1 and R3 have even

  value, the resistors R2 and R4 have the same value, and the condensations

  C1 and C2 have the same value, C1 = C2 = C. In the latching phase the voltage at the input E6 of the high-pass filter 6 is a square signal of amplitude A; after passing through the high-pass filter formed by the capacitor-C3 and the resistor R5, the output S6 of the high-pass filter has the same signal centered on the negative voltage -V of the power supply; this signal is applied to the transistor Q1 which forms with the resistor R6 a controlled current source. When the signal at the output S6 is high, the collector current of the transistor Q1 has a value I which is a function of the resistor R6, and when the signal at the output of S6 is at low level the transistor Q1 is blocked, and the current is zero. Transistors Q2 and Q3 constituting a differential pair controlled by the voltage from the generator 8 of low frequency square signals; this voltage being alternately positive and negative, as represented in FIG. 2, at S8, the current of transistor Q1 is switched alternately towards the

  collector of transistor Q2 or the collector of transistor Q3; in different

  Therefore, at the output S7 of the multiplier 7, the signal represented in FIG. 2 has amplitudes I and I. The transistors Q4 and Q5 on the one hand and Q6 and Q7 on the other hand constitute two current mirrors of way

  to attack the loop filter 3 without saturating the transistors Q2 and Q3.

  The loop filter 3, of the integral type, behaves with respect to the integrator current; the voltage V (S3) at the output of the loop filter is: V (S3) = C i (t) dt

  i (t) being the differential current, and C = C1 = C2.

  The role of the high-pass filter 6 is given below.

  When the latching is reached, the output of the hysteresis comparator can, according to the sign of the initial frequency difference fl - f2, be in the high state. In this case the transistor Q1 remains on and continues to feed the loop filter, which disturbs the

  operation. The presence of the high-pass filter 6 brings, with some

  In this case, the base of the transistor Q1 has a negative potential V, which blocks it. The time constant must be chosen so as to pass the capture frequency of the loop, this capture frequency being the minimum frequency appearing at the output of the hysteresis comparator 5, but also so as to block the transistor Q1 and thus to stop the saw tooth of the scan signal

2605 1 6 2

- 10 -

  before it comes out of the capture range.

  The interest of the hysteresis comparator is as follows. In function

  Normally the signal E at the input of the phase locked loop receives a random digital signal having a certain jitter. The high frequency parts of the jitter will be demodulated by the loop and transmitted on the error signal, which is the output signal S2 of the low-pass filter 2. If the comparator 5 was a simple comparator, it would trigger and cause therefore the stall; on the other hand, the hysteresis comparator will only trigger if the jitter amplitude exceeds A- ú, the predetermined value of the hysteresis. The maximum jitter, G max, admissible at high frequencies is: G max = (A) = 0.5 T1 g1 being the gain of the phase comparator and equal to A / Tf for an OR

  exclusive and T1 the period of the frequency input signal fl.

  Likewise, the random nature of the input signal E, and more particularly

  In particular, the long "O" and "1" sequences result in the output of the phase-1 comparator by decoding; again, the hysteresis

  solves the problem and avoids stall.

  With an input signal E at 100 MHz and a phase-locked loop constituted by: an exclusive phase-exclusive OR phase comparator of type F 100 107 of gain gl = 0.5 V / radian, a low-pass filter of the RC type of 30 MHz cut-off frequency, a loop filter of time constants R1 C = 4.5 ms and R2 C = 0.224 ms, and a controlled oscillator in gain voltage g3 = 7 MHz / V, the following results are obtained: the loop alone has a noise band of 100 kHz and amplitude

  maximum jitter G max = 1.01; it is therefore adapted to a recovery

  rhythm; the capture band is 280 kHz, the maximum coupling time corresponding to a frequency jump of 6 MHz being 300 ms; jumps

  larger ones lead to stall.

  To the above phase locked loop, the arrangement

  of the invention constituted by: a hysteresis comparator consisting of a looped fast comparator, the hysteresis value being

- 11 -

  set at 700m V, a high-pass filter with a cut-off frequency of 36 MHz, a two-dial multiplier with a gain of 2.7 m A / V2, and a generator

  low frequency period T = 15 ms.

  The capacitors C1 and C2 of the loop filter have a value of 1 microfarad; accordingly, the scan signal has a peak-to-peak amplitude of 4 volts and a period of 15 ms; the frequency range

  swept by the oscillator is 493 = 28 MHz.

  The following results are obtained with the device: the loop clings on frequency hops of 20 MHz in less than 23 ms; the maximum jitter G max admissible is 0.35 T1 (T1 being the period of the input signal), which is comparable to the figures obtained with

other systems; -

  - the maximum number of consecutive "0" allowed in the signal of

  is 450 on a pseudo-random sequence of length 215-1,

what is excellent.

  These results show that the device for assisting the acquisition of the invention associated with a phase-locked loop allows a recovery rate much better than that obtained by the locking loop alone; a gain of at least twenty is possible over time

  hanging compared to a single loop.

- 12 -

Claims (4)

CLAIMS:   1 / A method of assisting the acquisition of a phase-locked loop receiving an input signal of frequency f1 and comprising a phase comparator, a low-pass filter, a loop filter and a voltage-controlled oscillator and delivering a signal of frequency f2 before latching, said low-pass filter delivering to the loop filter a sawtooth signal of frequency f1-f2, characterized in that it shapes, outside the loop to phase-locking, said sawtooth signal by a hysteresis comparator, which filters the shaped signal to eliminate frequencies below a capture frequency of the phase-locked loop, which is performed multiplication of the signal thus filtered by a low frequency square signal to obtain a multiplied signal, which is integrated into said   multiplied signal to obtain a scan signal as long as the   tion is not obtained, and that said oscillator is controlled by said scanning signal to vary the frequency thereof, said scanning signal having a frequency equal to that of said low frequency signal and linearly passing a positive peak value at a peak value negative and vice versa.   2 / A method according to claim 1, characterized by the fact that   the multiplied signal is integrated by the loop filter.   3 / Device for assisting the acquisition of a phase-locked loop (BVP), implementing the method according to claim 2, characterized in that it comprises a hysteresis comparator (5), a filter high pass (6), a multiplier (7), and a generator (8) of low frequency square signals, the hysteresis comparator (5) being connected at the output of the low-pass filter (2) of the locking loop of phase, the high-pass filter (6) being connected at the output of the hysteresis comparator, the multiplier (7) having an input connected at the output of the high-pass filter, an input connected at the output of the generator (8) and a connected output to the loop filter (3) of said phase locked loop.   4 / A device for assisting acquisition according to claim 3, characterized   in that the high-pass filter (6) is constituted by a capacitor (3) connected between an input (E6) and an output (S6) of said 2605 1 62 - 13 -   high-pass filter and a resistor (R5) connected between said output (S6) and a negative voltage (-V), and that the multiplier (7) comprises a first current mirror (Q4, Q5) a second current mirror ( Q6, Q7) each connected to a positive voltage (+ V), a differential circuit consisting of two transistors (Q2, Q3) each having a base connected to the output of the generator, each transistor being connected to a current mirror, said differential circuit also being connected by a third transistor (Q1) and a resistor (R6) in series to said negative voltage (-V), said third transistor (Q1) having a base connected to said output (S6) of the high-pass filter (6); ), and each mirror   connected to the loop filter (3) of the lock bolt. phase.