FR2600808A1 - Memory plane with fast read-out - Google Patents

Abstract

The present invention relates to a memory plane comprising a large number of memory slots each of which is associated with the intersection of a word line (WLi) and a bit line (BLj). According to the invention, there is furthermore provision for: - an extra bit line (BLSI) of the same structure and geometrical shape as each of the bit lines but comprising an actual memory slot at each intersection of a word line, and - comparators (AI... Ap) whose first inputs (-) are together connected up to the extra bit line and whose second inputs (+) are connected up respectively to an output (SI... Sp) of a bit line. Application to increasing the read-out speed of ROM memories.

Description

FAST PLAYBACK MEMORY PLAN
The present invention relates to the field of memories and more particularly that of semiconductor memories. Its advantages and characteristics will be explained in more detail in relation to read only memories (ROM) but it will be noted, as will be explained in more detail below, that it also applies to other types of memories.

 FIG. 1 generally represents a conventional ROM memory and FIG. 2 illustrates an example of a ROM memory point.

FIG. 1 represents more particularly the general organization of a conventional ROM or ROM map which comprises word lines WLi ... WLi ... WLn and bit lines BL1,
BL2, BL3, BL4 ... BLj ... BLq.

 By construction, the memory plane is characterized, at the intersection between each bit line and each word line, by the presence or absence of a switch such as the one represented in FIG. 2 which consists of a MOS transistor Tij at the intersection of the word line WLi and the bit line BLj.

This MOS transistor has its drain connected to the bit line, its source connected to a reference voltage such as ground and its gate connected to the word line WLi. So, in the event that a transistor
Tij is present at the intersection of the word line WLi and the bit line BLj, when the word line WLi is set high, the transistor is made conductive and the potential of the line BLj (which was previously preloaded ) fall to the potential of the reference voltage. Of course, in the absence of a transistor, the potential on the bit line BLj does not vary regardless of the value of the signal on the word line WLi. In FIG. 1, the presence of a transistor Tij at the intersection of a bit line and a corresponding word line is symbolized by a cross.

Returning to FIG. 1, it will be noted that the different word lines WL1 ... WLi ... WLn are connected to decoders
D1 ... Di ... Dn allowing, as a function of upstream logic signals (not shown), to activate at a given instant one of the word lines WL1 ... WLn. The bit lines are conventionally grouped by subset, for example four by four in the example shown, the line groups BL1 to BL4 ... BL (q-3) to
BLq being respectively connected to MUX 1 ... multiplexers

MUX p, with p = 4q. These multiplexers receive an input signal (CdMUX) making it possible to simultaneously activate one of the corresponding bit lines connected to each of these multiplexers, for example the lines BL1, BL5 ... BL (q-3). A precharge device, PR1 ... PRp, is associated with each of the multiplexers to precharge one of the bit lines of each group immediately before the actuation of one of the decoders; these precharging devices are controlled by a signal called Cd PRECH. Thus, when a decoder, for example the decoder Di, is actuated, a line of words WLi will be activated and all the lines BL1, BL5 ...

BL (q-3) will be analyzed; depending on whether or not there is a ground connection switch at the corresponding crossing point, the outputs Si ... Sp of each group of bit lines will obtain a state characteristic of whether or not there is a setting switch to ground. In other words, the bit lines comprising at the crossing with the word line WLi a MOS transistor will pass at low level while the bit lines not comprising at these crossing points of MOS transistor will remain at high level.

In practice, this transition from high level to low level of a bit line takes place with a certain time constant linked to the fact that the switches, for example a transistor
MOS Tij, have a certain drain / mass capacity and a significant resistance linked to their small size. Thus, the descent of a bit line from the high precharge level to the reference voltage is relatively slow. Therefore, amplifiers (not shown) connected to the outputs of lines S1 to Sp will not be able to provide very quickly an indication of the change in the state of a set of bit lines following the actuation of a word line decoder.

 An object of the present invention is to allow an acceleration of the read speed of a read only memory.

 To achieve this object as well as others, the present invention provides for processing in a particular way the outputs of each group of bit lines by carrying out a differential reading with respect to a signal varying with the signal on each bit line according to a relationship. determined.

 More particularly, the present invention provides a memory plane comprising a large number of memory points, each of which is associated with the crossing of a word line and a bit line, to supply memory signals on a plurality of bit lines in response to the presence of an address signal on a word line and to the state of the corresponding memory points. This memory plan also comprises: an additional bit line of the same structure and geometric shape as each of the bit lines but comprising an effective memory point at each crossing with a word line, and comparators whose first inputs are connected together to the additional bit line and the second inputs of which are respectively connected to an output of a bit line.

 Other objects of this. invention and in particular its application to the simplification of the structure of random access memories (RAM) while maintaining the same reading speed will be explained below.

These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of a particular embodiment made in relation to the attached figures, among which
FIG. 1 represents in general the structure of a read only memory (ROM) plane of the prior art
FIG. 2 represents a conventional memory point of a read only memory;
FIG. 3 represents a memory plane structure according to the present invention
FIG. 4 represents a diagram of voltage variation as a function of time, useful for explaining the operation of the memory plane according to the invention; and
Figures 5 and 6 show details of variants of the memory plane structure according to the present invention.

 In the various figures, the same elements are designated by the same references.

Thus, in FIG. 3 which illustrates a memory plane according to the present invention, there is the memory plane with its word lines WL1 ... WLn and its bit lines BL1 ... BLq as well as the word decoders D1 .. Dn, the bit line multiplexers MUX1 ... MUXp and the precharge circuits PR1 ... PRp. -
To this system, is added an additional bit line BLS1 of the same arrangement and constitution as the various bit lines BL1 to BLq but which includes a switch (an MOS transistor) at each of the crossing points with a word line. Thus, the capacity with respect to the mass of this additional bit line BLS1 will be equivalent to the maximum possible capacity of a normal bit line. Indeed, in a normal bit line, there will never exist a switch (a transistor) at each crossing with a line of words. The outputs of the multiplexed bit lines (S1 to Sp) are connected to a first input (+) of comparators Al ... Ap acting as polarity detectors, the second inputs (-) of which are connected to the output SS1 of the line of additional bits BLS1. There is thus obtained, at the outputs SA1 ... SAp of the comparators Ai ... Ap, a signal resulting from a differential reading which allows, as will be explained below, a much more precise and much faster detection of changes in level on the bit lines.

 FIG. 4 represents the variations in function # of the time of the voltages at various points of the memory plane of FIG. 3. If, at an instant t0, a decoder Di is actuated, the voltage on the word line WLi starts to increase between a zero level and the high voltage level of the circuit, for example the VDD precharge level. It is only after a certain delay, at an instant tl-, that the MOS transistor Tij existing at a crossing point ij will become conductive. The voltage on the corresponding bit line BLj will begin to fall from this instant t1 towards the ground level in a way which is considered to be substantially linear for the sake of simplification.

This voltage drop line BLj has been drawn in a hatched area which corresponds to more or less rapid voltage drops depending on whether the bit line # BLj considered comprises more or less active crossing points (provided with a transistor) . On the other hand, the voltage on the additional bit line BLS1 will drop more slowly because this line comprises a maximum capacitive load, all of its crossing points being effectively associated with a transistor. Thus, between the + and - terminals of the corresponding comparator A, we will see a positive or negative voltage difference, + dV2 or -dV1 depending on whether the crossover point ij included or not a transistor. This possibility of detection using of a comparator with a positive or negative difference value makes it possible to achieve high sensitivity and therefore to detect very quickly after time tl whether the crossing point ij was active or not (memorization of an l or of a 0).

 On the other hand, in the prior art, it was simply examined on the outputs S1 ... Sp whether the voltage remained at the preload level VDD or fell with respect to this preload level. Such a voltage detection according to a given polarity made it necessary to wait much longer before being able to make a detection. For example, we would have been obliged, instead of detecting at time t2 to wait for time t3 for which a sufficient voltage variation dV3 has appeared. In practice, it was necessary to wait for voltage variation values of the order of a volt corresponding to the detection threshold of an MOS detector (FIG. 4 is not to scale).

 It is by a digital example, with a ROM memory in CMOS technology, with a channel length of two micrometers and with a capacity of 16 kbits, that the advantages of the invention will be better seen. According to the present invention, as in the prior art, the duration between the instants t0 and tl is of the order of 20 ns. On the other hand, according to the present invention the duration between the instants tl and t2 is of the order of 10 ns while the duration between the instants tl and t3 for a conventional reading was of the order of 40 ns. Thus, the total reading time according to the present invention drops to 30 ns compared to 60 ns in the prior art.

 For the system according to the present invention to function satisfactorily, it is first of all necessary that the preload levels on all the bit lines and the additional bit line are identical. For this, we will use as was already known in practice, and as shown in FIG. 5, precharge transistors Tl ... Tp connecting during the precharge all the bit lines including the additional bit line to others. Of course, this connection is made by means of the multiplexers in the case illustrated in FIG. 5.

 On the other hand, all the amplifiers Ai to Ap should be synchronized suitably for reading, that is to say between the instants tl and t2. For this, an additional second bit line BLS2 (see FIG. 3) can be added similar to the other bit lines but with a lower time constant (instead of having a stronger time constant like the line BLS1). The appearance of a voltage drop on the SS2 output of the BLS2 line serves as a synchronization signal to VALEC synchronization inputs of the amplifiers Ai to Ap and this can be done via a simple inverter (not referenced ). Obtaining this lower time constant can result from an appropriate choice of the shapes of the transistors arranged at the crossing points.

 In FIG. 3, no connection has been shown between each word line and the additional bit lines, which could have been done. Instead, an additional word line WLS has been provided, associated only with the additional bit lines BLS1 and BLS2 and with a decoder DS operated each time one of the decoders D1 to Dn is selected. In this case each of the additional bit line transistors will have its gate connected to its source (the reference voltage).

This arrangement also makes it possible, as shown in FIG. 6, to simply ensure the existence of a threshold on the first additional bit line to avoid cases where the voltages would drop very quickly on this line (case of a memory of small dimension). This threshold is ensured by the prediction, at the crossing point between the additional bit line BLS1 and the additional word line WLS, of a transistor
Additional MOS TST in addition to the normal MOS transistor TSO at this crossing point. Thus, the voltage on line BLS1 cannot drop below the threshold voltage of a MOS transistor (approximately 1 volt).

 The present invention is not limited to the embodiments described. For example, the present invention has been explained above in relation to ROM memories where it finds a fundamental application for increasing the speed of reading without greatly complicating the structure of a ROM memory.

 The present invention, that is to say the provision of an additional bit line to ensure differential reading with each of the normal bit lines of a memory plane, could also be used in relation to random access memories (RAM). ). In this application, the present invention does not seek to increase the reading speed of a RAM memory but to maintain this reading speed by greatly simplifying the structure of the RAM memory.

 Conventionally, in a RAM memory, each memory point is associated with two complementary bit lines which are in reverse states, these two bit lines being generally used in writing for writing information into a memory point. However, it is known that it is possible to write information into a memory point using a single line of bits, for example by providing asymmetric memory points.

It is clear that then the writing speed is generally slower. However, in certain applications, it is not necessary to have a very fast writing speed (in the case of a memory containing a program or controlling an interconnection network), and in other applications it is desirable to reduce the number of wires per column (case of dual access memories). It is then possible according to the present invention to delete every other bit line and to add a single additional bit line which is equivalent to each complementary bit line and has a higher capacitive characteristic, for example because it is connected to all the comparators while a normal bit line is connected to only one. This additional bit line will serve as a reference to allow differential reading of the output of the various bit lines.

The reading speed is thus preserved by reducing the surface of the RAM memory.

Claims (7)

 1. Memory map comprising a large number of memory points, each of which is associated with the crossing of a single line of words (WLi) and a single line of bits (BLj), to supply memory signals (S1 ... Sp) on a plurality of bit lines in response to the presence of an address signal on a word line and to the state of the corresponding memory points, characterized in that it further comprises  - an additional bit line (BLS1) of the same structure and geometric shape as each of the bit lines and comprising. an effective memory point at each crossing of a line of words, and  - comparators (Ai ... Ap) whose first inputs (-) are connected together # to the additional bit line and whose second inputs (+) are respectively connected to an output (S1 ... Sp) of a bit line.  2. Memory map according to claim 1, characterized in that the memory points are the memory points of a memory ROM.  3. Memory map according to claim 2, characterized in that each memory point is constituted by the presence or absence of a controlled switch (Tij), a main terminal of which is connected to the bit line (BLi), of which l the other main terminal is connected to a reference potential and the control terminal of which is connected to the word line (WLi) of the corresponding crossing.  4. Memory map according to claim 3, characterized in that it further comprises an additional word line (WLS) associated with the additional bit line (BLS1), this additional word line # being activated each time a word line is activated.  5. Memory map according to any one of claims 2 to 4, characterized in that it comprises precharging means before reading (PR1 ... PRp) for each bit line or group of bit lines and means for interconnect the bit lines during the preload phases.  6. Memory map according to any one of claims 1 to 5, characterized in that it comprises a second additional bit line of time constant lower than the other bit lines, according to a determined relationship, and providing synchronization signals of reading (VALEC).  7. Memory map according to any one of claims 4 to 6, characterized in that the first additional bit line (BLS1) comprises means (TST) to prevent it from going below a predetermined voltage level understood- between the precharge voltage and the reference voltage.