FR2591364A1 - Device for evaluation, by measurement, of the performance of a computer system - Google Patents

Abstract

The invention allows evaluation of the performance of the hardware and software of a computer system (level of test activity, level of processor activity, interdependence between tasks, hardware response time etc.). The device according to the invention is an entirely-programmable hardware device which is connected, on the one hand, at A5 onto the bus of the system to be investigated, without altering its operation, and, on the other hand, at A1 onto an external computer, which stores the information originating from the invention, and analyses it, with a view to evaluating the performance of the system to be investigated. The device which is the subject of this invention consists of a set of functions denoted A to S. The selection function A routes, on the intermediate bus via A1, part of the information originating from the system to be investigated. The input and output function S provides the dialogue between the functions of the device and the external computer. The map B function routes the information from the intermediate bus onto the read bus situated at B5. The clock function C allows measurement of time intervals delimited by the appearance of two events which originate from the intermediate bus. The event counting functions D to R make it possible to log the appearance of events present on the intermediate bus.

Description

 The present invention relates to a device for measuring the performance of a computer system.

 Since the appearance in computer systems of new principles such as resource sharing, multiprocessing, multiprogramming, it is increasingly difficult to predict their behavior.

The performance of a computer system is directly linked to the management and organization of the physical resources constituting the architecture of the system.

In a common computer system, two types of software coexist:
-the operating system software,
- the application software.

 The application is made up of programs which run on a hardware environment comprising, one or more processors sharing, a common memory.

Each processor can have access to a local memory, and to communication interfaces with the outside.

 Program execution is counted against active agents called tasks.

 The central part of the operating system, called the kernel, is directly related to the hardware of the central unit.

The core is the set of common mechanisms, which facilitate the control of tasks, their cooperation, and their communication with the application environment.

 To increase the reliability of the software, the methodology for designing and implementing the programs was oriented towards structured programming.

 At the same time, the evaluation of the performance of a computer system has evolved towards the analysis of the tasks and functions performed by the system.

The hardware and software performance evaluation mainly focused on:
-the stain activity rate,
-the processor activity rate,
-the activity rate of the equipment,
-the response time of the material,
-detection and analysis of critical areas in
time and frequency,
-the duration of the tasks,
-the interdependence between Caches,
-detection of bottlenecks and
possible deadlocks,
- the length of the queues .etc ...

The device, object of the invention, allows the evaluation of these performances.

The device according to the invention is a fully programmable hardware device which is connected:
- on the one hand as a spy on the system bus to
study, without altering its functioning,
- on the other hand on an external computer which
stores the information from the invention, and
analyzes them in order to assess the performance of the
system to study.

For a better understanding of this invention:
-the description of the equipment is accompanied by
drawings using the same references,
-the description of the software installed on the
external computer, is illustrated by
programs.

In order to facilitate the description of the invention:
-we will assume that the system to be studied includes
a 24-bit address bus and a control bus
8 bits,
-we will assume that the read and write buses
of the invention are 8-bit data buses,
-we will assume that the external computer has
an 8-bit data bus.

The drawings are listed as follows:
FIG. 1 represents the block diagram of the
device which is the subject of the invention,
FIG. 2 represents a detail of the device
referenced in FIG. 1,
FIG. 3 represents a detail of the device
referenced in FIG. 2,
FIG. 4 represents a detail of the device
referenced in FIG. 1,
FIG. 5 represents a detail of the device
referenced in FIG. 1,
FIG. 6 represents a detail of the device
referenced in FIG. 1,
FIG. 7 represents a detail of the device
referenced in FIG. 1,
FIG. 8 represents a detail of the device
referenced in FIG. 1,
FIG. 9 represents a detail of the device
referenced in FIG. 1,
FIG. 10 represents a detail of the device
referenced in FIG. 9,
FIG. ll, explains the generation of the CO signal,
FIG. 12 explains the generation of the signal
reading of the intermediate bus,
FIG. 13 explains the generation of the signal
clock reading,
The device which is the subject of this invention consists of a set of functions denoted from A to S.

According to FIG. 1, the device according to the invention allows the performance of a computer system connected, via its bus, to be evaluated in AS of the selection function A.

The bus of the system to be studied provides at A5 all the address, control and synchronization signals, # the selection function A.

The selection function A switches part of the information coming from the system to be studied to its output A1.

The selection of information from the system to be studied is programmed via the write bus connected at A4, and the control bus connected at A3.

The control bus, connected at A2, carries control signals exploited by certain functions of the device which is the subject of this invention.

The input and output function S:
- ensures dialogue with the external computer,
via bus S1,
-provides all information on buses
control and writing by S3 and S4,
-provides and receives part of the signals from
control and synchronization on the bus
control by S2,
- receives all the useful information å
performance development, on the bus
read by S5.

The map B function receives information from the intermediate bus via its line B5, and switches it to the reading bus via its line B1 under the control of the external computer.

The clock function C allows, from a programmable quartz clock, to measure time intervals separating the appearance of two signals.

These time intervals are routed on the read bus by Cl, under the guidance of signals from the control, command and write buses, connected respectively at C2, C3, C4.

The event counting functions D to R allow:
-to count the appearance of present events
on the intermediate bus,
-to ensure and synchronize the readings
of the computer via lec buses
ture, writing, command, and control.

According to FIG. 2, the information of the system to be studied, connected in Assont directed to:
-the event selection function 10,
-the synchronization function 12 via the function
control 15,
-interruption detection function 18.

The event selection function 10 is composed of a buffer memory 104 and a bus amplifier 105.

 The events from the system to be studied are sent in 1043 to the buffer memory 104 and are transferred in 1041 to the intermediate bus as soon as the positive transition of the synchronization signal connected in 1042 occurs.

In order not to alter the quality of the information located on the intermediate bus, the information is amplified by the amplifier 105, before being sent to Al.

 According to FIG. 3, the control function 15 is composed of a logic function 153 and a bus amplifier 154.

Ie output signal 1531 of logic function 153 is informed in the timing diagram of FIG. 11 knowing that:
-The signal R goes through zero when the system
studying performs a read operation,
-The signal W goes through zero when the system
studying performs a write operation,
-The signal M goes through zero when the system
studying performs a memory operation,
- Signal 0 goes through zero when the system
studying performs an entry and exit operation,
-The clock signal ç passes to one to validate
control signals.

All the control signals of the system to be studied are sent to the amplifier 154 before being sent to the synchronization function 12 via the bus 151.

 According to FIG. 2, the control signals coming from the control function 15 are routed to 126 on the synchronization function 12. These control signals are used to generate the synchronization signal 127, sent at 102 to the selection function events 10.

The synchronization function 12 is composed:
- an 8-bit selector 128,
-of an 8-bit comparator 129,
-of an 8-bit memory 130,
-of an 8-bit memory 131.

The content of memory 131, sent to selector 128 at 1282, is used to select one or more control signals from the control function 15.

The control lines thus selected are sent in 1292 to the comparator 129.

On the other hand the control lines not selected by 128, are forced to the high level in 1281.

To load the memory 131, the external computer places the word to be memorized on the write bus connected at 1312, and activates the signal C'S2, coming from the command bus, connected at 1311.

The memory 131 is loaded in 2 steps:
1 / the computer places on the write bus
the byte to memorize,
2 / the calculator. controls the positive transition
C'S2 signal via the bus
ordered.

The comparator 129 generates a positive synchronization pulse in 1293 when the binary value of the digital signals connected in 1292 is equal to the binary value of the digital signals connected in 1291.

the positive synchronization pulse is generated when the control signals of the system to be studied are in a chosen configuration, programmed in memory 130.

This synchronization pulse, denoted SYNC, is sent by 121 on the control bus.

To load the memory 130, the external computer places the word to be memorized on the write bus connected in 1302, and activates the signal C'Sl, coming from the command bus, connected in 1301.

 The interrupt detection function 18 is used to generate the reset signal from the IRQ signal.

The interrupt detection function 18 is composed:
-from four inverters 185,187,189; 190,
- two selectors 186 and 188.

 -of an 8-bit memory 191.

The memory 191 is used to activate the selectors 186 and 188.

The activation of selectors 186 and 188 allows the switching of the IRQ signal connected at 184 to:
-the reset line of the control bus,
-the line for loading memory 191.

A negative transition of the IRQ signal connected at 184 corresponds to:
a positive transition of the reset signal
connected at 181 via selector 186,
-a positive transition of the connected signal
in 1911 corresponding to the loading of the
memory 191 via 185,186,187,188 and 190.

Depending on the content of the write bus, the selections
teurs 186 and 188 will be deselected or will remain
activated.

To load the memory 191, the external computer places the word to be memorized on the write bus connected at 183, and activates the signal CA22 (negative transition), coming from the command bus, connected at 182.

 According to FIG. 4, the selected events, located on the intermediate bus, are sent to the sampling function 20.

This sampling function 20 is composed of three 8-bit memories, 3 states, referenced 209, 210 and 211.

The sampling function 20 is used by the external computer, to record the identity of the event located on the intermediate bus.

Each event, coded on 24 bits (A0-A23), is stored in the three 8-bit memories as follows:
-bits A0-A7 in memory 209,
-bits A8-A15 in memory 210,
-bits A16-A23 in memory 211.

To record the identity of the event located on the interconnected bus, the external computer proceeds in 2 steps as follows:
1 / it loads the content of the intermediate bus into
the three memories 209,210,211 when
the event is stable on the bus,
2 / he accesses the content of the
memories 209,210,211 via the 8-bit read bus.

To load memories 209,210,211, the external computer generates a positive pulse CB21 from the control bus on input 232 of flip-flop D 23.

This pulse passes on the input 202 of the appearance of the negative transition of the synchronization signal SYNC in accordance with the timing diagram of FIG. 12.

The positive pulse generated in 202 allows the loading of the three memories 209, 210 and 211.

To maintain the content of one of the three memories 209 210 or 211, on the read bus, the external computer must activate the command line of the high impedance output of the corresponding memory (C'S3, C'S4 or C 'S5)
This high impedance line must be activated for the duration of the memory reading by the computer.

EXAMPLE:
To read the contents of memory 209, the
external computer must keep level
down signal C'S3, from the control bus, connected in
2092, during the read operation.

 To prevent the computer from the arrival of a new event on the intermediate bus, the SYNC signal is switched via the selector 22 on the control line CA11.

 The activation of the selector 22 by 221 is carried out by the signal 241 delivered by the memory 24.

To load the memory 24, the external computer places the word to be memorized on the write bus connected at 243, and activates the signal CA21, coming from the control bus, connected at 242.

 According to FIG. 5, the time interval function 25 is used to count the number of pulses of known frequency, separating the appearance of the two signals RESET and LECT, originating from the control bus.

The pulses of known frequency, come from the clock function 37, from 371.

The time interval function 25 is composed:
-a 24-bit counter 259,
- three 8-bit memories 256,257,258.

A high logic level of the reset signal, coming from the control bus, causes the signals of outputs 2591, 2592.2593 and 2594, of counter 25 to pass at low level.

On the other hand, a positive transition of the LECT signal, associated with the high level of the signal F0 coming from 371, allows the simultaneous loading of the three memories 256, 257, and 258 by 311 via the two logic circuits 32 and 31.

The three memories are loaded at each positive transition of the signal delivered by the inverter 31.

The loading of memories 256, 257 and 258 is in accordance with the timing diagram of FIG. 13.

Each time interval, coded on 24 bits (TO-T23), is stored in the three 8-bit memories as follows:
-bits TO-T7 in memory 256,
-bits T8-T15 in memory 257,
-bits T16-T23 in memory 258.

To maintain the content of one of the three memories 256, 257 or 258, on the read bus, the external computer must activate the command line of the high impedance output of the corresponding memory.

The control lines are connected respectively at 252, 253 and 254 of the counting function 25.

The activation at the low level of the signals connected at 252, 253 and 254 is carried out by the external computer by combining the signal CA22 with one of the signals denoted A, B or C in accordance with the table below.

CONTROL BUS SIGNALS * H. IMPEDANCE LINE
x ***************************** * * CA22 AA * B * C * FROM MEMORY NUMBER
+ + - - * x * 256 via 252
+ - + - * * 257 via 253
*************** ****************************** * - * + 258 via 254
NOTE:
* NOTE: *
*-CA22 signal is active at low level,
* -signals A, B, C are active at high level. *
************************************************** X *****
The clock function 37 is composed:
-a 377 quartz clock of known frequency
-a counter 376 used as a divider,
-a multiplexer 374,
-of a memory 375.

The signal 371 delivered by the clock function 37, corresponds to one of the signals delivered by the output 3761 of the counter 376 via the multiplexer 374.

The multiplexer 374 is controlled by one of the signals stored in the memory 375.

The action of the signals stored in the memory 375 on the multiplexer 374 ensures the routing of one of the output signals from the counter 376 to the output 371 of the clock function 37.

The memory 375 is loaded by the external computer, via the write bus connected at 372 and the logical combination of the two signals
A and CS15, from the control bus via the AND circuit 38 connected in 3752.

The counter 376 permanently receives on its input 3762, the pulses, of known fixed frequency, delivered by the quartz clock 377.

 Certain signals stored in memory 36 can activate selectors 30, 33 and 34.

Role of the three selectors 30, 33 and 34:
-activation of selector 30 allows
keeping line CA11 low,
-activation of selector 33 allows passage
pulses delivered by the counter 259,
on line CA11 of the control bus,
-activation of the selector 34 allows the
external computer to activate the reset line
of the control bus through
CS15 and B signals from the control bus.

The memory 36 is loaded by the external computer, via the write bus connected at 365 and the signal CA21 coming from the control bus.

 According to FIG. 6, the information coming from the intermediate bus is sent at 391 via D5, on the event detection function 39.

The event detection function 39 is made up of:
- three 8-bit comparators 396,394 and 392,
- three 8-bit memories 397,395 and 393.

The output signal of the event detection function 39, connected at 416 to the event counting function 41, travels low when the content of the intermediate bus is equal to the content of all memories 397,395 and 393 L event, coded on 24 bits, present on the intermediate bus is sent to the three comparators 396,394 and 392 as follows:
-A0-A7 lines in 3963 of comparator 396,
-A8-A15 lines in 3943 of comparator 394,
- Al6-A23 lines in 3923 of comparator 392.

The identity of the event to be monitored, coded on 24 bits, is stored in all of memories 397,395 and 393 as follows:
-bits A0-A7 in memory 397,
-bits A8-A15 in memory 395,
-bits A16-A23 in memory 393.

To store the identity of the event in all of memories 397, 395 and 393, the computer places the data on the write bus and activates lines CS1, A, B and C of the command bus, as follows :
-activation of CS1.

- writing of the word to memorize in the memory
397 on the write bus,
-activation and deactivation of signal A,
- writing of the word to memorize in the memory
395 on the write bus,
-activation and deactivation of signal B,
- writing of the word to memorize in the memory
393 on the write bus,
-activation and deactivation of signal C,
- deactivation of signal CS1.

The output signal of the event detection function 39, connected at 416, is also used to generate the reset signal of the control bus via the selector 405.

The selector 405 is activated by one of the signals memorized in the memory 406.

The loading of the memory i06 is carried out by the external computer, via the write bus connected at 402 and the signal CA21 coming from the control bus.

 The event counting function 41 is used to count the number of occurrences of the event detected by the event detection function 39.

The event counting function 41 is composed:
-a 24-bit counter 417,
- three 8-bit memories 418,419 and 420.

A high logic level of the reset signal coming from the control bus, or a low logic level of the signal RZ1 coming from the control bus, causes the output signals 4171,4172 and 4173 of the counter 417 to pass low.

On the other hand, a positive transition of the LECT signal coming from the control bus, allows the simultaneous loading of the three memories 418, 419 and 420.

To record the number of occurrences of the event stored in memories 418,419 and 420, the external computer will sequentially empty the contents of the memories on the reading bus, combining the activation of signal CZ1 with one of the signals denoted A, B or C of the control bus.

 According to FIG. 7, the information originating from the Intermediate bus is sent at 522, via E5, to the event detection function 52.

 The function, event detection 52, operates identical to function 39 in FIG. 6.

This function 52 is composed
-3 8-bit comparators 523,524 and 525,
- 3 8-bit memories 528,527 and 526.

The output signal of the event detection function 52, connected at 546 to the event counting function 54, travels low when the content of the intermediate bus is equal to the content of all the memories 528,527 and 526.

The event, coded on 24 bits, present on the intermediate bus is sent to the three comparators 523,524 and 525 as follows:
-AO-A7 lines in 5233 of comparator 523,
-A8-A15 lines in 5243 of comparator 524.

 - lines A16-A23 in 5253 of comparator 525.

The identity of the event to be monitored, coded on 24 bits, is stored in all of memories 528,527 and 526 as follows:
-bits AO-A7 in memory 528,
-bits A8-A15 in memory 527,
-bits A16-A23 in memory 526.

To store the identity of the event in all of the memories 528,527 and 526,1e computer places the data on the write bus and activates the lines CS2, A, B and C of the command bus
The output signal of the event detection function 52, connected at 546, can also be used to generate the signal CA11 of the control bus via the selector 535.

The selector 535 is activated by one of the signals memorized in the memory 536.

The memory 536 is loaded by the external computer, via the write bus connected at 532 and the signal CA21 from the control bus.

 The event counting function 54 is used to count the number of occurrences of the event detected by the event detection function 52.

The event counting function 54 is composed:
-a 24-bit counter 547,
- three 8-bit memories 548, # 549 and 550.

A high logic level of the reset signal from the control bus, or a low logic level of the signal RZ2 from the control bus.

lowers the output signals 5471,5472 and 5473 from the counter 547.

On the other hand, a positive transition of the LECT signal allows the simultaneous loading of the three memories 548,549 and 550.

The LECT signal can be generated from:
-di signal CAll, coming from the control bus,
CB2l signal from the control bus
To record, the number of occurrences of the event stored in memories 548, 549 and 550, the external computer will sequentially empty the contents of the memories on the read bus, combining the activation of signal CZ2 with one of the signals denoted A, B or C of the control bus.

 According to FIG. 8, the information coming from the intermediate bus is sent at 672, via F5 to R5, on the event detection functions 67 from F to 67 from R.

Each event detection function 67 has an operation identical to function 39 in FIG. 6.

Each function 67 is composed
- 3 8-bit comparators 673,674 and 675.

 - 3 8-bit memories 678,677 and 676.

Each event detection function 67 follows an event of the intermediate bus.

The loading of each set of memories 678, 677 and 676 is carried out by the external computer, by activating the signals CSN (N = 3 to 12>, A, B, C, originating from the control bus.

Each event detection function 67 is associated with an event counting function 68.

At each event recognition, the output signal of the event detection function associated with it, connected at 686, passes to the low level
Each negative transition of the signal connected at 686 is followed by the increment of the counter 687 of the event counting function 68.

The counter 687 is reset to zero:
-by activating the reset signal from the bus
control,
-by activating the RZN signal (N = 3 to 12)
of the control bus by means of the computer.

The content of the counter 687 is stored in all of the memories 688, 689 and 690, when the positive transition of the LECT signal from the control bus occurs.

 To record the number of occurrences of the event stored in memories 688,689 and 690, the external computer will sequentially empty the contents of the memories on the read bus, combining the activation of the signal CZN (N = 3 to 12) with one of the signals marked A, B or C from the control bus.

 According to FIG. 9, the buses of the external computer are sent to the two input and output circuits 79 and 80 via S1.

The two I / O circuits 79 and 80 allow protection and synchronization of exchanges between the device which is the subject of the invention and the external computer.

The two circuits 79 and 80 operate similar to the Peripheral interface adapter 6521 manufactured by MOTOROLA.

Circuit 79 is connected as follows:
- port A, 8 bits, programmed as input, is connected
to the read bus via amplifier 91,
- port B, 8 bits, programmed as output, is connected
in 833 to the multiplexing function 83 via
amplifier 90,
- the line CAl, programmed as input, is con
connected to line CA11 of the control bus
via amplifier 89,
- line CA2, programmed as output, is con
connected to line CA21 of the control bus
via amplifier 88,
-the CB2 line, programmed as output, is con
connected to line CB21 of the control bus
via amplifier 87,
- the data bus, 8 bits, bidirectional,
is connected in 792 to the data bus of
outdoor computer,
-selection, control and
synchronization, are connected in 791 on
the address and control buses of calcula
outside designer.

Circuit 80 is connected as follows:
- port A, 8 bits, programmed as output, is connected
to the write bus via amplifier 81,
- port B, 8 bits, programmed as output, is connected
in 831 to the multiplexing function via
amplifier 82,
- the line CAl, programmed as input, is con
connected to line CA12 of the control bus
via amplifier 86,
- line CA2, programmed as output, is con
connected to line CA22 of the control bus
via amplifier 85,
- the data bus, 8 bits, bidirectional,
is connected in 802 to the data bus of the
outdoor computer,
-selection, control and
synchronization, are connected in 801 on
the address and control buses of the computer
outside.

According to FIG. 10, the information coming from the port B of the I / O circuit 79 ensures, via the multiplexers 834 and 835, the generation of the signals CZN and
RZN <N: = 1 to 15) on the control bus.

The information contained on lines DO to D3 of port B of circuit 79, ensures the generation of signals RZ1 to RZ15.

The information contained on lines D4 to D7 of port B of circuit 79, ensures the generation of signals CZ1 to CZ15.

 the information coming from port B of the I / O circuit 80 ensures, via the multiplexers 836 and 837, the generation of the signals CSN, A, BC and C'SN (N: = 1 to 15) on the control bus .

The information contained on lines DO to D3 of port B of circuit 80, ensures the generation of signals A, B and C, as well as CS'1 to CS'5.

The information contained on lines D4 to D7 of port B of circuit 80, ensures the generation of signals CS1 to CS15.

Operation of one of the multiplexers 834 to 837:
- the logical combination, on 4 bits, Zero, app
quée on its entry, makes pass all its
output lines at the low level,
-a logical combination, on 4 bits, other than
zero, applied to its input, makes it transit
at the high level one of its 15 output lines.

Claims (11)

 1. Device for measuring the performance of a computer system, characterized in that it comprises:  real-time selection means, denoted A, for events  elements present on the system bus to be evaluated,  means for recording identity of events,  marked B, present on the intermediate bus,  means of measurement and recording of inter  time blocks, denoted C, delimited by the appearance of  two RESET and LECT signals,  means of detection and counting of events, noted  D to R, present on the intermediate bus,  protection and synchronization means  exchanges, noted S, with the external computer,  2. Device according to claim 1, characterized in that the means of selection in real time, denoted A, of events present on the bus of the system being studied, comprise:  an event selection function 10,  a synchronization function 12,  a control function 15,  an interrupt detection function 18.  counter bus under the name SYNC).  synchronization 12, is also sent to the  (the signal connected at 102, coming from the function  positive signal connected to input 102  at 101 on the intermediate bus at each transit  system to study and pass this information  at its input 103 the bus information of the  event selection function 10 receives knowing that:  memoir 131.  129, under the guidance of the content of the  of these control signals on the comparator  tion, and conveying part or all  control of the system to be studied after adapta  - a selector 128 receiving the signals from  said synchronization function 12 comprises:  the content of memory 130 connected in 1291.  coming from selector 128, coincides with  when the nature of the control signals,  - a comparator 129 delivering the SYNC signal  C'S2 signal from the control bus).  memorize on the write bus and activate the  131, the external computer places the word at  (To load the memory  request the operation of selector 128  - a memory 131 whose content is used to com  sation 12.  the selector 128 of the synchronization function  amplification as well as the CO signal on the input  transfer these same control signals after  the control signals of the system to be studied, and  activates signal C'S1 from the command bus) the counter function 15 receives at its input 152  the word to memorize on the write bus and  memory 130, the external computer places  rator 129 (To load the  control signals connected to the compa  logical combination of identification of  a memory 130 used to store a  - an input and output operation for writing.  - an input and output operation for reading,  a memory write operation,  a memory read operation,  dier performs  the CO signal is generated when the system has been  in memory 191.  under the guidance of one of the stored signals  carry on the reset line of the control bus,  coming from the system bus to study for the  - a selector 186 receiving the IRQ pro signal  includes:  the interrupt detection function 18  and 188.  IRQ signal wise through selectors 186  - a memory 191 whose content allows the step  3. Device according to claim 2, characterized in that the loading of the memory 191 is carried out under the control of the signal CA22 from the control bus or by the IRQ signal from the bus of the system to be studied. Depending on the content of the write bus, the appearance of the IRQ signal will maintain or not maintain the activation of the selectors 186 and 188.  4. Device according to claim 1, characterized in that said means for recording the identity of events present on the intermediate bus, comprise:  ~ a sampling function 20 memorizing in the  three memories 209, 210 and 211 the content of the bus  intermediate, under the guidance of the generated signal  by rocker D 23.  loading of the three memories 209, 210 and 211.  a D flip-flop used to generate the signal  by the synchronization function 12.  SYNC, from the control bus, generated in 121  - presence of negative signal transition  demand, generated by the external computer,  - presence of signal CB2l, coming from the com bus  carried out:  when the two conditions below are  the signal generated by the flip-flop D 23 appears  command) knowing that:  closes and activates the CA21 signal from the bus  laughter places the word to memorize on the ecri bus  loading memory 24, the external computer  CA11 from the SYNC signal (To carry out the  the selector 221 used to generate the signal  a memory 24 whose content is used to activate  and C'S5 from the control bus.  external tor from the three signals C'S3, C'S4  211, is performed sequentially by calcula  stored in all of memories 209,210 and  recording the identity of the event  and 211.  high impedance of one of the memories noted 209,210  signals denoted C'53, C'54 and C'S5, control the output  Activation by the external computer of one of the  5. Device according to claim l, characterized in  what the so-called measurement and recording means  time tervalles, denoted C, delimited by the appearance of the two  reset and read signals,  include:  a clock function 37,  a time interval function 25,  a memory 36 used to activate the selectors  34.33 and 30.  from the control bus).  closes and activates signals A and CS15,  place the word to memorize on the screen bus  from memory 375, the external computer  selector 374 (For loading  - a memory 375 used to control the  divider 376,  375, one of the signals delivered by the  under control of memory content  - a selector 374 used to select  of the standard frequency,  diques whose frequency is a submultiple  by clock 377, different perio signals  shot of the standard frequency signal delivered  - a divider 376 used to generate, for example  known frequency,  issue a standard periodic signal of  - a 377 quartz clock used for  said clock function 37 comprises:  knowing that:  control.  the appearance of the LECT signal from the bus  memorize the content of counter 259 as soon as  - three memories 256, 257 and 258 used for  from the control bus,  tion of two high levels of the RESET signal,  delivered by selector 374, between the pair  the number of negative signal transitions,  - a counter 259 used for accounting  the time interval function 25 comprises:  calculator.  control, via selector 34 using the  via signals CS15 and B from the bus  - allow activation of the reset line by  selector 30,  - connect line CA11 to the low level via the  of the control bus via selector 33,  output 2592 of counter 259 on line CA11  - allow the signal delivered by the  the content of memory 36 can: 6. Device according to claim 5, characterized by  the fact that  generation of the story memorization signal  bare of counter 259, in all three  memories 256, 257 and 258, must satisfy one of the  two conditions listed below:  - presence of the high level of the LECT signal from  of the control bus, and presence of the transi  positive signal from the selec  tor 374,  - presence of the high level ~ of the signal delivered  by selector 374 and presence of the tran  positive position of the LECT signal  reading the contents of memories 256, 257 and 258  is performed sequentially by the computer  exterior as follows:  - activation of the CA22 signal from the communication bus  order,  - activation of signal A from the control bus  (the content of memory 256 is located on the  reading bus),  - reading the reading bus,  - activation of signal B from the control bus  (signal A is automatically deactivated; the  content of memory 257 is located on the bus  reading),  - reading the reading bus,  - activation of signal C from the control bus  (signal B is automatically deactivated; the  content of memory 258 is located on the bus  reading),  - reading the reading bus,  - deactivation of signal CA22.  NAND circuits 26,27,28 and 29.  signal CA22 with one of the signals A, B or C via the  outdoor culateur, by combining the activation of the  memories 256 257 and 258 is performed by the cal  activation of one of the high impedance lines of  7. Device according to claim 1, characterized in that the event detection and counting means, denoted D a R, present on the intermediate bus are broken down into twelve major event counting functions:  event selection and counting function  D elements capable of generating the RESET signal on the  control bus,  an event selection and counting function  E elements that can generate the LECT signal on the  control bus,  ten event selection and counting functions  elements F to R.  8. Device according to claim 7, characterized in that the function of selecting and counting events D, comprises:  an event detection function 39,  a reset function 40,  an event counting function 41.  monitor.  memorize the identity of the event a  - three memories 397,395 and 393 used for  the contents of the three memories 397,395 and 393,  to compare the content of the intermediate bus  - three comparators 396,394 and 392 used  the event detection function 39 includes: knowing that:  seems from the three memories 397, 395 and 393.  corresponds to the identity stored in the  the event located on the intermediate bus  low level signal when the identity of  generate on their common output line a  the three comparators 396,394 and 392  store in memory 393.  - writing on the writing bus of the word a  from the command bus,  - activation and deactivation of signal B  memorize in memory 395,  - writing on the writing bus of the word to  from the command bus,  - activation and deactivation of signal A  memorize in memory 397,  - writing on the writing bus of the word to  ordered,  - activation of signal CS1 from the bus  external computer as follows:  393 is performed sequentially by the  loading the three memories 397,395 and  - deactivation of signal CS1.  from the command bus,  - activation and deactivation of signal C  reset selection 40.  - on the input of the function selector 405  event counting 41,  - on the entry 416 of the counter 417 of the land  396,394 and 392 is connected:  the output signal common to the three comparators  and activates the signal CA21 from the control bus).  places the word to be memorized on the write bus  from memory 406, the external computer  inverter 404 (for loading  of the three comparators 396,394 and 392 via  control bus from the output signal  memory 406, can generate the reset signal on the  the selector 405, controlled by the content of the  signal connected at 415 of function 41.  by the appearance of two high levels of  394 and 392, in the separate time interval  output, delivered by 396 comparators,  the number of negative signal transitions  - a counter 417 used for accounting  includes:  said event counting function 41  control.  from the appearance of the LECT signal from the bus  to store the content of counter 417  - three memories 418,419 and 420 used  - the signal RZ1 from the control bus.  - the reset signal from the control bus,  one of the two signals listed below  high impedance of the memories noted 418,419 and 420) the signal connected in 415, can be activated from  411,412 and 413 is used to unlock one of the outputs  the command bus (activation of one of the lines  CZ1 associated with one of the signals denoted A, B, C from  outside on the read bus from the signal  is performed sequentially by the computer  reading the contents of memories 418,419 and 420  9. Device according to claim 7, characterized in that the function of selection and counting of events E, comprises:  an event detection function 52,  a selection function CA11 53,  an event counting function 54.  watch.  memorize the identity of the event has on  - three memories 528,527 and 526 used for  the contents of the three memories 528,527 and 526,  to compare the content of the intermediate bus  - three comparators 523,524 and 525 used  said event detection function 52 comprises: knowing that:  of the three memories 528,527 and 526.  the identity that is memorized throughout  located on the intermediate bus corresponds to  low level when the identity of the event  on their common output line a signal from  the three comparators 523,524 and 525 generate  - deactivation of signal CS2.  from the command bus,  - activation and deactivation of signal C  memorize in memory 526,  - writing on the writing bus of the word to  from the command bus,  - activation and deactivation of signal B  memorize in memory 527,  - writing on the writing bus of the word to  from the command bus,  - activation and deactivation of signal A  memorize in memory 528,  - writing on the writing bus of the word to  ordered,  - activation of signal CS2 from the bus  exterior as follows:  is carried out sequentially by the computer  loading the three memories 528,527 and 526  selection CAll 53.  - on the input of the function selector 535  event counting 54,  - on the input 546 of the counter 547 of the function  523,524 and 525 is connected:  the output signal common to the three comparators  signal CA21 from the control bus).  word to memorize on the write bus and active  memory 536, the external computer places the  pourer 537 (to load the  of the three Comparators 523,524 and 525 via the in  control bus from the output signal  memory 536, can generate signal CA11 on the  the selector 535 controlled by the content of the  signal connected at 545 of function 54.  by the appearance of two high levels of  524 and 525, in the separate time interval  output delivered by comparators 523,  the number of negative signal transitions  - a 547 counter used for accounting  includes:  said event counting function 54  the inverter 61.  as soon as the LECT signal from  to store the content of counter 547  - three memories 548,549 and 550 used  from one of the memoirs noted 548, 549 and 550).  used to unlock the high impedance output  (activation of one of lines 541, 542 and 543  signals marked A, B, C from the control bus  from signal CZ2 associated with one of  external computer on the read bus,  550 is performed sequentially by the  reading the contents of memories 548,549 and  - the signal RZ2 from the control bus.  - the reset signal from the control bus,  below  from one of the two signals listed  the signal connected at 545, can be activated  inverter 61.  control via circuit NO OR 62 and the circuit  control or the CB21 signal from the bus  is generated from the CA11 signal from the bus  the LECT signal sent on the control bus  absence of signal CA11 <CAil low level).  - be used to generate the LECT signal in  laughter can:  the signal CB21 generated by the external computer  - inhibit the LECT signal (CB21 high level)  10. Device according to claim 7, characterized in that the functions of selecting and counting events F to R, each include:  an event detection function 67,  an event counting function 68.  monitor.  memorize the identity of the event at  three memories 678,677 and 676 used for  the contents of the three memories 678,677 and 676,  to compare the content of the intermediate bus  three comparators 673,674 and 675 used  includes:  said event detection function 67 knowing that:  memories 678,677 and 676.  identity memorized in all three  located on the intermediate bus corresponds to  low level when the identity of the event  on their common output line a signal from  the three comparators 673,674 and 675 generate  of event 68.  counter 687 of the counting function  673,674 and 675 is connected to input 686 of the  is associated with a value of N), the output signal common to the three comparators  event selection and counting function  in the closed interval 3..12; At each  - deactivation of the signal CSN (N is contained  the control bus,  - activation and deactivation of signal C from  riser in memory 676,  - writing to the memo word writing bus  the control bus,  - ~ activation and deactivation of signal B from  riser in memory 677,  - writing on the writing bus of the word a memo  the control bus,  - activation and deactivation of signal A from  memorize in memory 678,  - writing on the write bus of the word à.mes-  ordered  - activation of the CSN signal from the bus  exterior as follows:  is carried out sequentially by the computer  loading of the three memories 678,677 and 676  connected in 685 from function 68.  the appearance of two high signal levels  and 675, in the time interval separated by  output delivered by the comparators 673,674  number of negative signal transitions  - a 687 counter used to record the  said event counting function 68 comprises:  control.  as soon as the LECT signal from the bus appears  to store the content of counter 687  - three memories 688,689 and 690 used  688,689 and 690).  high impedance outputs of noted memories  lines 681, 682 and 683 are used to unlock a  A, B, C from the control bus (activation of a  CZN (N: = 3..12> associated with one of the noted signals  outside on the read bus, from the signal  is performed sequentially by the computer  reading the contents of memories 688,689 and 690  order.  - the signal RZN (N: = 3..12) from the com bus  - the reset signal from the control bus,  below  from one of the two signals listed  the signal connected at 685, can be activated at  11. Device according to claim 1, characterized in that said means of protection and synchronization of exchanges, denoted S, with the external computer, comprise:  ~ a parallel input and output interface 79,  a parallel input and output interface 80,  a multiplexing function 83.  outdoor culateur.  to the address and control buses of the cal  synchronization are connected in 791  - the selection, control and  outside guard,  connected in 791 to the calcula data bus  - the bidirectional data bus, is con  planner 87,  to the CB21 line of the control bus via the am  - line CB2, programmed as output, is connected  planner 88,  to the line CA21 of the control bus via the am  - line CA2, programmed as output, is connected  amplifier 89,  to line CA11 of the counter bus via  - the line CAî, programmed as input, is connected  plexing 83 via the amplifier 90,  information to the multi function  - port B 793, programmed as send output t  via amplifier 91,  information from the read bus  - port A 794, programmed as input receives  is connected as follows:  the programmable input and output interface 79, knowing that:  external computer.  to the address and control buses  synchronization are connected in 801  - the selection, control and  outdoor reader,  connected in 802 to the calcu data bus  - the bidirectional data bus, is con  via amplifier 85,  connected to line CA22 of the control bus  - line CA2, programmed as output, is  via amplifier 86,  connected to line CA12 of the control bus  line CAl, programmed as input, -is  multiplexing 83 via amplifier 82,  information to the function of  - port B 803, programmed as output sends  via amplifier 81,  information from the write bus  - port A 804, programmed as output receives  is connected as follows:  the programmable input and output interface 80,  6521 manufactured by MOTOROLA.  similar to the Peripheral Interface Adapter  grammables 79 and 80 operate  the so-called pro input and output interfaces  multiplexer 837.  - signals A, B, C, CS'1 to CS'5 from  plexer 836,  - signals CS1 to CS15 from the multi  835 plexer,  -RZ1 to RZ15 signals from the multi  plexer 834,  signals CZ1 to CZ15 from the multi  multiplexing 83 ::  control bus, said control bus receives function  ficitor 82, and on the other hand in 8372 at  in 8371 at port B of PIA 80, via the amplifier  an 837 multiplexer connected on the one hand  control bus,  ficitor 82, and on the other hand in 8362 at  in 8361 at port B of PIA 80, via the amplifier  - an 836 multiplexer connected on the one hand  control bus,  ficitor 90, and on the other hand in 8352 at  in 8351 at port B of PIA 79, via the amplifier  - an 835 multiplexer connected on the one hand  control bus,  ficitor 90, and on the other hand in 8342 at  in 8341 at port B of PIA 79, via the amplifier  - an 834 multiplexer connected on the one hand  said multiplexing function 83 comprises:  of 79 through the 835 multiplexer.  through lines D4 to D7 of port B  - generation of signals CZ1 to CZ15 by  from 79 through the 834 multiplexer,  through lines DO to D3 of port B  - generation of signals RZ1 to RZ15 by  the information from port B of circuit 79 ensures:  80 through the 836 multiplexer.  through lines D4 to D7 of port B  - generation of signals CS1 to CS15 by  port B of 80 through the multiplexer 837,  via lines DO to D3 of  - generation of signals A, B, C, CS'1 to CS'5  circuit 80 ensure:  information from port B of