FR2587868A1 - VIDEO SIGNAL PROCESSOR COMPENSATED WITH TIME ERRORS - Google Patents

Abstract

A. VIDEO SIGNAL PROCESSOR WITH TIME ERROR COMPENSATION. B. PROCESSOR CHARACTERIZED IN THAT FURTHER, A DIGITAL IMAGE MEMORY 31 IS CONNECTED TO CIRCUIT 18 TO COMPENSATE SIGNAL DEFECTS AND THAT THE OUTPUT OF THIS DIGITAL IMAGE MEMORY 31 IS CONNECTED TO A CIRCUIT FOR SEPARATE PROCESSING OF THE CHROMINANCE FRACTION AND THE LUMINANCE FRACTION OF THE DIGITAL SIGNALS TAKEN FROM THE IMAGE MEMORY 31. C. THE INVENTION CONCERNS VIDEO SIGNAL PROCESSORS WITH COMPENSATION OF TIME ERRORS.

Description

v 1.-

  "Video signal processor with time error compensation."

  A video signal processor, in which video signals taken from an information carrier are converted to digital signals and stored in digital form, a first signal

  synchronization is also used for the conversion of

  analogue-digital technology and for the inscription of

  digital signals in a first intermediate memory, and at the output of this first intermediate memory, to which is applied, for reading, a second signal

  of synchronization, is connected a circuit for the com-

  thought of signal faults, circuit at the output of-

  which is connected a second intermediate memory in

  which digital signals are recorded with the se-

  cond synchronization signal and from which

  the digital signals are read with a third

Synchronization report.

  When reproducing video signals, especially color television signals, from a recording medium, different defects in these signals appear and these defects must be

  compensated to a large extent for reproduc-

  as good as possible. This is the first

  gne of time errors and speed errors as well as 2.- loss of signals (drop-outs), which are caused

  by defects of the information carrier. He is in-

  It is known to store image signals in an image memory which are picked up in segments from a magnetic tape acting as an information carrier, so that they can then be read repeatedly.

to reproduce a still image.

  To fulfill the aforementioned functions, we know different devices that work, either on

  an analog base, a digital base.

  A known method for compensating for

  time in television signals in

  theirs, which are taken from a computer

  in which said color television signals are converted into digital signals, and are stored in digital form, consists in that first synchronization signals (C1) are obtained, the phase position of which is influenced by the horizontal frequency synchronization contained in the color television signals taken from

  of the information medium, and whose frequency is

  mandated by a first control voltage, these first synchronization signals (01) being used for the digital analog conversion and for the registration

  digital signals in a first intermediate memory

  digital signals being read from

  this first intermediate memory with a second

  sync signal (02) whose frequency is an integer multiple of a frequency reference signal

  horizontal, the difference between a line period of

  digital signals read from the first internal memory

  intermediate and the reference signal line period, being measured to derive the first voltage of

  control, the horizontal frequency pulses of the

  benchmark being compared with regard to the 3.-

  phase position with the frequency pulses

  of the signals read from the first intermediate memory, the writing and reading of the digital signals in a memory or from a memory, being controlled according to the phase difference, so that the time between the recording and reading corresponds to the phase difference, the signals read from the memory being written in a second intermediate memory, the digital signals being read from this second intermediate memory by means of third synchronization signals (03 ) which are obtained from the second synchronization signal by a controllable phase shift, a phase comparison being carried out between the color synchronization signal of the signals read from

  the second intermediate memory and a sync signal

  reference coloring, and the result of this

  the phase comparison being stored on one line respectively to obtain a second control voltage which is used for phase shifting of the second

  synchronization signal (DE-A1-30 26 473).

  With this known process for the compensation

  time can be associated with a digital image memory for still image reproduction or

slow motion shots.

  The object of the present invention is to

  improve the known process to obtain in a way also

  optimum possible compensation for the

  your. A video signal processor according to the invention is characterized in that in addition, an image memory is connected to the circuit for compensating for signal faults and the output of this digital image memory is connected to a circuit for the separate processing of the chrominance fraction and the luminance fraction 4.- digital signals taken from the image memory. A significant improvement is obtained

  in that the digital signals are applied to a circuit

  cooked for the determination of speed errors and that

  the output signals of this circuit for determining

  speed errors, are sent to two generators.

  pulse generators which are provided to generate the first and the third synchronization signal, for controlling the frequency of the first and third

synchronization signal.

  Other features of the invention make it possible to envisage advantageous complements and improvements of the video signal processor according to the invention defined above, thus:

  - the digital signals applied to the

  moire image are derived by analog conversion-

  of the video signal applied as a color television signal, - at the output of the image memory,

  circuits of delay of a line, a circuit totalizing

  and a signal switch are connected so that during a first frame period, the signal of

  luminance and the chrominance signal are obtained from

  firing digital signals belonging to a frame and that

  during a second frame period, the light signal

  of two successive successive lines of the same frame is interpolated and the chrominance signal is obtained by repetition of the chrominance signal of the same frame, - the output signals of the signal switch are respectively applied to a converter

  digital-analogue, the output of the digital converter

  the analog signal provided for the chrominance signal being applied via a bandpass filter and a color subcarrier phase circuit to a

  inputs of a totalizing circuit, the output of the con-

  digital-to-analog converter for the signal

  luminance being applied by means of a

  bandpass and a correction circuit, preferably a corrector connected, to the other input of a summing circuit, and that the subcarrier phase circuit

  of color includes a phase shifter capable of being

  which is capable of being controlled by means of a phase comparison between the color synchronization signal and a reference carrier, - to the digital signals applied to the image memory is added an identification signal,

  which contains information concerning the rela-

  in time of the digital signals in relation to

  a reference color television signal, for

  account of the sequence of: frame and sequence of the color subcarrier conditioned by the system

  television in color, whereas it is

  seen after the image memory, a circuit for exploiting

  of this information, which circuit the signal switch provided after the image memory controls so that the signals read from the memory are adapted to the reference color television signal in this respect.

  regarding the succession of frames and the phase of

  tation of the color subcarrier.

  - the first intermediate memory is

  consisting of a PIFO circuit with a registered memory

tion and reading connected to it.

  before the analog-to-digital conversion, a color synchronization signal contained in the applied video signals is conveyed via a limiting and filtering circuit which keeps the amplitude of this color synchronization signal constant. .-

  - in a synchronization signal of cou-

  their, the phase position changing by line

  the PAL color television process is switched

  in decline before the analog-digital conversion.

  - a control signal is applied to the

  first pulse generator for controlling the posi-

  phase of the first synchronization signal, this control signal being derived by scanning a mis er signal. place in the video signal before conversion

  analogue-digital, and which, according to a predefined

  finished, goes from a first value to a second value.

  - the signal, which according to a predefined function

  finite goes from a first value in a second value,

  is coupled with a frequency synchronization pulse

  horizontal situation which is delivered by a gener-

  pulse rate, this pulse generation circuit

  including a signal switch in itself known, a demo-

  dulator and a pulse separation circuit, the video signals from two magnetic heads

  being likely to be applied to the commu-

  channel switch and this channel switch being switched

while scanning lines.

  a high synchronization signal

  decision is likely to be applied to the first and

  second pulse generator and, with respect to this

  As a result of the high precision synchronization signal thus applied, the phase position and the frequency deviation of the synchronization signal obtained can be controlled.

  by the digital signals applied.

  - by the implementation of at least one gen-

  digital pulse generator in which the output of a digital totalizer is connected via a

  register at the first entry of this digital totalizer.

  and in which, in addition, at a second entry of the

  digital talisor, triggered by a pulse of 7.- horizontal frequency synchronization, a first value is likely to be applied during a short

  moment, while during the remainder of the

  another value is likely to be applied.

  other registers are connected upstream of the second input, registers with which, according to a horizontal frequency synchronization pulse, respectively, several positions of higher values of the second input may be connected to an input for the first value, or several low value positions are likely to be

  connected with an entry for the second value.

  - the digital totalizer and the register

  are provided for twenty bit positions.

  a synchronization signal is applied to a synchronization input of the register, the frequency of this signal being constant and situated in the frequency zone of the synchronization signal to be obtained, while by an appropriate choice of the zone of the second value; ,

  the frequency of the output signal of the register is a fraction

  frequency of the synchronization signal thus applied, and at the output of the register a multiplier of

  frequency is connected via a converter

digital-to-analog

  a circuit for shaping a sinusoidal oscillation is arranged between the register and

  the digital-to-analog converter.

  - the frequency multiplier is consti--

  killed several frequency duplicators that each contain an analog multiplier and a tuned filter

on the output frequency.

  An exemplary embodiment of the invention is shown in the accompanying drawings and will be shown

  in more detail in the description below:

  - Figure 1 (la - lb). is a block diagram of 8. - the embodiment of the invention,

  - Figure 2 shows part of the

  FIG. 1 shows diagrams of the voltage versus time for the signals appearing in the device according to FIG. 2; FIG. 4 shows other diagrams of the voltage according to FIG. time with a modified time scale with respect to FIG. 3; FIG. 5 is a block diagram of a digital pulse generator,

  - Figure 6 shows a detail of the general

digital pulse generator,

  FIG. 7 is a diagrammatic representation

  2 is a block diagram of a circuit for determining speed errors; FIG. 9 is a diagram showing for example, the evolution over time of speed errors, - Figure 10 is a block diagram to represent in more detail a part of the

figure 8.

  The identical parts are provided on the

identical reference figures.

  Color television signals (PBAS)

  applied in 1 to the video signal processor according to the

  Figure 1, are the output signals of a video tape device. They include, among others, speed errors and time errors as well as signal drop-outs. The function of the processor

  video signal shown in Figure 1, is the compensation

  correction or correction of these defects. In addition, there is further provided in the video signal processor an image memory to allow reproduction with a different speed than the shooting. Gela is

  particularly important in the case of

  in which the signals of a frame are

  registered by being distributed over several tracks. Most of the signal processing is done with digital circuits, and for this purpose the color television signals applied at 1 are

  converted to digital signals using a converter

analogue-digital system 2.

  Before, however, television signals

  in color reach the analogue converter

  digital 2, they are prepared as described below, in order to create the best prerequisites for

  the subsequent processing steps.

  Firstly, using a circuit 3 known per se for adjusting the amplification and detachment

  black level, these values are set. In one

  4 which will be described in greater detail in connection with FIG. 2, a predefined function, hereinafter referred to as

  ramp, is introduced into the zone of the signal of syn-

  horizontal frequency synchronization of

  color television. This function is used later

  for the precise determination of the position

  phase of the color television signal by

  port to sync signals. It is then proceeded with a phase reversal, in itself known, of the

  color synchronization signal switched in its posi-

  phase in accordance with the television method of

  PAL color in every second line. This retrogression

  phasing facilitates the subsequent exploitation of the

  Color sync signal to determine speed errors. Finally, television signals in

  FBAS color pass through a pass filter

  down 6 to prevent further disturbances.

  10.- To avoid visible disturbances of the quantization, this quantization takes place in the analog-digital converter 2 with a precision

  of 9 binary digits. To analog converter-

  digital 2 is applied a synchronization signal 01,

  which is coupled with the television signals in

  their FBAS applied in 1 and whose frequency is

  13.5 MHz, that is about 3 times the frequency

  of the PAL color carrier = alternating phase line.

  The video signal processor shown in Fig. 1 is provided for a particular kind of magnetic tape apparatus in which a frame is recorded by being distributed over a plurality of tracks, as will be discussed hereinafter. In magnetic tape machines with this so-called segmented scanning, there is indeed several times switching in a frame from one magnetic head to the other. This usually takes place

  within the frequency suppression interval

  this horizontal, in which case, due to switching the horizontal frequency synchronization pulse is lost. The color television signals applied at 1 respectively comprise respectively ahead of the first line of what is called a packet of lines, a disturbed synchronization pulse. For subsequent reproduction of the signals on a control receiver, or for the transmission of signals by

  via a radio transmitter, this is not a problem

  itself, because later new synchronization signals are added to the television signals

  in colour. To detect the time error, an operator

  However, synchronization of the horizontal frequency synchronization pulse is necessary. In the case of

  recording apparatus and reproducing apparatus

  known, it was therefore appealed for the first time

  first line of a bundle of lines, to an extrapolation

  values determined for the following lines.

  To the video signal processor according to

  re 1, however, are directly applied through the inputs

  57 and 58 and from the magnetic tape machine

  that, the carrier frequency output signals of the magnetic heads after amplification and correction

  appropriate frequency rate. The switch of

  59 connected to inputs 57 and 58 is controlled by

  that switching occurs respectively in the

  the line before the horizontal frequency synchronization pulse for which the signal applied at 1 is switched. The output signals of the channel switch 57 are demodulated at 60 and are applied to a pulse separation circuit 61. This pulse separation circuit is known per se, and separates the H, V, 2 V signals from the applied video signal. The signal H is used in the circuit 4 for the shaping of the

ramp signal.

  The output signals of the analog-digital converter 2 are applied to the inputs of a ramp operating circuit 12 and a FIFO circuit

  13. The ramp operating circuit 12 is

  in more detail in Figure 2, and it generates a

  digital standard which indicates deviations from a

  predefined phase transition between the first synchronization signal C1 and the synchronization pulse in

  horizontal frequency of television signals in

  their. This signal is applied to a control input which serves to control the phase position of the first pulse generator 14. The synchronization signal C1 thus modified in the phase position is applied, on the one hand, to the analog-to-digital converter. as a scanning synchronization and, on the other hand, via a logic circuit 15, to the FIPO circuit 13 as a registration synchronization. With the help of the control loop constituted by the circuits 2, 11, 12 and 14, a very precise phase relationship is obtained between the color television signals and

  the first synchronization signal C1.

  At the first pulse generator 14, a synchronization signal C2 produced by

  a quartz generator, not shown. A circuit, represented

  in more detail with the help of Figure 4, the general

  14, ensures that the first synchronization signal

  C1 has a constancy of frequency just as good as the second applied synchronization signal 02, although it can be modified in phase and frequency

relative to the signal C2.

  For the compensation of speed errors

  If a control of the frequency of the first synchronization signal C1 is required, then an appropriate digital signal from a circuit 16 is applied to the circuit 14 to determine the speed errors. The circuit 16 is shown in more detail in FIG. 6. The synchronization signal C1 is conveyed from the first pulse generator 14 via a logic circuit 15 to the FIPO-13 circuit and thus controls the synchronization

  from the FIFO circuit 13. In a manner consistent with

  As such, for the time error compensators, addressing signals are generated in the logic circuit 15 for controlling a read-write memory (RAM) 17. This RAM 17 has approximately the capacity

  two lines, so that by means of an appropriate addressing

  time errors of up to about one line can be compensated for. At the exit of RAM 17,

  are then available digital signals in the-

  what time errors and speed errors

  are compensated as a first approximation.

  The digital signals are then applied

13.-

  to a circuit for the compensation of losses of

  slashes (drop-outs). Circuits suitable for this purpose are known per se and do not need to be described.

  in more detail in connection with the present invention.

  A particularly advantageous circuit adapted to the video processor according to the invention is described in the application

  patent FE 2153/85 filed simultaneously by the

dant.

  Following Circuit 18 for compensation

  signal loss, a circuit 11 is connected by means of which signals are placed in the digital signals to characterize the switching phase of the color carrier and respectively the first or the second carrier.

  of the second frame. Knowledge of the communication phase

  mutation is necessary for further processing because

  the color synchronization signal is downgraded to the

  of circuit 5 no longer contains this information. The

  characterization of a frame is used when reading

  the color television signal from the

  image memory for correct interpolation of

genes.

  Since high precision requirements must be

  can be imposed on the phase position of the

  chrominance in the case of conventional television systems.

  their quadrature modulation, another floor, denominated

* Me also compensates for fine time errors, is connected in the known time error compensators to a first stage. The time position of the color television signals is then shifted so that the color synchronization signals also coincide.

  exactly as possible with a color-coded carrier

  ence. In the case of the video signal processor shown in FIG. 1, this problem is solved by the circuit portions described hereinafter, a correction 14. further remaining speed errors being further performed. For this purpose, digital signals are

  applied through a digital converter

  than analog 19 to a phase comparison circuit 20,

  wherein the phase position of the synchronization signal

  color is compared with that of a reference color carrier. The output voltage of the phase comparison circuit 20 is applied via an analog-to-digital converter 21 to the phase position control input of a second generator

digital pulses 25.

  After a circuit 26 for compensation of the travel time of the circuits 19, 20, and 21, the digital signals arrive in the FIFO circuit 27 in which they are written with the high-precision synchronization signal 02. Reading from the FIFO circuit

  27 is done with the synchronization signal 03

  This is controlled by the digital pulse generator 25, and in the phase difference from the synchronization signal C2 - corresponds to the time errors remaining to be corrected. The digital signals thus read from the FIFO0 circuit 27, then arrive in a digital-to-analog converter 28 from the output of which the video signals are routed to a low-pass filter 49 serving to eliminate the synchronization disturbances still present in the signal. It connects an erase circuit 59 for the renewal of the erasure, an erase signal A being applied to this circuit 59. In a summing circuit 50 is set up a color synchronization signal and a synchronization signal (black burst) applied at 55. Then the color television signals arrive via

  switches 47, 48 to the output amplifiers 51, 52.

  At the outputs 53 and 54 of the output amplifiers 51, 52 15.- the corrected television signals are then available

for later use.

  The output signals of the circuit 18 for the compensation of the signal losses are written in an image memory 31 for the reproduction of the signal signals.

  color television with a speed different from

  sings, that is to say for a still image, a slow motion, an acceleration. To reduce the technical complexity, the digital signals are only registered with a range of binary digits of 8 in the image memory 31. Such image memories are described in detail

  in the literature correlated with the type of reproduction

  duction, especially in the case of

  segmented scanning magnets and do not need to be described in more detail in correlation with the

  present invention. Television signals in

  their read from the image memory 31 are applied to the signal switch 36 via two delay circuits of a line 33, 34, and

of a summing circuit 35.

  To avoid incidents of

  The signals applied with the signal switch 36 are transmitted in such a way that, in a first frame period, the color television signal read from the image memory 31 is transmitted and that in a second frame period the luminance signal of two further successively subsequent lines is interpolated and the chrominance signal is obtained by repetition of the chrominance signal of the first frame. Such

  circuit is already described in DE-C2-26 40 759.

  Using an exploitation circuit 37, the information

  added with circuit 11 are exploited with regard to

  identifies the frame in question and the switching phase of the color carrier. The frame information is applied

  to the signal switch 36 for control.

16.-

  The digital signals applied to

  of the signal switch 36 for producing the luminance signals and chrominance signals Y and C

  are respectively applied to a digital converter-

  analog 38, 39. The analog luminance signal is obtained with a low-pass filter 40 with a frequency

  limit of 3 MHz and sent via a

  Rector 41 to a totalizing circuit 42. The corrector 41 serves to increase the sharpness of the edges and can by

  example be a connected corrector known per se.

  The signal delivered from the digital-to-analog converter 39 arrives via a bandpass filter 43 in the form of a chromed signal.

  to a circuit 44, which retrograde respectively

  in the operating state when reading the digital signals from the image memory 31, the inverted polarity of the color difference signal U and operates a phase control of the chrominance signal for

  adapt it to the phase of a color carrier of reference

  ence. This avoids an error of 90 which, without this phase regulation, could appear because of the

  repeating a frame from the image memory 31.

  In addition, the waste time errors are thus compensated. A suitable circuit for this purpose is described

  in the patent application P 35 17 697.0 Schnell nachsteu-

  eradicate Phasenschieber ", filed by the plaintiff.

  The output signal of the totalising circuit

  tion 42 is erased in accordance with the standards in a

  faded cook 45 and provided in another circuit of

  summation 46 of synchronization signals and

  color synchronization. The switches 47, 48 allow the outputs 53 and 54 to be occupied independently of each other with the signals

  color television which are read from

  3t pictures, or with the color 17- television signals that are brought without memory

image to the output circuit.

  For the compliant video signal processor

  to the invention, a precise coupling of the signal of syn-

  C1 chronization with digital video signals is

  necessary. A circuit to obtain such an accou-

  Figure 2 shows the circuits 2, 4, 12 and 14 of Figure 2.

device according to Figure 1.

  In circuit 3, the signal obtained at

  firing of the pulse shaping device 63, using the switch 65, is introduced into the signal

analog video.

  The pulse shaping device 63, which can advantageously be produced by means of a phase-linearly low-pass filter, forms the signal

  R shown in Figure 3 and Figure 4. The

  essential part of the signal R is a gradual slope

  ascending (ramp) starting at the lower limit of the A / D converter 2 and extending symmetrically to the 50% line of the control

  is between one and two periods of the sync signal.

nization.

  The signal B appearing in this way is

  FIG. 3 and is applied to the analog converter

digital network 2.

  To control the switch 65, the impulse

  rectangular voltage denoted by D in Fig. 2, is derived from a horizontal frequency synchronization pulse applied from 61 (Fig. 1)

  using the pulse shaping device 64.

  The pulse shaping device 64 comprises

  in a manner known per se, a mono-

stable.

  18.- The analog-digital converter 2

  is fed with the synchronization signal C1. A part

  From the output of the analogue-to-digital converter 2, the digital color television signals are sent with an accuracy of 9 digits of binary digits via the connection point 7 to

further processing.

  The digital color television signals are furthermore also applied to a register 68 with an accuracy of 9 digits of binary digits or with a range of binary digits of 9.

  register 68 is synchronized by the synchronization signal

  it is further controlled by the pulse D produced by the pulse shaping device 64. In FIG. 4 is shown, with an enlarged time scale with respect to FIG. 3, in FIG.

  the line designated by B.E, the part corresponding to the

  General R digital color television signals, however shown to be visible in the form of analog signal. In the region of the pulse D falls several pulses of the synchronization signal C. The corresponding scanning values are transmitted from the register 68 and arrive at another register 70 and a window comparator 71 whose output signal controls the register 70. The window comparator known per se, delivers at its output a signal when the value of the input signal applied from the register 68 is between two values entered at 72 and 73, of

for example 10% and 90%.

  Before the start of the ramp, the scan values are very small, so the register 70

  is not released by the window comparator 71. The first

  value exceeding 10% of the total amplitude of the

  gaal D is entered in the register. If it then occurs 19.- still a sweep value lying below

  %, this last value replaces the previous value

  registered in the Register 70. Because, as

  this is described below, the scanning value is used

  for the regulation of the phase position of the

  scanning synchronization, it will set up

  normal operation, that is to say without action of particular disturbing quantities, a phase position such that the signal D is scanned in the vicinity of the point M.

  Using a programmable memory to read

  only the PROM (75), in which the shape of the ramp of the signal R is introduced, is determined from the scanning value, the position of departure from the midpoint M of the ramp of the scanning instant on which is based on this scan value. This value

  is read from the PROM 75 and is used to

  prescribe the phase position of the synchronization signal C1. When correcting time errors and speed errors, the operation of color television signals is

  color synchronization. The preconditions can

  can be created for this purpose, because the color synchronization signal is superimposed on a part of the

  signal, which connects to the predefined function

  finished and whose amplitude value is preferably

  50% of the amplitude range of the video signal,

  as shown in Figure 3.

  The generation of pulses 14 and 25 (FIG. 1) must satisfy the following requirements: both the phase position at the beginning of the lines and also the frequency must be controllable with

  control signals applied from the outside. Stability

  frequency should be approximately one color carrier in the vicinity of 10 6. The phase and 20- the frequency should follow, to a large extent without

  inertia, the changes of the control signals.

  The requirements can hardly be fulfilled with conventional oscillators such as quartz oscillators and on-off oscillators. The pulse generator is therefore used.

  numerical representation shown in Figures 5 and 6.

  In the case of the device according to FIG. 5, the reference 101 denotes a 20-position totalizer with an output 102 and a first and a second input 103, 104. The 20 bit positions of the output

  102 are connected to the inputs of a register with 20

  105 whose outputs are in turn connected to the first input 103 of the totalizer 101. The register 105 is controlled with the synchronization signal C2

applied in 106.

  For each synchronization pulse

  plicated at 106, a change of the digital

  the value applied to entry 104 of the totalisa-

  101 being then respectively added. If the total

  The user has reached his maximum capacity, we start from scratch. The 8 low value positions of the input 104 are connected via a register 107 with a first 8-position input 109. A second 8-position input 110 is connected through another register 111 with the 8 value positions

  higher than entry 104. The 4 intermediate positions

  The values of the input 104 are zero, which is represented in the figure by a ground sign. In addition, the position of the input 104 with the identifying value immediately following the maximum value, is fed through a register with a ONE. The synchronization signal C2 is applied via the input 106 to the synchronization inputs of the registers 21.

  In addition, the registers may be alterna-

  blocked by a synchronization pulse

  plicated to the input 112, the synchronization pulse

  being applied to register 107 by means of

  of an inverter 113. The alternative blocking the regis-

  107 and 111 with the synchronization pulse.

  applied in 112, means that, on the one hand, the 8 posi-

  higher value values of entry 104 are

  for a short time on the values of the signal applied at 110 and that, moreover, between the synchronization pulses a one applies to the position immediately following the highest position of the input 104 and that at the positions of low values of the input 104, applies the signal brought to 109, the other positions

being on zero.

  By the repeated addition of one into the posi-

  immediately following the highest position, and the value applied at 109, a value increasing linearly in time of the output signal of the totalizer 101 or of the register 105 is obtained.

  the capacity of the totalizer 101 is reached, the value

  comes abruptly to zero and then increases again linearly in time. With one at the position immediately following the highest position, the

  Frequency is in principle determined. With the app value

  plicated at 109, the slope of the increase and therefore the frequency of the output signals of the register 105, can be controlled extremely finely. In that case,

  the frequency of the output signals is understood to mean

  not the frequency of synchronization, but the frequency

  analog signals that are represented by

digital signals.

  If now during the sync pulse

  the value applied through the

  110 is brought for a short time to the eight 22. -

  positions of higher value of entry 104, the

  By increasing the linearity of the sawtooth-shaped tension in time, it is set to a starting value from which the increase is continued. With the value of the signals applied at 110, an adjustment of the phase position between the output signals of the register and the synchronization pulse applied at 112,

is possible.

  The frequency at the output of the register 105 corresponds to approximately a quarter of the frequency of the signal

  synchronization C2 applied in 106.

  To simplify the subsequent frequency multiplication, the sawtooth function is converted to a sinusoidal function in read only programmable memory (PROM) 114. For this purpose, the reproduction of the sawtooth function is sinusoidal is deposited in the PROM, so that when introducing the output signals of the register 105 into the addressing input of the PROM, it appears

  data outputs of the signals which represent a function

sinusoidal

  For the derivation of the synchronization signal

  to be obtained from the output signals of the register, it is not necessary to have a high precision such as that which has been chosen for the implementation of the accumulation process by means of the totalizer 101 of the register 105. Consequently, only the ten high value positions of the output signal of the register 105

  are applied to PROM 114. Similarly, the signals of

  of the PROM 110 have only an extension of 10 digits

  binary frequencies and are brought through a

  Fig. 118 to a digital-to-analog converter 115, the output of which is connected to a frequency multiplier 116. The timing signals appearing at the output 117 of the frequency multiplier 116 can be altered with respect to their frequency, in the frequency zone of the synchronization signal C2 applied

  In addition, a phase shift of several

  synchronization is possible. In the case of the circuit used as digital pulse generator 14 (FIG. 1), the frequency can be modified according to steps

  extremely small. For example, the amendment

  The LSB (least significant bit rate) at input 109 corresponds to a change in the phase position with respect to the frequency signaling pulses.

horizontal of 0.48 ns per line.

  The totalizer 101, the registers 104, 107 and 111, as well as the circuit 114 can be easily

  made using conventional functional digital blocks

  c. Due to the relatively high frequencies, in an example realized in practice,

  Function blocks of the F series (= fast). The registers

  very then were realized with function blocks of the type P 374, several registers then being connected

  in parallel because of the large extent in bi-numerals

  ners. In the same way, in the case of the

  totalizer 101 which has been realized with five function blocks

  The circuit 114 can be realized with a PROM of the TBP 24 541 type and a PROM of the TBP 28 586 type. Finally, a suitable digital-analogue converter can be obtained under the type designation.

TDC 1016.

  Even if the constitution of a multiplier

  frequency does not present any difficulty for a specialist

  list, it should be described however with reference to the circuit schematically shown in Figure 6, the constitution of a simple frequency duplicator. Two

  these frequency duplicators are connected to one of the

  the other in circuit 116 (FIG. 5). The signal

  sinusoidal output by the nuneric-analog converter

  24 (Fig. 5) is brought via the point

  branch 120 to the two inputs of a multiplier 121.

  At the output of the multiplier 121 there is thus a signal which

  consists of a double-frequency sinusoidal oscillation

  quence and a portion of DC voltage. The part of

  DC voltage could in itself be eliminated by a simple

  full RC coupling. In the circuit represented, he is

  provided a band-pass filter 122, 123, 124 which, apart from the DC voltage component, also eliminates

  possible harmonies arising from non

  linearity of the multiplier 121. At the output 125, is then available a sinusoidal oscillation with double frequency. As a frequency multiplier, other circuits can also be used, for example

PLL circuits.

  Figure 2 schematically represents the

  troduction and separation of pulses 2H and 2V such

  they are carried out in the circuits 11 and 37 (Figure 1).

  In two of the nine parallel data links are inserted switches 131, 132, which are controlled by

  a pulse shaping device 133. The dis-

  pulse shaping is synchronized by a horizontal frequency pulse H and delivers to

  switches 131 and 132 a pulse width 500 ns.

  Meanwhile, the pulses 2H and 2V applied from the circuit 61 (Figure 1) are introduced. during

  the remaining part of the line period, the conmuta-

  131 and 132 are in the upper position

  and thus also connect the links for the seventh

  me and the eighth binary digits. In the circuit 37,

  the links for the seventh and eighth digits

  are connected to the entries of a two-digit register D

  134 which is synchronized by the H pulse.

  In the register D, pulses 2H and 2V are then available.

  In Figure 8 is shown, more in de-

  tail, the circuit 16 (Figure 1) for the determination of speed errors. The circuits 2, 12, 13 and 14 and their cooperation are already described in correlation with

Figure 1.

  The circuit 136 to which the digital color television signals are applied constitutes a selection circuit using which

  selected during the synchronization signal

  color formation are formed. In this circuit 136 the scanning values of the digital signals during the color synchronization signal are checked to see if they are within an area in which the increase of the sinusoidal function

  is important enough to get through

  of the scanning value considered, an informa-

  sufficiently precise on the phase position. This is the case about half of the amplitude range of the color synchronization signal, ie for the phase positions for which the sinus

is between -0.5 and + 0.5.

  To convert the scan values into a phase value by calculation, the output signals of the circuit 136 are applied to a circuit 137 for forming the sine wave. This circuit 137 consists essentially of a read-only memory (PROM),

  in which is written an appropriate functional table.

  Like, at the color synchronization signal can

  to be superimposed on statistical disturbances, which

  a phase measurement, the average value is formed in a circuit 138 from four measurements inside.

  a color synchronization signal.

  Since the synchronization signal C1 conditions

  By the phase regulation with the aid of the circuit 12 26 may present a sudden phase variation at the beginning of the line, the value of the phase signal

  corresponding to this abrupt phase variation is sub-

  processes in a subtraction circuit 139 of the output signal of the circuit 138. From the signals obtained so far, characterizing the absolute position of

  phase of the color synchronization signals, we define

  Nit using the register D 140, which is applied a synchronization signal H, and the subtraction circuit

  141, values that characterize the length of a line.

  According to the rules of the commutation law, another success

  assignment of subtractions can also be chosen.

  With a read-only programmable memory 142, these values are compared with values

  deposit for the length of the lines, which are

  phase angle of the color carrier

  in read-only programmable memory 142.

  Thus, at the output of the circuit 142 there is a value of the speed error which is however reported

  at the frequency of the synchronization signal C1. The frequency

  the timing signal C1 is in turn dependent on an applied frequency control signal

  to the pulse generator 14. Fear to obtain an abbreviation

  solute of the speed error, the frequency control signal is accordingly added to a totalizer

  143. The signal thus obtained may be applied by the

* by means of a register D 144 to the pulse generator 14 as a frequency control signal for the

next line.

  It can be expected to establish an average of the speed error signals on several lines, which is indicated in the figure by the register

and the summing circuit 146.

  In the case of segmented scanning magnetic stripe apparatus, a special derivation of a signal 27. -

  correction for the respective first line of a seg-

  possibly necessary. Such a circuit is

  147 and is described in more detail in correlation with

  9 and 10. With the aid of the switch 148 which is controlled via a control circuit 149 by a head switching pulse K, the output signals of the circuit 147 are fed into

  the correction signals for the following lines.

  The diagram shown in FIG. 9 shows velocity errors as a function of time as they may occur in the signals applied to the video processor according to FIG. 1. The curve represents the evolution of the speed errors during the scanning of 4 segments. 1, 2, 3 and 4. Respectively at the beginning of a segment, there is a sudden variation A or B while the speed error only slightly changes at

  inside a segment consisting of 52 lines. The segments

  1 and 3 are reproduced by a first magnetic head

  tick, while segments 2 and 4 are reproduced

  by a second magnetic head.

  It appeared that sudden variations in speed errors remain in practice constant

  when passing from one head to another. In total, the

  speed errors is, however, subject to

very fluctuating statistics.

  In the method used, it is assumed that, within a segment, a speed error can be determined by measuring the length of a line and can be used for correction in the lines.

  following. However, as for the correction of the first

  first line, there is no analogous value available

  from a previous line, we use the

  the abrupt variation A or B from the change of heads of the same preceding direction to be able to conclude with the aid of this value, and from the 28- last line of one of the segments, as far as the correction value for the first line of the segment

  following the next segment.

  In many cases of application, the

  their sudden variations A and B are practically

  identical, so that it is sufficient to conclude from a change

  segments on the next. In known magnetic tape devices with segmented scanning, there is no reproduction signal available after

  the last line of a segment to determine the length of

  this line. Consequently, in a complement of the method according to the invention, the error of speed of the penultimate line is used to determine the sudden variations A and B as well as for the error

  speed of the first line of the next segment.

  The process according to the invention will be described in more detail below with reference to a numerical example. A correction value must

  be determined for the first line of segment 4.

  For this purpose, the value measured for the fifty-first line of the preceding segment 3, which is also used as a correction value in the fifty-second line, is added to the magnitude A. The magnitude A is

  calculated from the difference of the determin-

  for the first line of segment 2 and for the fifty-second line of segment 1, the latter value being derived from the length of the fifty and

first line of the first segment.

  The device according to FIG.

  the functions of circuits 147 and 148 (FIG. 8) are applied via a D-register

  , synchronized by a pulse of horizontal frequency

  zontal, the speed errors determined by measurement

  lengths of lines in the form of digital

  range of 9 binary digits. For the 29. -

  value determined at the end of the fifty-first li

  it is not available only for the correction during the fifty-second line, but also for the determination of abrupt variations A or B, the pulse H at the beginning of the first line is not

  applied to the D 155 register synchronization input.

  The digital signals representing the correction values, pass through a totalizer 156 with which the values A or B are added only

  in the first lines. At this totalizer 156,

  rope a limiter 157 which guarantees that the maximum value

  or minimum given by the binary number at 9 posi-

  tions is transmitted, if by reason of the addition in the

  totalizer 156, an excess or a lack

reduce. At the totalizer 157 is connected, via a register 158,

  which is synchronized with horizontal frequency pulses, the output

  159 from which the correction signals can

  applied to known correction circuits

in itself.

  The output signals of the limiter 157 are further applied to another register 160 which stores the correction value for the fifty-second line of each segment, until the appearance of the next correction value obtained by measuring the length from the first line. From register 160, the

  signals that are stored are taken in reverse form.

  seized, so that in the totalizer 161, is formed

  the difference of the respective correction values

  the first line of a segment and the last line of the preceding segment. These values A and B are stored sipar - have in the registers 162 and 163 for the duration of two segments, and being shifted from one segment to the beginning of the segment which follows the segment 30.- immediately following, these values are applied to

totalizer 156.

  Registers 162 and 163 are synchronized

  with a pulse H of horizontal frequency. Their experiences

  are respectively controlled via an input OC with the corresponding signals OC1 and

  0C2, so that no signal from the registers

  162 and 163 are applied to the totalizer 156

  during the second line and until the fifty second.

  As already mentioned above, the

  their sudden variations A and B of the signal may in practice be identical under certain conditions, and in this case only one of the registers 162 or 163 is sufficient. (FIFO means: buffer register of the first output type /

first entry).

31.-

RE V E N D I C AT 1 0 N S

  1.- Video signal processor, wherein

  video signals taken from an information carrier

  are converted into digital signals and are stored in digital form, a first synchronization signal being furthermore used for the analog-to-digital conversion and for the writing of the digital signals in a first intermediate memory, and at the output of this first memory intermediate,

  to which a second reading is applied for reading

  synchronization circuit, is connected a circuit for the compensation of signal faults, circuit to the output of which is connected a second intermediate memory in which the digital signals are written with

  the second synchronization signal and from the-

  which the digital signals are read with a third synchronization signal, a processor characterized in that

  that, moreover, a digital image memory (31) is connected with

  to the circuit (18) to compensate for

  and that the output of this digital memory of

  ge (31) is connected to a circuit (33, 34, 35, 36) for the separate processing of the chrominance fraction and the luminance fraction of the digital signals taken

  from the image memory (31).

  2.- Video signal processor according to the

  claim 1, characterized in that the digital signals

  applied to the image memory (31) are derived from

  analog-to-digital conversion of the video signal

  plicated as a color television signal (coding

closed).

  3. A video signal processor according to claim 2, characterized in that at the output of the image memory, delay circuits of a line (33, 34), a summing circuit (35) and a switch signals (38) are connected so that during a first frame period, the luminance signal and the chrominance signal are obtained from the signals

  numbers belonging to a frame and that during a se-

  frame period, the luminance signal of two subsequent successive lines of the same frame is inter-

  polished and that the chrominance signal is obtained by

  the chrominance signal of the same frame.

  4.- Video signal processor according to the re-

  claim 3, characterized in that the output signals

  of the signal switch (36) are respectively

  connected to a digital-to-analog converter (38, 39), the output of the digital-to-analog converter (39)

  for the chrominance signal being applied by the

  a bandpass filter (43) and a color subcarrier phase circuit (44) to one of

  inputs of a totalizing circuit (42), the output of the con-

  digital-analog transformer (38) provided for the

  luminance signal being applied via a passband filter (40) and a correction circuit

  (41), preferably a corrector connected, to the other

  of a totalizer circuit (42), and that the color subcarrier phase circuit (44) comprises a

  controllable phase shifter that is likely to

  tible to be ordered using a phase comparison

  between the color synchronization signal and a por-

reference.

  5.- Video signal processor in which

  video signals taken from an information carrier

  are converted into digital signals, which after time error correction and signal loss compensation are written to a digital memory

  of image, processor characterized in that

  to the image memory (31) is added an identification signal, which contains information with respect to the time relationship of the signals 33.

  compared to a conventional television signal.

  their reference, to account for the frame succession and the sequence of the color subcarrier

  conditioned by the color television system con-

  is considered, while there is provided after the image memory, a circuit for exploiting this information, circuit that the signal switch (36) provided after the image memory (31) controls so that the signals read from the memory are adapted to the reference color television signal with respect to the frame succession and the switching phase of the

underprotector of color.

  6.- Video signal processor in which

  video signals taken from an information carrier

  are converted to digital signals and are stored

  in digital form, a first synchronization signal

  used for analogue-to-digital conversion and for digital signal

  first intermediate memory, a circuit for

  thought of the signal faults being connected to the output

  part of this first intermediate memory to which

  is applied for reading, a second sync signal

  while at the exit is connected a se-

  intermediate memory in which the digital signals

  are registered with the second sync signal.

  and from which the digital signals are read with a third synchronization signal, characterized in that the digital signals are applied to a circuit (16) for determining speed errors and the output signals of

  this circuit (16) for determining errors in

  These are fed to pulse generators (14, 25) which are provided to generate the first and third synchronization signals to control the frequency of the first and third synchronization signals.

  7.- Video signal processor

  claim 6, characterized in that the first intermediate memory consists of a FIFO circuit (13) with a register and read memory (RAM) (17) connected thereto. 8. Video signal processor according to claim 6, characterized in that prior to the analog-to-digital conversion, a synchronization signal of

  the color contained in the applied video signals, shall be

  mined through a limiting and filtering circuit (5) which keeps the amplitude of

  this color synchronization signal.

  9. Video signal processor according to claim 8, characterized in that in a signal of

  color synchronization, the phase position changes

  per line in accordance with the PAL color television process is switched backward prior to analog-to-digital conversion. 10.Processor of video signal according to the

  claim 6, characterized in that a control signal

  is applied to the first pulse generator (14) for controlling the phase position of the first synchronization signal, which control signal is derived by scanning a signal set up in the video signal before the analog-to-digital conversion, and which, according to a predefined function, goes from a first value to

a second value.

  11. Video signal processor according to claim 10, characterized in that the signal, which according to a predefined function changes from a first value to a second value, is coupled with a pulse.

  of horizontal frequency synchronization which is de-

  delivered by a pulse generation circuit, this circuit

  pulsed pulse generator comprising a known signal switch 35 (59), a demodulator (60),

  a pulse separation circuit (61), the

  video signals from two magnetic heads being

  likely to be applied to the inputs (57, 58) of the

  channel switch (59) and this channel switch (59)

  being switched during line scanning.

  12.- Video signal processor according to the

  claim 6, characterized in that a sync signal

  high accuracy (02) is likely to be applied to the first and second pulse

  (14, 25), and that, with respect to this synchronizing signal,

  of high precision so applied, the position of

  phase and frequency deviation of the synchronization signal

  obtained (Cl, 03) is likely to be controlled by

the digital signals applied.

  13.- Video signal processor characterized

  by implementing at least one pulse generator

  digital outputs (14, 25) in which the output (102) of a digital totalizer (101) is connected via

  from a register (105) to the first entry (103) of this

  digital talisman (101) and wherein in addition, at a second input (104) of the digital totalizer (101),

  triggered by a frequency synchronization pulse

  horizontal, a first value may be applied for a short time, while during the remainder of the line period another value is

likely to be applied.

  14.- Video signal processor according to the

  Claim 13, characterized in that other registers

  (107, 111) are connected upstream of the second

  (104), registers with which, depending on an im-

  horizontal frequency synchronization pulse, respec-

  Actually, several higher value positions of the second input (104) may be connected to an input (110) for the first value, or else 36 may have several low value positions.

  to be connected with an input (109) for the second

  their. 15. Video signal processor according to claim 14, characterized in that the digital totalizer (101) and the register (105) are provided for

twenty binary positions.

  16.- Video signal processor according to the

  claim 13, characterized in that a sync signal

  chronization is applied to a synchronization input

  (106) of the register (105), the frequency of this signal being constant and being in the frequency zone of the synchronization signal to be obtained, while by an appropriate choice of the zone of the second value, the frequency of the signal the output of the register (105) is a fraction of the frequency of the synchronization signal thus applied, and that at the output of the register (105) a

  frequency multiplier (116) is connected by the

  via a digital-to-analog converter (115).

  17. A video signal processor according to claim 16, characterized in that a circuit (114) for shaping a sinusoidal oscillation is arranged between the register (105) and the converter.

digital-analog (115).

  18.- Video signal processor according to

  claim 17, characterized in that the multiplication

  frequency converter (116) consists of several

  Frequency plicers that each contain a multi-

  analog plier (121) and a filter (122, 123, 124)

  tuned to the output frequency.