FR2583238A1 - Plesiochronous digital transmission device with expanded buffer memory - Google Patents

Abstract

A digital transmission relay includes input and output circuits which are interconnected by digital information processing and storage means. These processing means comprise an addressable buffer memory 33 of large capacity. Two counters 41 and 51 define a write pointer and a read pointer respectively in this memory 33. With each end-of-cycle of the counter 51, a logic circuit 6 determines the deviation between the two pointers, and shifts one of them by a predetermined number of addresses when this deviation is below a predetermined margin, the direction of the jump being related to the direction of the deviation.

Description

Plesiochronous digital transmission device with extended buffer memory.

The invention relates to digital transmission networks involving mobile relays, such as satallites.

Such a network comprises a departure station on the ground, the relay station which constitutes the satellite, and an arrival station which is in principle again on the ground. Furthermore, it is well known that digital transmission necessarily takes place with reference to a clock signal. A distinction will therefore be made between the departure clock, the satellite clock and the arrival clock.

The satellite is in principle of the geostationary type. This means that its orbit is determined so that this satellite is substantially fixed relative to the earth.

If it were rigorously fixed with respect to the earth, the satellite would be assimilated to a ground station.

In practice, due to the instability of the satellite in its orbit, the path that the waves will undergo on one side between the departure station and the satellite, on the other between the satellite and the arrival station, n is not of constant duration. These variations produce the equivalent of a Doppler effect, for the understanding of which it is convenient to consider the satellite as a mirror which would move slowly.

Everything happens as if the source of the digital signals and their destination point are moving relative to each other, and we therefore observe a drift. Thus, in short, the movement of the satellite results in a clock drift or "jitter" on the transmitted data. Technically, clock jitter is called "jitter", as it occurs between two stations which communicate and are in relative motion.

Those skilled in the art know that, when digital information is thus transmitted through different stations, these will operate with neighboring time references or clocks, hence the name of plesiochronous digital transmissions.

Reference is now made to standards for multiplexed digital transmission of the MIC (pulse code modulation) type. According to a known standard, for which the nominal bit rate is 2048 kilobits per second, the transmission is done on 30 digital channels. It uses a compression / expansion coding law, which does not intervene directly in the present invention. The same standard specifies the temporal structure of the transmission of digital information, which is important to remember.

This temporal structure is subdivided in the following way - it is firstly decomposable into a series of multiframes, each with a duration of 2 milliseconds; - each multi-frame is in turn broken down into 16 frames, each of which lasts 125 microseconds; - each frame is finally subdivided into 32 words, each lasting 3.9 microseconds. The words of ranks 1 to 15 and 17 to 31 define 30 channels of effective digital transmission; the words of ranks zero and 16 are used for the transmission of digital service information.

The word of rank zero gives a frame alignment signal, transmitted in two parts, which alternate every other frame. The rank word 16 serves as a multi-frame locking word, in the first frame of a multi-frame; in the other 15 frames of the multi-frame, it is used for signaling relating to the operation of each of the transmission channels. The word of rank 16 then interests, each time, two of the 30 transmission channels, and this cyclically; for example, the rank word 16 of the second frame of a multi-frame will carry out the signaling for the transmission channels contained in frames 1 and 17, that of the third frame, for the channels of frames 2 and 18, and and so on.

At the departure station, as at the arrival station, digital transmission involves an auto-switch.

From its own clock, the auto-switch must define or acquire the multi-frame and frame synchronizations, so that we can keep the correspondence between the digital information of the different channels and their respective recipients.

It is clear that when a clock difference occurs during transmission, the auto-switch can lose these synchronizations. The transmitted information is then unusable, as long as synchronizations are not restored.

By construction, the auto-switches can support a small clock drift, corresponding to short-term jitter. It is known to equip auto switches for this purpose with an input or output memory, of limited capacity.

The problem is that the drift that is induced during transmissions by a satellite often exceeds the memory accumulation capacities of the switch. In general, this results in a loss of information. In the case of multiplexed digital transmissions of the MIC type, the consequences are more serious, since it will most often appear a total loss of synchronization.
This poses a real problem during digital transmissions using a geostationary satellite as a relay.

Thus, one of the aims of the present invention is to allow the transmission of digital information between two earth stations and via a satellite, despite the movements or instabilities of the satellite in its orbit.

Another object of the invention is to control the slippages or clock drifts which may occur during such a transmission, so as not to cause loss of frame or multi-frame alignment of the transmission equipment. , and this without having to decode the frame and multi-frame structure of the transmitted digital information.

Yet another object of the invention is to use for this purpose a buffer memory, capable of being incorporated into one of the stations (at least), and the capacity of which can be adapted in a ratio of 1 to 8 without modification of its control electronics.

The proposed digital transmission relay device is of the type comprising input circuits capable of receiving digital information, output circuits capable of transmitting digital information and processing means capable of storing the information received by the input, to the rhythm of the reception clock, as well as to restore them to the output circuits, to the rhythm of a local clock.

According to a first characteristic of the invention, these processing means comprise - a large capacity addressable buffer memory; a first cyclic counter forming a writing pointer for addressing the memory at the rate of the reception clock; a second cyclic counter, of the same capacity as the first, forming a read pointer for addressing the memory at the rate of the read clock; means which, when one of the counters goes into a predetermined state, determine the difference between the scores of the two cyclic counters, and cause one of the counters to jump by a predetermined number of addresses, when said difference is less than a predetermined margin, the direction of the jump being linked to the direction of the difference.

Preferably, the digital information transmitted is of the built-in clock type, such as that known under the name of HDB3.

In a first embodiment of the invention, the detection of the transition to the predetermined state is done on the second counter, that is to say on the counter forming the read pointer.

The jump can then interest the second counter itself, or preferably the first counter, that is to say the one responsible for writing score.

According to another aspect of the invention, the amplitude of the jump corresponds to a time interval of 2 milliseconds, or a multiple of this value.

Very often, digital transmission is multiplexed in time over a predetermined overall period. In such a case, the amplitude of the jump is equal to this global period, or multiple of it.

Furthermore, initially, or when transmission resumes after interruption, the two counters are brought into positions offset from one another by approximately half their capacity.

According to another aspect of the invention, the buffer memory is organized in words, and the information both received and transmitted are organized in words of the same size, before writing and transmission, respectively.

In a particular embodiment, the words are 8 bits.

According to another aspect of the invention, the difference between the size of the counters and twice the predetermined margin is chosen to be greater than twice the peak-to-peak jitter that the transmission of information can undergo.

The present invention finds a preferential application when the transmission involves a geostationary satellite, and the initial positioning of the two counters is carried out taking into account the situation of the satellite with respect to its circadian clock drift.

Other characteristics and advantages of the invention will appear on examining the detailed description below, and the appended drawings, in which - FIG. 1 is a schematic electrical diagram of an embodiment of the device according to the invention ; - Figure 2 is a time diagram schematically illustrating the circadian drift of a geostationary satellite; and - Figures 3A, 3B and 4A, 4B respectively show two jumps in opposite directions made by the device according to the invention.

The attached drawings are essentially certain. They are incorporated into the description to serve both to supplement it and to define the invention, if applicable.

Although the invention is susceptible of other applications, it will now be assumed that the device of FIG. 1 is used with a geostationary satellite. First, it is assumed that the satellite receives a signal from a first earth station, and that it retransmits this signal towards a second earth station. We will examine the case of a two-way transmission below.

The received signals arrive, after the usual high frequency reception stages, at an input stage 10 of the device. This stage comprises a transformer link, capable of transmitting the digital data with incorporated clock coded in the form known as HDB3. The output of the input stage 10 is applied to an HDB3 signal decoder, referenced 11. This decoder 11 thus has a clock output denoted H and a data output denoted D. All of the circuits 10 and 11 forms the input circuits 1 of the device.

It would be possible to process digital data bit by bit. The device illustrated processes them by bytes, which each make 8 bits. Of course, larger words are possible.

A circuit 2 will allow the passage to the bytes to be carried out. This circuit includes a divider by 8 counter, reference 22, which will be used to define the internal reception clock for the device. The circuit 2 also includes an 8-bit register, referenced 21, which receives in sequence the data available on the output D of the decoder 11. To this register 21 is associated its own clock circuit 20, which receives the signal H from the decoder 11. Depending on the signal H, the register 21 will group the data received in 8-bit words.

reference is immediately made to the output circuits, taking into account their similarity to the input circuits.

The output circuits proper comprise an HDB3 coder referenced 91, followed by the transformer output stage 90. The coder 91 receives a local clock or HREF reference clock, which will control the reading of the data.

A circuit 8 takes account of the byte structure of the words inside the device. In this, it comprises a divider by 8 referenced 82 of the reference clock
HREF. This reference clock is also applied to the input CK of the clock circuit 80 associated with an 8-bit register 81. And it is the serialized data output of this register 81 which supplies the encoder 91 bit by bit.

We immediately observe that the output of circuit 82 is also applied to an input PL of circuits 80 associated with register 81. Every 8 pulses of the reference clock, this input PL will allow parallel loading of register 81 using of data coming from inside the device, on a bus referenced 35 which will be discussed again below.

It can also be seen that the dividers by 8, 22 and 82 supply their divided outputs to a circuit 7 responsible for managing the write / read conflicts, reading having priority. The general principle of such a circuit is known.

When a pulse from the HREF reference clock and the reception clock appear simultaneously, circuit 7 will have the effect of first passing the HREF read reference clock, then of delaying a little the writing clock H, so that reading has priority. In a way, this is an anti-coincidence circuit, the principle of which is known to those skilled in the art.

To achieve this anti-coincidence, circuit 7 provides a write / read isntruction, denoted R / W. It also provides an order which will allow the execution of the writing at an address defined by a counter. It is immediately noted that this order is applied to the output validation input, denoted OE, of the member 30, as well as to a validation input of a counter 41.

Finally, the divided output of counter 22 is applied to the load validation or clock input of a control circuit associated with a three-state latch memory, referenced 31.

This lock memory 31 has the effect of acquiring and freezing the 8-bit digital word available at the output of the register 21, at the instant defined by the output of the divider by 8, 22.

It will then deliver this word on its own output, in response to the command which comes from circuit 7 on the input OE of the member 30.

In this situation, the circuit 7 also provides a write order, that is to say that the signal R, 'W is at 0, and inhibits its validation of output, since an inverting gate 32 puts at true state the signal OE which is the complement of the validation signal of output from memory 33.

In this way, it is possible to introduce write data into memory 33.

Each time, this introduction is done by an address defined by the counter 41, which is a preprogrammable counter of 11 or 14 bits, depending on whether the memory 33 has a capacity of 2 kx 8 or 8 kx 8. A circuit 40 allows the 'initialization of the meter upon commissioning or each resumption of service, as will be seen below.

From this initialization, the counter 41 operates in cyclic counting, at a frequency which is that defined by the output of the divider 22, certain write clock pulses being offset when they coincide with a read clock, and this by the effect of circuit 7.

The address word thus available in the counter 41 is applied to a three-state buffer circuit 42, which transmits it on the address bus 36 of the memory 33.

We now understand that writing to memory 33 is done in the direction of increasing addresses, in a manner defined by the operation of the cyclic counter 41.

In the reading state, the management circuit 7 supplies an R / W signal equal to 1, while the signal OE is at 0, thus authorizing the memory to present on its output the information that it contains, at an address always defined by the address bus 36. But the address now results from the output of a three-state buffer circuit 52, which itself relays the address bits from a counter 51 which has 11 or 14 bits as for the counter 41. The counter advances at a frequency defined there again by the reference clock divided by 8, since this clock signal comes from the output of the divider 82, to be applied to the clock input of the circuit 50 controlling the counter 51. It is immediately noted that this circuit 50 also includes a transfer output, denoted Co, the role of which will be seen below.

We now understand that the content of the memory will be alternately (or almost alternately) subject to writing and reading, at the respective rhythms of the reception clock H and the reference clock
HREF (or another clock which would come from one of the stations located on the ground).

The problem posed will now be defined in more detail, with reference to FIG. 2.

This figure is a graph which illustrates the variations of the clock phase PH as a function of time, taking into account the movements of a geostationary satellite in its orbit, and the residual ellipticity of the latter.

The figure shows variations of small amplitude and in the very short term. It also shows a 24-hour periodicity, which has been represented schematically in sinusoidal form. The amplitude of the phase variation linked to this circadian rhythm, reduced in time, is around 1 to 1.5 milliseconds for a young satellite. It can be up to 2 to 3 milliseconds for a satellite that has been in service for a long time, and whose energy available for orbit corrections is less important.

For comparison, it is recalled that the data transmission rate is 2 megabits per second.

We immediately understand that the variations or drifts of the clock mentioned above will be the source of undeniable difficulties.

A receiving ground station will supply digital data to an auto-switch. It is known to interpose between the station itself and the auto-switch a buffer memory. But the buffers are small, and it sometimes happens that the data read in the buffer does not exit faster than new data received is introduced. Even more seriously, it happens that the data received are at a rate at this point higher than the output rate of the buffer memory that some of the data received is not transmitted to the auto-switch.

In transmissions in general, this phenomenon is regrettable, in particular with regard to data in the voice band, since such data are transmitted via frequencies modulated in phase and / or in amplitude, according to certain combinations. As soon as we delete digital samples, or on the contrary repeat some of them, phase errors occur, which distort the voice information.

As it is more multiplex digital information of the MIC type, the jumps can have disastrous consequences: one can indeed lose the synchronization of frames or that of multi-frames, or that of words, which causes a loss of time. considerable, by the obligation to repeat a significant part of the messages, after the loss of synchronization encountered has been diagnosed.

You would think that things will get better if you manage to keep the word synchronization, even the frame synchronization. In fact, it is not. Indeed, such a defect has complex consequences.

If for example it is the multi-frame structure which is destroyed, it must first be realized. Indeed, transmissions are always accompanied by a certain immunity against errors, and it is not at the first anomaly that we admit that we lost this synchronization of multi-frames. It is therefore necessary to have observed several times the loss of the synchronization of multi-frames to admit that it is actually lost.

Once we have noticed the loss of multi-frame synchronization, we proceed to a search which is not quickly acknowledged: in other words, we thus enter a kind of alarm phase, which extends over a much longer time interval than the time anomaly that caused the loss of multi-frame synchronization.

There therefore appears to be a clear accentuation of the short time defect, through the play of the synchronization loss detection cycle, and the acquisition cycle of a new synchronization.

From a structure such as that illustrated in Figure 1, the invention provides an elegant solution to these problems.

This solution resides in the fact that means are provided which, on passing one of the counters 51 or 41 into a predetermined state, determine the difference between the address scoring performed by these two cyclic counters, and cause them to jump one of the counters 41 and 51 of a predetermined number of addresses when said difference is less than a predetermined margin, ie the direction of the jump being linked to the direction of the difference.

It then suffices that the amplitude of the jump corresponds to a time interval of 2 milliseconds or a multiple of this value, in the case of the multiplexed transmission MIC already mentioned.

More generally, the digital transmission being multiplexed in time over a predetermined overall period, the amplitude of the jump is made equal to this overall period, or multiple thereof.

In order to further limit the risks of one of the counters 41 and 51 being exceeded by the other, on initialization of the system or on each transmission resumption, the two counters are pre-positioned in offset positions. one of the other by about the amplitude of the jump or a multiple thereof, preferably about half the capacity of the counters.

The word "approximately" reflects the fact that the situation of the satellite relative to its circadian time drift as illustrated in FIG. 2 can also be taken into account. Indeed, if initialization or return to service is performed on the middle line LM in Figure 2, we can then shift the counters exactly half their capacity. Of course, we will act differently if the drift is at one of its MAX or min extremum, because it is then possible to bring the two counters to values very close to each other, in a direction such that the subsequent variation of the drift tends to spread them apart without them crossing.

For its part, the predetermined margin which forms the threshold from which a jump will be made can be established as follows: the difference between the size of the counters 41 and 51 and twice the margin is chosen to be greater than twice the peak-to-peak jitter that may be subject to the transmission of information. This relationship combines clock counts and time values, which can be made compatible since the average value of the clock frequency is known.

Another aspect of the invention resides in that the relative situation of the two respective writing and reading pointers is examined periodically, with respect to the counting of one of these counters. This can be done from the write counter 41. The embodiment described, however, starts from the read counter 51. For this purpose, each time the latter has completed a lap, its carryover output Co, manifested in the circuit 50, activates a multi-frame jump decision logic circuit (more or less).

At this instant, the logic circuit 6 receives from the address bus 36 the address value defined by the write counter 41.

In the example chosen, the predetermined margin has a length of two frames. It is also assumed that the counters 41 and 51 have a capacity of 11 bits.

This is illustrated in FIGS. 3 to 6, where a circle represents a complete revolution of memory addressing by the counters or pointers of reading PL and writing PE. These pointers move in the direction of the arrow F. A multiframe corresponds to a quarter of a circle. For FIGS. 3A, 3B, SA, 5B, it is assumed that the write clock is a little faster than the read clock. It is the opposite for Figures 4A, 4B, 6A, 6B.

It is sufficient, when the address of the read pointer is crossed to zero (excitation of the output Co of the member 50) to look at the address bits A6 to A10 that the counter 41 delivers. Three cases are possible for these bits - bits A6 to A10 of the write pointer are all equal to 1. This means that the write pointer is ready to join the read pointer, and that the margin between the two pointers is less than two frames. We then make a jump of a multi-frame back to the writing pointer. This amounts to forcing at value 1 the bit of rank A9 of the write address. This forcing is carried out by the connection illustrated at 61 in FIG. 1.

FIGS. 3A and 3B illustrate the principle: FIG. 3A shows that the pointer PE for writing is ready to join the pointer PL for reading, and is located within two frames of the latter. In this condition, the writing pointer is made to jump backwards by a multi-frame.

this results in a block of deleted BDS data (reinforced quadrant).

- In another configuration, the bits A6 to A10 are all equal to 0. This means that the write pointer, which goes slower than the read pointer, is ready to return to the same level as this one (Figure 4A ). In this case, we make a jump of a multi-frame forward to the writing pointer (figure 4B), this coming back to force are bit
A9 to 1. this results in a block of repeated data BDR (quadrant in strong line).

- In the other configurations, no action is performed on the write pointer.

Of course, the margin is determined so that, given the relative mean drift of the two pointers, it is not possible for them to meet within their operating cycles, when they were more set aside as the margin of two frames at the start of such an operating cycle.

In the above, the modification related to the writing pointer. An often preferable variant is to make the modification on the read pointer itself.

To do this, the read pointer of a multi-frame is simply jumped when it is in relation to the write pointer in one of the configurations illustrated in FIGS. 5A and 6A. The jump appears in Figures 5B and 6B.

In the case of a block of repeated data, the results are not quite the same depending on whether one intervenes on the write pointer or the read pointer. In the first case (FIG. 4B), the reading will not provide the immediately preceding block, but an earlier block, over the interval of time which will have been skipped. We assume that the sequence transmitted is abcdef, and that the jump is made between e and f.

According to FIG. 4B, b is repeated after e, to then read f, etc.

In other cases (Figure 6B), the written sequence abc is read as a, b, b, c, which is preferable.

The invention is capable of various applications which, essentially, relate to the sliding of clocks produced by a satellite. In terms of operating clocks, two cases should be considered. To analyze them, we will consider that there exists on the ground a West station, which transmits or receives with respect to the satellite, as well as an East station, also capable of transmission-reception with respect to the satellite. These two stations cooperate with automatic exchanges.

1 /. - It is assumed that the OE transmission in the West takes place at the rate of the HREF reference clock.

East side, the clock clock (HG) received (ER) serves as operating clock, and controls the EE emission in the East direction
Where is. We then receive a doubly jittered clock (HG2) on the west side (OR).

All you need is a buffer memory OM written at the rate of HG2 and read at that of HREF. In principle, this arrangement avoids any jump.

2 /. - Each side has its reference clock for transmission, these clocks being assumed to be accurate to within 10 11 (for example). In the west, the reception OR is done according to the clock of East giguée HEG. The OM memory, registered to this HEG clock, is read at the rate of the reference clock in
West HOR.

Conversely, the data received in East (ER), at the rate of the clock clock in the west HOG, are written into the buffer memory EM, from which they are read at the rate of the clock clock reference HER. The existence of jumps depends on the relative stability of the HER and HOR reference clocks.

Furthermore, it will be noted that the device of the invention can be used for digital transmissions at the same rate, but whose periodic structure would not be that for which it was intended. It would work correctly except the appearance of discontinuities in said periodic structure at the time of the jumps (which are much less numerous than according to the prior art).

Claims (12)

Claims. 1. Device forming a digital transmission relay, of the type comprising - input circuits (1), suitable for receiving digital information, - output circuits (2), suitable for transmitting digital information, and - means for processing (3, 4, 5) able to store the information received by the input circuits, at the rate of the reception clock, as well as to restore them to the output circuits for transmission, at the rate of a local clock , characterized in that the processing means comprise - a large capacity addressable buffer memory (33), - a first cyclic counter (41), forming a writing pointer for addressing the memory (33) at the rate of the reception clock, - a second cyclic counter (51), of the same capacity as the first, forming a read pointer for addressing the memory (33) at the rate of the read clock, and - means (6) which, when one (51) of the counters goes into a predetermined state, determine the ec art between the scores of the two cyclic counters, and cause one (41) of the counters to jump by a predetermined number of addresses when said difference is less than a predetermined margin, the direction of the jump being linked to the direction of the difference . 2. Device according to claim 1, characterized in that the digital information is of the type with built-in clock. 3. Device according to one of claims 1 and 2, characterized in that the detection of the transition to the predetermined state is done on the second counter (51). 4. Device according to one of the preceding claims, characterized in that the jump concerns the second counter (51). 5. Device according to one of claims 1 to 3, characterized in that the jump concerns the first counter (41). 6. Device according to one of the preceding claims, characterized in that the amplitude of the jump corresponds to a time interval of two milliseconds, or a multiple of this value. 7. Device according to one of the preceding claims, in which the digital transmission is multiplexed in time over a predetermined global period, characterized in that the amplitude of the jump is equal to this global period, or multiple thereof. 8. Device according to one of the preceding claims, characterized in that, initially, or at a resumption of transmission, the two counters are brought into positions offset from one another by approximately half their capacity ( 40). 9. Device according to one of the preceding claims, characterized in that the buffer memory (33) is organized in words, and in that the information both received (21,31) and transmitted (81) are organized in words of same size, before writing and sending, respectively. 10. Device according to claim 9, characterized in that the words are eight bits. 11. Device according to one of the preceding claims, characterized in that the difference between the size of the counters and twice the margin is chosen to be greater than twice the peak-to-peak jitter that the transmission of information can undergo. 12. Device according to one of the preceding claims, in which the transmission involves a geostationary satellite, characterized in that the initial positioning of the two counters takes account of the situation of the satellite with regard to its circadian clock drift.