FR2582423A1 - Buffer memory to be interposed between two synchronous systems with different speeds - Google Patents

Abstract

Buffer memory to be interposed between a sending system EM supplying sequential, n-bit data in parallel to a fast system and a receiver system RE receiving this data at a slower rate, characterised in that it includes N separate blocks of memory MA, MB, MC, MD in each of which the write/read operations for each group of n simultaneous data items are shifted by one clock cycle with respect to the neighbouring block, each block taking account only of one group out of N of these data items, and thus having available, for its own cycle of operations, a time equal to N clock HAD cycles, this clock cycle being synchronised with that of the sender EM in a write phase and with that of the receiver RE in a read phase. Application: image memory for a digital camera.

Description

Buffer memory to interpose between two synchronous systems at different speeds.

 The invention concerns the buffer memories to be interposed between a sending system, supplying sequential data at a rapid rate, and a receiving system which can receive this data only at a slower rate. In particular, the transmitting system may include a sensor such as a digital television camera or an analog camera associated with a digitizer, and provide sequential information at a high speed generally incompatible with that of the receiving system which will use this information and which is most often a computer or calculator. In this case, the memory in question is more especially an image memory intended to memorize at their rate the information coming from the sensor to then transmit it to the computer at its own rhythm.

 Buffers of this type are already known, in particular image memories. The main difficulty they have to overcome is related to the large amount of information to memorize, generally several hundreds of thousands of bytes, associated with the fact that this information arrives at a high speed, from 4 to 10 million bytes. /second. However, the integrated circuit memory elements available on the market are either of high access speed but of low capacity, or of fairly large capacity but of low access speed and incompatible with the arrival speed indicated above. .

Consequently, all the current image memory systems which must ensure compatibility between capacity and speed lead to numerous and expensive memory elements, as well as to control electronics which are also complex and expensive.

 The object of the invention is to eliminate the above drawbacks, that is to say to satisfy the conditions of capacity and speed imposed, but with simple electronics and slow memory circuits, few and inexpensive.

 For this, the buffer memory according to the invention, to be interposed between the transmitting system supplying sequential n-bit data in parallel at a rapid rate and a receiving system receiving this data at a slower rate, is characterized in that it comprises N separate memory blocks in each of which the write / read operations of each group of n simultaneous data are shifted by one clock cycle with respect to the neighboring block, each block taking into account only one group on N and having for its own operating cycle a time equal to N clock cycles, this clock cycle being synchronized with that of the transmitter for writing, and with that of the receiver for reading.

 To benefit from the maximum simplification, the number N is preferably chosen equal to a power of 2.

 Thus, the invention makes it possible to use memories N times slower than usual. Conversely, knowing the cycle time of a block of memory used, and the period of arrival of the data from the transmitter, it suffices to choose for N the power of two at least equal to the quotient of these two times.

 In particular, the memory according to the invention can be used as image memory between a television camera provided with a digitizer with line synchronization and image synchronization, and a computer.

 Each memory block can advantageously be constituted by a dynamic random access memory (RAM) with time multiplexing of the addresses and local control logic.

 In addition to these memory blocks, the device according to the invention comprises an address generator on the abscissa and orderly commanded by a control circuit of the address generator receiving the synchronizations of the digitizer and the computer, controlling a logic processing circuit memory block commands, which in turn controls the memory blocks.

Other features of the invention will appear in the following description of an embodiment taken as an example and shown in the accompanying drawing in which
Figure 1 is the general diagram of the system;
FIG. 2 is the diagram of one of the memory blocks;
FIG. 3 the diagram of the control circuit of the memory blocks;
FIG. 4 the diagram of the address generator;
FIG. 5 the diagram of the control circuit of the address generator;
Figure 6 a diagram illustrating the variable windowing;
Figures 7 and 8 are timing diagrams of the main signals used.

 In the example chosen, the system constitutes an image memory interposed, as can be seen in FIG. 1, between an EH transmitter constituted by a video camera associated with a digitizer, and a RE receiver constituted by a computer.

The field of the camera, shown diagrammatically in FIG. 6, comprises at most 512 x 512 pels each coded on n = 4 bits (16 shades), but it is only proposed to store the content of a window of constant extent of 256 x 256 pels but of variable position in the field defined by the xo and yo values which may vary each between
O and 255.

 Memorizing an image corresponding to such a window therefore requires a total memory capacity of 256 x 256 x 4 bits, or 64 K pels of 4 bits (K = 1024).

According to the invention, such a memory is divided into a certain number N of memory blocks, here 4 memory blocks referenced respectively MA, MB, Nc, MD. This is of course an example and there is no need for the number N of memory blocks to be equal to the number n of bits per pel. Each memory block such as
M therefore comprises 16 K x 4 bits.

 Inside the window shown in FIG. 6, each image point as P is defined by two numbers, its abscissa ADX (or column number, coded on 8 bits (ADXO ... ADX7), and its ordinate ADY (or line number) also coded on 8 bits (ADYO ...

ADY7).

In each memory block, to code the 16 K addresses, 14 inputs are required. We use for this an ADY address coded on 8 bits, arriving by bus ..... .7 visible in Figure 1, and an address
ADX coded on 6 bits and arriving via the ADX2 bus ... 7. The least significant bits ADXO and ADX1 will be used to select a block among the four.

 All the memory blocks are connected on an I / O bus carrying four data in parallel, DO ... D3. This bus ES is connected to the input word DEO ... DE3 by means of a quad flip-flop 10 with 3-state output synchronized by the clock HPX (coming from the emitter EM) and controlled by the logic variable E (active in write mode). Similarly, the ES bus is connected to the output word DS0 ... DS3 by means of a quad flip-flop 11 of type "D" synchronized by a clock signal lIAD and the outputs of which are forced to zero by the signal FD.

All blocks also receive IIPX complemented clock input also from the transmitter. On the other hand, each block also receives its own logic control signals WG, CAS, RAS and F, and are therefore each assigned the index
A, B, C or D corresponding; these signals are produced by the control circuit of the memory blocks CBM.

 FIG. 2 shows more particularly the detail of constitution of a memory block MA, all the others, MB, MC and MD being identical, apart from the index of the indexed variables.

This memory block includes
- a dynamic RAM memory of 16 K x 4 bits;
- a synchronized multiplexer 2 - 1 octuple, MUX1, transferring
depending on the status of the RAS command - i.e. ADX 2 addresses, ...

 ADX 7, ADYO, ADY1 when KAS = 1, i.e. the addresses ADY2, ...

 ADY7 when R S = O.

The synchronization on the rising edge of R # X makes it possible to ensure that the address entries of the RAM are stable during the negative transition of RAS;
- RAM control logic which in turn includes
a 2 - 1 multiplexer, MUX 2, applying to the W input
RAM (write command), i.e. the WG command
when E is active (writing is allowed if WG = O),
either logical state 1 when E = O (writing is not
then not allowed regardless of the WG state) ;;
a multiplexer 2 - 1, MUX 3, applying on input G
(command to activate the output), i.e. the logic state
1 when E is active (the D / Q output is then disconnected
I / O bus output), i.e. the WG command when
E is inactive (the RAM output is connected to the
ES bus when WG = 0);
a NAND gate 12 applying to the CAS input of the RAM
either the CAS command supplemented if the F command is
active, ie logical state 1; this logic allows
put the RAM either in normal operating mode,
either in cooling mode;
. the RAS command is applied to the RAS input of the RAM
Permanently.

 The four logic control signals WG, CAS, RA ## S and F, specific to each of the four memory blocks, are developed as seen above by the control circuit of the CBM memory blocks, the details of which are reported. in FIG. 3. This circuit is important and characteristic of the invention because it is it which carries out the sequencing of the operations of each memory block with a view to the alternating distribution between these various blocks of data arriving at the rapid rate of the transmitter. This distribution takes place according to a cycle which lasts N clock cycles, in this case four clock cycles, successively offset from one another and which are identified by the logic variables A, B, C and D obtained by decoding of the address bits ADXO and ADX1 using a DCR1 decoder.

Considering for the moment - exclusively the operating cycle of the MA block, this cycle, of duration of four clock cycles as we have seen, includes
- cycles A and B which are reserved for addressing the RAM;
- cycle C which is a waiting cycle during which the address is decoded by the RAM;
- cycle D which is the active cycle during which is carried out, either the write operation if E = 1, or the read operation if
E = 0.

For this, the logic commands of the MA block are generated as follows:
RASA is taken directly from line A, which gives the relationship RASA = A.

 Likewise WGA is taken directly from direct output D.

Finally
CASA is generated by a NOR OR 13 logic gate receiving at input A and B, which according to Morgan's theorem is equivalent to achieving the intersection CAS A = A &.

The logic control signals of the other memory blocks MB,
MC and MD are developed identically by a circular permutation.

 In this way, the block MA having started its operating cycle a clock cycle before the block MB, two clock cycles with the block Mc, etc., is available at the end of its operating cycle to initiate a new cycle while the other blocks are occupied.

 The timing diagram of FIG. 7 explains the temporal evolution of the operating cycles of the blocks M and MB.

 The circuit CBM also comprises, in the upper part of FIG. 3, the logic for developing the window signals FA ... FD which will be explained below.

The various address signals necessary to supply the two address buses indicated above are generated by the address generator GA shown in more detail in FIG. 4. This address generator comprises two synchronous modulo 512 counters
CSX and CSY respectively generating the addresses ADX and ADY, by noting that in addition to the eight binary signals indicated above, ADXO ... ADX7 or ADYO ... ADY7, there is also a ninth additional signal ADX8 or ADY8 corresponding to the most significant bit. Each counter includes, in addition to the nine binary address outputs, nine preload inputs, some of which can be activated by a PAO input and preset by a device shown diagrammatically by switches 14 or 15 in the figure, switches which, depending on their open or closed state, make it possible to binary code values taking account of the xo and yo values indicated above for positioning the window. Each counter further includes a precharge command input and a clock input for counting. The CSX counter developing the column addresses at its precharge input controlled by an SLM # PX signal and its clock input controlled by the HAD signal already mentioned. The CSY counter developing the row addresses at its precharge input controlled by the SYI signal image synchronization and its clock input controlled by the same SMPX signal controlling the precharge of the CSX counter.

 The three signals PAD, HAD and SLMPX controlling the address generator GA are produced by the control circuit of the address generator CGA of FIG. 5 in a different manner according to the phases of operation, writing or reading.

In the writing phase, the memory must be synchronized by the camera. In this case the SLMPX signal comes (through the multiplexer
MUX4 of FIG. 5) of the synchronization of lines SYL coming from the video digitization card EM, the signal HAD is a copy of the clock signal HPX and the address preload signal PAD acts so as to fix the preload value at a value 512 - xo for CSX and 512 - yo for CSY, these xo and yo values being programmable. This takes the form of the fact that the most significant input bit (256) of each counter CSX and CSY is always at 1. The corresponding value is therefore preloaded in the counter CSX by the line synchronization signal SYL and in the counter CSY by the image synchronization signal SYI. The content of CSX is incremented by
HAD, that is to say in the present case by HPX from the end SYL. After xo clock pulse, the content of the counter CSX in modulo 512 reaches the value O and consequently the address ADX 8 switches from the value 1 to the value 0 and remains in this state as long as the column values correspond to the column values from the window.

The counter CSY operates in the same way, its precharging being effected by the image synchronization signal SYI at the value 512 - yo and its content being incremented as has been seen by the line synchronization SYL. The ADY8 address therefore switches from 1 to O when the line numbers correspond to the line numbers in the window. We therefore see that the point explored is in the window if and only if neither of the addresses ADX8 and
ADY8 are in state 1. This is how, in FIG. 3, the window signal> FA is produced by a NOR gate 15 which receives as input
ADX8 and ADY8. The other window signals FB, FC and FD are produced by a parallel serial register 17 actuated by the rising edge of the clock HPX.

 In the reading phase, the operation is analogous to the previous one, but in this case the PAO signal does not activate the previous xo and yo values but lets act fixed values corresponding to the windowing desired for the computer. The signal BAD is no longer synchronized on the clock EPX but on the computer and the signal SLMPX is no longer connected by MUX4 on line synchronization but on a pseudosynchronization of line leaving the decoder DCR2 of FIG. 5.

The command of the address generator CGA of FIG. 5 comprises for this an AND gate 18 which receives as input the four addresses ADXO, ADX1, ADX2 and ADX3 and generates a signal CO which indicates that the number ADX in modulo 16 is equal to 15. Finally the DCR2 decoder receives as input the previous CO signal, the ADX4 signal in an inverting input and the ADX8 signal and generates the line pseudosynchronization, active in state O when ADX8 = 1, ADXI = O and
CO = 1.

 The circuit of FIG. 5 also includes a read-only memory ROH which receives as input the nine addresses ADXO to ADX8 and which transmits a signal TRANS, which is equal to 1 when the arithmetic value ADX is between 4 and 259, this signal TRANS indicating that the data from the memory is to be read.

 The control circuit of the address generator CGA is also responsible for managing the exchanges with the computer in order to ensure both the synchronization of the exchanges and the adaptation of the image format.

 The synchronization of the exchanges is done according to the usual call-response protocol. When the exchange is programmed, the calculator emits a READY signal. When the data from the memory is good to read, which is indicated by the variable TRANS as we have just seen, the synchronization circuit sends a cycle request signal CYCREQ, the computer responds with the signal BUSY which returns to zero the CYCREQ signal and whose return to zero signifies the end of the exchange cycle. During the entire duration of the elementary exchange cycle, the operation of the memory must remain frozen.

 This synchronization circuit is organized around a flip-flop of the type D '' referenced BD1 in FIG. 5. When READY T and TRANS are both activated, the input D of BD1 is activated by the AND gate 19. The first clock pulse HAD arriving at the rising edge control input changes the output Q of the flip-flop to state 1.

When the computer issues the BUSY response, the logic complement
BUSY developed by the inverter circuit 20 and applied to the asynchronous input CL returns Q to zero, therefore also CYCREQ.

 The HAD clock circuit is organized around a flip-flop of type "D" reference BD2. In the absence of the signals CYCREQ and BUSY, detected by the gate NOR OR 21, the output Q of this rocker is always in state 1 so that 1AO is always equal to HPX due to the inversion of the gate NO AND 22, an additional inversion by 23 restoring the RAI signal). On the contrary when CYCREQ or BUSY are active, gate 21 acts on the asynchronous input CL which causes the resetting of Q and consequently the resetting of RAI). However, the OAO ## applied to the priority asynchronous input PR, which gives priority to setting state 1 of Q, ensures that any clock cycle started will normally be ended.

 Thus, depending on whether the exchange with the computer is in progress or not, the MAD clock has its own cycle synchronized with the exchange and comprising missing cycles with respect to the HPX clock, or else is a copy of the HPX clock. The timing diagram of FIG. 8 specifies the temporal evolution of these signals.

 Adaptation to the image format requires that two functions be carried out: the modification of the preloading of the address counters, and the modification of the synchronization of the lines.

For the first function, the READY signal from the computer is firstly synchronized by Syl thanks to a flip-flop of type "D" BD3 whose control input is attacked by SYI via an inverting gate 24. On thus ensures that the change in the operating mode of the memory, to pass from writing to reading or vice versa, takes place at the start of an image cycle. The signal
READY T from the flip-flop BD3 is itself synchronized by SYL # thanks to the flip-flop of type "D" referenced BD4 and whose complemented output Q controls the multiplexer MUX4 indicated above. This ensures that the preloads are properly carried out before changing the multiplexer to switch from line synchronization
SYL to pseudo-synchronization of line coming from DCR2.Le signal
READY T applied to the asynchronous CL input of BD4 ensures the early return to the write mode as soon as the exchange is complete.

 The second function, that is to say the modification of the line synchronization, as already explained above, is obtained by the multiplexer 2 - 1, MUX4 controlled by the Q output of BD4. Apart from exchanges with the computer, the SLMPX signal controlling the generation of addresses is identical to SYL from the camera, while during exchanges with the computer, this SLMPX signal is produced by the DCR2 decoder generating pseudosynchronization of the lines.

 The invention thus makes it possible to meet the capacity and speed requirements imposed while using only common components, few in number and inexpensive.

 Naturally, apart from the example described, the invention applies to any buffer memory used in two synchronous systems, and the capacity can easily be modified. For example, the format of the words can be increased at will by placing in parallel in each block several RAM circuits, and the capacity can be increased both in rows and in columns by adding RAM memory circuits suitably selected by the bits of additional addresses obviously necessary.

Claims (6)

 1. Buffer memory to be interposed between a transmitting system (EH) providing sequential n-bit data in parallel at a rapid rate and a receiving system (RE) receiving this data at a slower rate,  characterized by the fact that it comprises N separate memory blocks (MA, MB, Mc, MD) in each of which the write / read operations of each group of n simultaneous data are offset by one clock cycle with respect to to the neighboring block, each block taking into account only one group on N of this data and thus having for its own cycle of operations a time equal to N clock cycles (HAD), this clock cycle being synchronized with that of the transmitter (EH) in a write phase and with that of the receiver in (RE) in a read phase.  2. Buffer memory according to claim 1, more particularly intended to serve as image memory between a digitized video camera providing the fast clock signal (HPX), the image synchronizations (SYI) and of line (SYL) and the n parallel data (DEO ... DE3), and a computer supplying and receiving the usual logic exchange protocol signals (READY, BUSY, CYCREQ) and also receiving the n bits in parallel (DSO ... DS3),  characterized by the fact that it comprises an address generator (GA) with two components (columns and rows) controlled by an address generator control circuit (CGA) receiving the synchronization and exchange signals from the camera and from the computer and controlling a logic circuit (CBM) for controlling the memory blocks, which in turn controls the memory blocks (MA ... ND)  3. Buffer memory according to claim 2, characterized in that each memory block comprises a dynamic random access memory (RAM) with time multiplexing of the addresses (MUX1) and local control logic (MUx2, MUX3, 12).  4. Buffer memory according to one of claims 2 and 3, characterized in that the memory block control circuit (CBM) uses the least significant bits (ADXO, ADX1) of the column addresses to work out via a decoder (DCR1) N shifted logic signals (A, B, C, D) and their complements (A, B, C, D) in order to develop by a decoding matrix the logic control signals of each memory block (RA # S, CAS, WC).  5. Memory according to one of claims 2 to 4, arranged to select a variable position window in the camera field defined by a maximum number (for example 512) of pels per row and column greater than the corresponding number of pels ( for example 256) of the window which corresponds to the capacity of the memory, characterized in that the address generator (GA) comprises two counters synchronous to the modulo of this maximum number, with adjustable preload values, the bit or bits most significant additional signals (ADX8, ADY8) being received at the inputs of a NOR gate (16, FIG. 3) to generate a window signal (FA) from one of the memory blocks (MA), and the signals from corresponding window of the other blocks (FB, Fc, FD) via a parallel serial register (17).  6. Buffer memory according to one of claims 2 to 5, characterized in that the control circuit of the address generator (CGA) processes the synchronization signals of the address generator (PAT, SLMPX, HAD) and of exchange with 11 computers (CYCREQ, BUSY, READY) by simple flip-flops of type "D" (BD1, BD2, BD3 and BD4) combined with logic (18, 19, 21, 22) and reversing (20, 23, 24) gates, a decoder (DCR2), a simple multiplexer (MUX4) and a read only memory (ROM).