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FR2569289B1 - NEW STRUCTURE OF MEMORIES ADDRESSABLE BY A CONTINUOUSLY MOVING WINDOW WITH OVERLAP - Google Patents

NEW STRUCTURE OF MEMORIES ADDRESSABLE BY A CONTINUOUSLY MOVING WINDOW WITH OVERLAP

Info

Publication number
FR2569289B1
FR2569289B1 FR8412946A FR8412946A FR2569289B1 FR 2569289 B1 FR2569289 B1 FR 2569289B1 FR 8412946 A FR8412946 A FR 8412946A FR 8412946 A FR8412946 A FR 8412946A FR 2569289 B1 FR2569289 B1 FR 2569289B1
Authority
FR
France
Prior art keywords
overlap
new structure
continuously moving
moving window
addressable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8412946A
Other languages
French (fr)
Other versions
FR2569289A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LEHMANN JEAN PHILIPPE
Original Assignee
LEHMANN JEAN PHILIPPE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LEHMANN JEAN PHILIPPE filed Critical LEHMANN JEAN PHILIPPE
Priority to FR8412946A priority Critical patent/FR2569289B1/en
Publication of FR2569289A1 publication Critical patent/FR2569289A1/en
Application granted granted Critical
Publication of FR2569289B1 publication Critical patent/FR2569289B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
FR8412946A 1984-08-16 1984-08-16 NEW STRUCTURE OF MEMORIES ADDRESSABLE BY A CONTINUOUSLY MOVING WINDOW WITH OVERLAP Expired FR2569289B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8412946A FR2569289B1 (en) 1984-08-16 1984-08-16 NEW STRUCTURE OF MEMORIES ADDRESSABLE BY A CONTINUOUSLY MOVING WINDOW WITH OVERLAP

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8412946A FR2569289B1 (en) 1984-08-16 1984-08-16 NEW STRUCTURE OF MEMORIES ADDRESSABLE BY A CONTINUOUSLY MOVING WINDOW WITH OVERLAP

Publications (2)

Publication Number Publication Date
FR2569289A1 FR2569289A1 (en) 1986-02-21
FR2569289B1 true FR2569289B1 (en) 1987-04-24

Family

ID=9307096

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8412946A Expired FR2569289B1 (en) 1984-08-16 1984-08-16 NEW STRUCTURE OF MEMORIES ADDRESSABLE BY A CONTINUOUSLY MOVING WINDOW WITH OVERLAP

Country Status (1)

Country Link
FR (1) FR2569289B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69324694T2 (en) * 1993-12-15 1999-10-07 Stmicroelectronics S.R.L., Agrate Brianza Double-row address decoding and selection circuit for an electrically erasable and programmable non-volatile memory arrangement with redundancy, in particular for flash EEPROM arrangements

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5822833B2 (en) * 1978-11-20 1983-05-11 株式会社日立製作所 Memory addressing method

Also Published As

Publication number Publication date
FR2569289A1 (en) 1986-02-21

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Legal Events

Date Code Title Description
ST Notification of lapse