FR2512307A1 - METHOD FOR TRANSMITTING ORDER DATA - Google Patents

Abstract

THE METHOD ACCORDING TO THE INVENTION IS INTENDED FOR THE EXCHANGE OF CONTROL DATA BETWEEN A ZMP CENTRAL MICROPROCESSOR AND DECENTRALIZED MICROPROCESSORS. TO THIS END, BSD INPUT CIRCUITS FOR SERIAL DATA TRANSMISSION ARE INTERCALED BETWEEN THE CENTRAL MICROPROCESSOR AND THE DECENTRALIZED MICROPROCESSORS.

Description

Method for transmitting control data The present invention

relates to a method of

  transmission of control data between a central unit

  control unit and peripheral functional units

  especially for the control of a tele-

digital communications.

  Digital transmission systems function-

  preferably by an imitation modulation method

  coded impulses (? Ic), by which analog information

  symbols or symbols are converted into pulse trains

  digital sions for their transmission With regard to the transmission of command data between

  a central control unit and functional units-

  peripherals, a common line network (omnibus line network) with a parallel transmission or a star network with a serial transmission is used, or a mixed form of these two networks In this case, a cyclic transmission of commands to each peripheral functional unit, with then its interrogation for the reception of information are possible or

  commands are given to the peripheral functional units

  individual risks to prepare them for receiving information

  formations Here also mixed forms are known.

  The object of the invention is therefore to propose a pro-

  assigned digital transmission of control data

  be a central control unit and functional units

  peripheral, simple, str and largely independent of technological progress The way in which this result is

obtained will appear later.

  Other features and benefits of ivin-

  vention will appear during the following description;

  follow an exemplary embodiment and with reference to the accompanying drawings in which: Figure 1 is a simplified diagram of a modular frame, and Figure 2 is a simplified diagram of the unit

control center.

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12307

  Schmitt's tilting part in the attack stage

  TZ is located in front of the data entry and, therefore,

  sound of the inversion produced by the TZ attack stage,

  an inverter stage is connected behind it.

  On the peripheral level, the receiver of a BG module consists of a Schmitt color switch circuit

  and the transmitter in a line driver circuit

  tor and the receptor are made in the form of a

  unit, called transceiver, whose direction of trans-

  mission is established by an order In position of re-

  pos, no data is transmitted and the transmitter and

receiver are blocked.

  The clock terminals of the N decentralized microprocessors DMP, for the clock signals And :? WR, are also grouped on common lines and are

  connected by clock lines RD, WR to the power circuit

  BSD input / output assigned to BGR modular frame.

  The clock line RD also leads to the entrance to the circuit.

  baked input / output BSD as well as the bistable tipping stage FF and a door connected behind it Thus, the input / output circuit BSD of each modular frame

  BGR, on the side of the DMP decentralized microprocessor of mo-

  dules BG 1 B Gn is directly controlled by signals.

  The command lines I Nr S, INTV are used for input and synchronization of data transfers

  switching and safety as well as differentiation

  tion of the input and output For this purpose, the micro-

  decentralized DMP processor of a BG module, preferably

  of the first BG 1 module is designed as a distri-

  stopper for a modular BGR frame The INTS command line connects the EAMP input-output microprocessor

  central control with the INT interrupt input The diff-

  data input or output referencing is identified by a short or long pulse at the INT interrupt input The addressing of a modular BGR frame by the EAMP input / output microprocessor is ensured by the INTS general that the BG 2 B Gn modules of a

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  frame are controlled by the decentralized microprocessor

  assigned a special module, preferably module BG 1.

  The INTV signals transmitted in series in a fixed time frame by the EAMP input / output microprocessor are received by the decentralized microprocessor DMP preferably from the first module BG 1 of a modular frame BGR and, weighted in duration are divided into star at the INT interrupt inputs of the corresponding modules

BG 2 * B Gn.

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