FR2509887A1 - Shared memory for microprocessor storage and matrix display - uses two position switching to allow data to be transferred to or from memory otherwise used to drive matrix display - Google Patents

Abstract

The appts. is coupled to the processor of an information system through a common bus and comprises a display (13,17), a random access memory (RAM) (9); two position switches (8,10); and a controller (16). If a memory address (19) is placed on the bus, the switches (8,10) connect the memory to the bus and control reading or writing from or to the memory (9). Otherwise the switches (8,10) are positioned to connect the memory (9) to the display (13,17). The controller (16) has an address decoder (6) coupled to the bus to generate a logic signal (FM) when the correct address is present. This signal (FM) is input to a logic gate along with the state of the read/write pin on the processor, the gate output controlling the operation on memory.

Description

MEMORY AND DISPLAY DEVICE
The present invention relates to storage and display devices for computer systems, in particular microprocessor systems.

 In such a system, the information to be displayed is generally too numerous for it to be possible to use a control wire for each information to be displayed (lighting of an indicator lamp for example). In general, display devices reproducing complex information, such as alpha-numeric characters, proceed by switching on points or segments supplied by two electrical networks constituting a matrix. This matrix structure makes it possible to control all the elements of the display with a number of wires much lower than the number of elements to be controlled. For example, we can control eight digital displays with seven segments with only 15 wires instead of 56. This matrix structure does not allow to switch on all elements simultaneously, it is necessary to multiplex the control information. In the previous example, only one of the eight digits can be lit at any given time. By performing rapid multiplexing, the displays all seem to operate simultaneously, due to the persistence of sensations in the human eye. The disadvantage of multiplexing is the complexity of implementation.

 For example, in the case of a system where the information to be displayed is supplied by a microprocessor, the small number of outputs available, even if there are output expanders, requires the multiplexing of the information but otherwise this is costly in computation time and in program memory space. To obtain a permanent display, at least apparently, the microprocessor must devote a large part of its time to read in memory and multiplex the data to display.

 On the other hand, in microprocessor-based computer systems, the capacity of the RAM memory incorporated therein is often insufficient, an external memory is connected to it by buses. Reading data by direct access to these memories can be carried out using a specialized integrated circuit for managing this direct access. This solution allows rapid transfers between a memory and a peripheral because the data does not pass through the microprocessor, but the latter is inhibited during these transfers. If such a circuit were used to read from memory the data to be displayed, the microprocessor would be inhibited almost permanently, which would be no better than making it read and multiplex this data.

 The device according to the invention overcomes these drawbacks, by limiting the task of the processor to a single transmission of each data item to be displayed to an external RAM memory, which is read directly to perform the display. On the other hand this memory is used by the processor as a common external memory, to write or read any data therein.

According to the invention, a storage and display device, connected to the processor of a computer system via the unmarked buses of this system, is - mainly characterized in that it comprises display means; RAM memory; two position switches; and control means for,
- if one of the addresses assigned to the memory is present on the buses, switch the switches so as to connect the inputs and outputs of the memory to the system buses, and order a write or read in the memory according to the command sent to the buses by the processor;
- if not, switch the switches so as to connect the inputs and outputs of the memory to the display means and order a reading in the memory.

The invention will be better understood and other characteristics will appear with the aid of the description below and the figures relating thereto:
- Figure 1 shows the block diagram of an embodiment of the device according to the invention;
- Figure 2 shows the same block diagram detailing an embodiment of the control means;
- Figure 3 shows the block diagram of a display used in the embodiment of Figure 1.

 In FIG. 1, a multiple input 1 is connected to the address bus of a computer system, for example a microprocessor. A multiple input / output 3 is connected to the system data bus.

The display is produced by a display 13 called a matrix display. The ignition of one of its elements is obtained by simultaneously supplying two conductors, one constituting a line, the other constituting a column of a matrix. Means 17 for controlling the display, carry out the multiplexing.

 In this example, the display 13 consists of eight digital displays, with seven segments, which make it possible to display eight digits. FIG. 3 represents the diagram of the display 13. Each digit is represented by a set 20 of seven segments a, b, c, d, e, f, g. Each segment can be illuminated by a light-emitting diode (LED). The cathodes of all the LEDs in the assembly 20 are connected to a common conductor constituting one of the columns of the control matrix, and supplied by an input terminal 21. Each digit of the display is made up identically to the assembly 20 and corresponds to a column of the matrix. The anode of each LED of a set 20 is connected to one of the seven conductors constituting the lines of the matrix. For example all the segments a of the eight digits are connected to a first line, the segments b to a second line, etc ...

 Multiplexing is carried out by successively supplying the data on the rows of the matrix, by the multiple input 18, and by successively connecting, to the reference potential, the columns of the matrix, by a multiple input 19, consisting of the input terminals 21 of all sets 20.

 In FIG. 1, a RAM memory, 9, stores data which is either to be displayed or useful for other tasks of the microprocessor. The data entering or leaving memory 9 are routed by a switch 10, either to multiple input-output 3 or to inputs of the means 17 controlling the display 13. The addresses supplied to memory 9 are routed by a switch 8 and come either from the multiple input 1, or from the outputs of the control means 17.

 An input terminal 2, connected for example to the system command bus, receives a logic signal when the system writes to one of its memories, in particular to memory 9. This signal is applied to control means 16 which also receive, by multiple input 1, the addresses generated by the system on its address bus. When the microprocessor uses the device according to the invention as a memory it sends an address, specific to this device and which the control means 16 are capable of recognizing. They then switch points 8 and 10 so that memory 9 is connected to the data bus and the address bus. Depending on the signal received by the input terminal 2, the means 16 control a reading or a writing in the memory 9.

The data to be displayed is registered at fixed addresses, reserved for this use, using the same instructions as for an ordinary storage.

 When the control means 16 do not detect the presence of the address of the device on the address bus, they control the switches 8 and 10, and the memory 9, so that it is read at one of the addresses where the data are to display. These are transmitted to the means 17 controlling the matrix display 13. To multiplex the display, the means 17 supply to the memory 9, via the switch 8, the series of addresses of the data to be displayed. Reading of the data to be displayed is only interrupted by the reading and writing operations controlled by the microprocessor. Generally these operations only take place a small fraction of the time, which makes it possible to have a permanent display in appearance.

 FIG. 2 represents the block diagram of the same exemplary embodiment but with more details, in particular as regards the control means 16, 17 and the buses.

 In this example, the data bus is bi-directional. The memory 9, 256 bytes with random access, receives eight address bits supplied by the switch 8 comprising eight circuits with two positions. It receives or supplies eight bits of data through the switch 10 comprising eight bi-directional and two-position circuits. The memory 9 being used permanently, its selection input (CS) is continuously supplied.

 The multiple input 1 is connected to the sixteen lines of the address bus, the eight most significant bits supply an address decoder 6 which generates a logic signal FM = I when the address assigned to the device is present on the address bus , that is to say when this device is used in its memory function.

 Input terminal 2, connected to the system command bus, receives an E / L = 1 signal when the system writes to one of the memories connected to the buses. The E / L and FM logic signals are supplied respectively to the two inputs of an AND logic gate, 7, which generates a W / R logic signal. This signal is applied to an input of memory 9 and controls the write function if it is at level 1, and the read function if it is at level 0.

 The FM signal is applied to an input of switch 10 and to an input of switch 8 to control their position.

 When FM = 1, the switch 10 connects, bi-directionally, the eight data inputs / outputs of the memory 9 with multiple input / output 3, connected to the eight lines of the data bus of the system; on the other hand, the switch 8 connects the eight entries of the addresses of the memory 9, to the eight least significant entries of the multiple entry 1. The data are read or written at this address in the memory 9, depending on whether the E / L signal or is applied to input terminal 2. Synchronization is ensured by a clock signal not shown.

 When the microprocessor does not read or write to memory 9, the logic signal FM is equal to 0, in this example.

The switch 10 connects the data inputs and outputs of the memory 9 to an encoder 12, called the line encoder. In this example, only four out of eight bits are used. The encoder 12 is specific to the type of displays used. In this case, it supplies displays with seven segments, so it has seven outputs. The bits present on these outputs make it possible to reconstitute by seven display segments, the decimal value of the binary word of four bits present at the input. Via an interface 11, called the line interface, these outputs excite the lines of the matrix of conductors supplying the display 13.

 The conductors of the columns are excited one by one, by an interface 14, called column interface, the inputs of which are connected to a decoder 15, called column decoder. A counter 5 provides it with a three-bit binary word and the decoder feeds the corresponding column.

In this example, there are eight columns, each controlling the seven segments of a number. Only one of the eight digits is fed at any time. A clock signal is applied to an input terminal 4 and increments the counter 5 at a sufficiently high frequency, 500 Hz for example, so that the successive lighting of the different digits seems simultaneous and permanent.

 The column decoder 15 receives the FM signal on an input, called inhibition input. When the device is used as memory by the microprocessor, the inputs of the line decoder, 12, remain at a fixed level, 0 for example. To prevent this from causing the display of an undesirable digit, for example 0, the FM signal is used to inhibit any display, by inhibiting the column decoder 15.

 The binary counter 5 supplies the same three-bit binary word to the column decoder 15 and to the inputs of the addresses of the memory 9, these being connected to the counter 5 via the switch 8 when this switch receives the FM signal. The five address bits not supplied by the counter 5 have a fixed value, 0 for example. The three bits supplied by the counter 5 are used to address the memory 9 in order to read there the values of the eight digits to be displayed.

 it goes without saying that the eight addresses defined by these five fixed bits, the three variable bits and the eight bits decoded by the decoder 6 are reserved for storing the data to be displayed. These addresses, like the others, are accessible by ordinary instructions of reading or writing in memory. The programming of a system using the device according to the invention is therefore very simplified as regards the output operations for display.

 The device according to the invention is particularly advantageous in cases where the capacity of the RAM memory necessary for the tasks of the microprocessor is low (256 bytes for example), since a single memory then makes it possible to carry out all the tasks. On the other hand, this device is particularly advantageous when the display includes a lot of information, because the task of the microprocessor is all the more lightened.

The invention is not limited to the embodiment described and shown. A variant of the device according to the invention consists, firstly, in using instead of switches 8 and 10 of the three-state logic gates, to isolate the device from the buses when it is not addressed, and, on the other hand, to connect the inputs of the line encoder 12 directly to the inputs-outputs of the data of the memory 9, and to connect the outputs of the binary counter 5 to the inputs of the least significant addresses of the memory 9 through doors with three states signal controlled
FM.

 Another variant consists in using instead of the counter 5 and the column decoder 15, a counter with decoded outputs, directly attacking the column interface 14, and supplying a binary coder to supply binary addresses to the memory 9 via the switch 8.

 it is also within the reach of those skilled in the art to use a different number of bits for the addresses and the data; to use another type of display with a matrix structure or not, or another memory capacity.

 The device can be simplified to store only data to be displayed. The switch 10 then switches only four circuits, in this example where the data are decimal digits.

 Another modification consists in eliminating the line encoder 12.

In this case, the microprocessor supplies data already coded appropriately for the display 13.

 The invention applies in particular to the storage and display of data in microprocessor systems.

Claims (4)

 1. Storage and display device, connected to the processor of a computer system by means of the unmarked buses of this system, characterized in that it includes display means (13 and 17); a RAM memory (9); two position switches (8 and 10); and control means (16) for,  - if one of the addresses assigned to the memory (9) is present on the buses, switch the switches (8 and 10) so as to connect the inputs and outputs of the memory (9) to the system buses, and order a write or a reading in the memory (9) according to the command sent on the buses by the processor,  - otherwise, switch the switches (8 and 10) so as to connect the inputs and outputs of the memory (9) to the display means (13 and 17) and order a reading in the memory (9).  2. Device according to claim 1, characterized in that the control means (16) comprise an address decoder (6) connected to the address bus by a multiple input (1), to generate an FM logic signal when the address assigned to the device is present on this bus; a logic gate (7) with two inputs, one of which receives the FM signal and the other of which receives an input / output signal by an input terminal (2) when the system processor writes to the device, to generate a logic signal W / R = E / L.FM controlling the writing or reading in the memory (9) depending on whether W / R is respectively 1 or O ;; and in that the FM logic signal positions the switches (8 and 10) so that the memory (9) is connected to the system buses when an address assigned to the device is present on the address bus.  3. Device according to any one of claims I or 2, comprising a display (13) composed of elements supplied by two networks of conductors constituting a matrix, and characterized in that the multiplexed control means of this display (13) comprise a binary counter (5) receiving a clock signal on an input terminal (4) to supply a variable binary word to the input of the addresses of the memory (9) via the switch (8) and to the input of a decoder (15) called column decoder, which excites through an interface (14), said column interface, successively each column of the display control matrix (13).  4. Device according to claim 3, characterized in that the means (17) for controlling the display (13) comprise an encoder (12), called line encoder, for converting the data to be displayed according to the code specific to the type of the display (13), and an interface (il), called line interface, for exciting the lines of the matrix of the display (13) according to the coded data supplied by the line coder (12).