FR2501950A1 - Digital chrominance signal generator for SECAM TV - has two programmable memories storing pre-calculated sample words for odd and even steps on reference signal - Google Patents

Abstract

Two programmable pairs of memories contain sample words of a reference signal and which were precalculated on a computer. One memory contains samples for odd steps while the other contains the even steps. These memories receive the same address during two successive sampling periods via two busses and are controlled for the read periods by complementary logic signals from a time base generator. Addressing of the memory cells is processed by an address counter containing three four bit sub counters. These are initialised by a synchronising signal from a clock running at the line frequency. The memory output passes via a unity adder or subtractor controlled from the time base. A digital-analogue is controlled to provide the amplitude required of the waveform.

Description

DIGITAL SIGNAL GENERATOR
CHROMINANCE CODES SECAM.

 The present invention generally relates to a digital generator comprising means for storing the digital samples of a periodic signal, addressing means for reading the samples at the sampling frequency and means for converting the digital samples read. It relates, in particular, to the digital generation of analog video color signals.

 In the state of the art, the reference signals to be inserted in specific lines of the composite video signal are generated either conventionally by a purely analog generator, or by means of a digital generator delivering the three primary color signals, red R, green V and blue B, to an encoder for the SECAM color television system, or to a digital generator that complies with the US NTSC color television system standards.

 The advantage of a digital generator that does not use any analog processing compared to an analog generator is to confer in particular a very good stability of the characteristics of the delivered signals, thanks to the presence of a minimum of adjustment. The only "analog" parameter that can influence the characteristics of the digital processing of the generator is the clock frequency, which is generally controlled by an external synchronization signal that can be extracted from an incident video signal in which the signals must be inserted. generated.

 It turns out, therefore, that, on the one hand, on the one hand, the quantization step - which sets the theoretical level of the quantization noise - and, on the other hand, the digital-analogue conversion means - the quality they depend on. the final level of the quantization noise and that of the distortion noise which may appear due to the non-linearity of the conversion means, the characteristics of the waveform of the signals delivered depend practically on the value of the samples recorded in the memories .

The samples could, of course, be taken at the output of a conventional analog generator. However, this procedure would help to add specific faults to this analog generator, such as those resulting from physical limitations or incorrect settings of analog components
The present invention aims to provide a digital signal generator specific to the color television system
SECAM in which the samples of each signal were proclaimed using computer means.

 For this purpose, a digital generator of the type defined in the entry is characterized in that the periodic signal is a signal to be included in a predetermined interval of one or more lines of the SECAM color television system, consisting of first and second chrominance signals to include cMcuri alternately every other line, in that the memory means comprise first means for storing the samples of the first chrominance signal and second means for storing the samples of the second chrominance signal and in that the logical addressing means comprises means for selectively addressing every other line of the first and second memory means and means for permitting the reading of the samples during the predetermined interval of said one or more lines.

Preferably, the digital generator according to the invention comprises a plurality of storage means which respectively store the samples of different coded reference signals.
SECAM, such as the bar test signal, the frame identification signals or test signals. In the following, it will be noted that the stored samples are not those of a color difference signal DR or DB but are preferably those of a chrominance subcarrier signal modulated by a color difference signal. DR or DB previously pre-emphasized in low-frequency, limited, then filtered low-pass. This modulated subcarrier signal is then subjected to high frequency pre-emphasis filtering and pre-correction sustain filtering. These analog processing, which degrade the signal in the analog generators, in particular because of the temperature instability and various distortions. , are precisely eliminated, according to the present invention, by performing previously with the aid of a computer the calculation of the values of the samples to be stored, in particular by means of digital filters, and then performing the phase shift of the subcarrier, according to SECAM sequences 0-180 -180 or 1800 -0 -0 using digital means.

 Other advantages of the present invention will become more apparent upon reading the following description of a preferred embodiment of the SECAM digital coded reference signal generator according to the invention and the examination of the single figure. corresponding to the block diagram of this generator.

 The digital generator is organized around a storage circuit 1 which may comprise a pair or M pairs of programmable PROM 111 - 121 to 11M - 12M memories. The two pairs 111 - 121 and 11M - 12M are only shown in the figure.

Each pair of memories is assigned to a type of chrominance signal. This may be for example one of the following reference signals: the bar test signal to be inserted into one or more useful lines of the composite video signal, the frame identification signals occupying the lines of the suppression signal and frame synchronization, a test signal to be inserted into specific lines of each frame, such as lines No. 17, 18, 330 and 331 of the SECAM television system with 625 lines, or an embedded modulated chrominance signal by a frequency staircase, for examplec60.4 to 1.6 MHz, for adjusting the bandwidth of a decoder
SECAM.

In the following, reference will be made to the television system in the neck
their SECAM L whose basic characteristics as well as
those of some of the abovementioned reference signals are given, for example, in Report 624 (1974) and Notices A 473-2 (1970) and A 569 (T78) published by the International Advisory Committee on
Radiocommunications (CCIR).

In one line, a SECAM encoded reference signal occupies a predetermined interval IT equal to the sum of the useful image period TU and the interval T occupied by the time subcarrier.
o reference minimum, also called burst, at the end of the rear level of the line suppression signal, ie: IT = TU + T0 = 52 + 4.9 = 6QSs
With respect to the falling front edge of the line synchronization signal OH which defines the beginning of the nominal period T of a
At a line equal to 64 strokes, the interval IT is preceded by a range of 5, 6 fs containing a line synchronization signal having a width of 4.7.

 The two memories 11 and 12 contain the sample words at N = 8 bits of a reference signal which have been precalculated by means of a computer. In conjunction with the requirement for a sampling frequency greater than twice the high cut-off frequency of the spectrum of the signals to be sampled, ie 2 x 6 = 12 MHz for a frequency band of the composite video signal or frequency band of the luminance signal equal to 6 MHz, two practical criteria for the choice of the sampling frequency FE are added.

 The first criterion relates to the access time, here of reading, and the capacity of the memories available on the market. This access time being greater than (t / 12) 10-6s = 80 ns, it is therefore necessary to share the storage circuit assigned to a reference signal in two memories 11 and 12 which are read alternately at a frequency which is half the sampling frequency. The first memory It contains the samples of odd ranks 1, 3, 5, ...

and the second memory 12 contains the samples of even ranks 2, 4, 6, ... The memories li and 12 respectively receive by two buses 13 and 14 the same address for two successive periods of a = hangling, address which denotes a cell of the memory t 1 containing the odd sample and a cell of the memory 12 containing the next even sample. The memories 11 and 12 are read-controlled at the frequency of FE / 2 by two complementary logic signals transmitted on wires 15 and 16 from the time base 2 of the generator.

 The second criterion concerns the slaving of the sampling over an integer multiple of the line frequency equal to FL = 15.625 Hz.

This integer multiple will be taken in the sequence equal to 864, which defines a sampling frequency equal to FE = 864 FL = 13.5 MHz although another frequency can be chosen such that 15.75MHz = 1008 FL plus close to the maximum number (1024) of the cells contained in memories 11 and 12 used according to this embodiment.

 Thus, for a line of the video signal, each memory 11, resp.

12 contains 864/2 = 432 even samples, resp. odd. However, only the samples of the reference signal contained in the determined interval IT = 56, 9 vs. During the interval of 5.61us preceding the interval IT and the guard interval of 64 - (5, 6 + 56, 9) = 1, 5 ps the memories are not read. Only the 384 (13.5 x 56, 9) / 2 cells - ä addresses between 1 and 384 of each of the memories it and 12 are filled by even and odd samples. The read permission of each pair of these memories During the interval IT is controlled by a signal transmitted on a wire 171 to 17M leaving the time base 2. Indeed, the effective presence at each line of this authorization having a duration IT is dependent on the nature of the reference signal. For example, if the memories 11M and 12M are assigned to the frame identification signals, the read permission occurs only for the nine-line IT intervals of the frame deletion and synchronization signal. These are, for an image, the lines Nos. 7 to 15 odd frames of the image and then the lines
Our. 320 to 328 even frames, as shown in FIG. 9 of the aforementioned CCIR Report 624.

 Finally, always about memories, each memory 11, 12 is divided into two sub-memories 11R and 11 bu 12R and 12B 'to 512 cells each. The sharing is due to the alternation of the DR and DB chrominance signals specific to the SECAM system.

It is known that, according to the sequential principle of the frequency modulation of the chrominance signals in the SECAM system, during a useful line, a chrominance signal assigned, for example, to the red primary color R, modulates a subcarrier which is clean, whose rest frequency is f0R = 4.406 MHz. On the next line, the other chrominance signal, assigned to the blue primary color B, modulates another subcarrier which is clean, whose resting frequency is 0B = 4,250 MHz. The alternation of the two chrominance signals is repeated line to line of a con
t unue and the cycle continues without abnormality also during the entire duration of the frame deletion lines.

According to the invention, the first sub-memories 11 and 12
R contain in their cells having the addresses 1 to 384 the odd and even samples of the corresponding reference signal, assigned to the red color. The second sub-memories 11 R and 1 contain in their cells having the addresses i- + 512 = 513A 384 and 512 = 896 the odd and even samples of the corresponding reference signal assigned to b blue.

 The addresses of the cells of the sub-memories are elaborated by an address counter 3 which is conventionally constituted by three sub-counters with 4 bits in series 35, 32 and 33. These counters are initialized, at each forward edge of the downstream signal. synchronization, by a clock signal at the line frequency which is transmitted by the time base 2 on the wire 34. Their counting is stopped by a signal delivered by a NAND gate 35 in response to the detected address 432 on the 9-wire output bus 36 of the counter and corresponding to the end of a line. The counter 3 advances at a frequency equal to half the sampling frequency under the control of the clock signal transmitted on the wire 15.

At this frequency half, the address of two sub-memory cells 11R and 22R or 11B and 12B on the bus 36 is recorded in the first nine stages of two buffer registers 41 and 42 of a memory selection circuit 4. The tenth register stage 41, 42 receives the most significant bit on a wire 43 which is representative of the address of one of the two sub-memories 11R and B12R 12 and
B and which selects them in the memory 11, 12. This is delivered by the complementary output Q of a flip-flop 44 whose input J receives a signal on a wire 45 coming out of the time base 2 and whose clock input is connected to the output of the NAND gate 35.The signal on the wire 45 is composed of two crenels at the half-line frequency, allowing the synchronization of the two chrominance signals of the SECAM system and consequently, the flip-flop 44 delivers the bit corresponding to one of these chrominance signals and the addressing of the two sub-memories or 1 1R and 12R, or and and 12. The transmission of the 10-bit addresses on the buses 13 and 14 by the buffer registers 41 and 42 is alternately paced by the clock signals complementary to the frequency FE / 2 on the wires 15 and 16.

However, as already said, this addressing will only operate to supply a sample word on the output bus 18 of the storage circuit i when the memory pair 11 - 12 considered is authorized to be read by the authorization signal. of reading transmitted on the wire 17.

 Timebase 1 will not be detailed because it uses conventional built-in logic. This receives the line synchronization signal SY which can be conventionally extracted from the incident composite video signal on which the generated signals will be inserted.

The synchronization signal slaves the sampling frequency F of a quartz clock. The logical unit of the time base makes it possible to elaborate all the aforesaid clock signals transmitted on the wires 15, 16, 17 to 17, 34 and 45 as well as others necessary for the function.
1 Part of the generator components. Of these, a third frequency inversion control signal FL is delivered on a wire 50 and is applied to an adder or subtracter circuit of the digit one and to a digital-to-analog converter 6, and a delayed signal to the sampling frequency FE is delivered on a wire 60 and also applied to the converter 6.

 The circuit 5 adds or subtracts 1 - according to the selected reference level, as will be seen in the following - to the 8-bit sample word transmitted on the bus 18 which connects in parallel the output buses of the memories 111 - 121 to 11M-12M. The 8-wire output bus 51 of the circuit 5 is connected to the bus c (input of the converter 6 through a logic adaptation interface to the TTL and ECL standards 7, according to this preferred embodiment A ue input 6t of the converter 6 a voltage is applied to adjust the amplitude of the analog signal from the converter. The output 62 of the converter 6 finally transmits the analog reference signal through a low pass filter 8 having a linear transfer function up to 6 MHz which corresponds to the frequency band of the video signal and delivers the desired reference analog signal under an impedance of 75 ohms.

 The signal delayed on the wire 60 synchronizes the conversion operation with the sample to be converted, following the delay of its processing in the circuit 5.

The phase inversion control signal is generally required in the SECAM system to improve the interference structure between the chrominance signals. Each period of this signal is divided into three slots each having a duration of 64 vs. one line every three lines a phase change of 1800, with the addition of 1800 from one frame to another. Thus, during each period of 192 ps of the signal on the wire 50 and for an odd image frame, the first slot is low and the last two slots are high, which defines the phase shift sequence 0 - t80 -t80; for an even image frame, the first slot is at the high level and the last two are at the low level, which corresponds to a phase shift sequence t 80 -0 Oc
These phase inversions are accomplished in the digital to analog converter 6 with respect to a reference level whose analog value is, in practice, zero amplitude. Each sampling word comprises N = 8 bits and, therefore, the signal is quantized at 28 = 256 quantization levels 0 to 255. Since a SECAM reference signal represents a quasi-symmetric waveform, a quantized reference level should be chosen which allows the use of the maximum of Quantization scale. This helps to optimize the quantization signal-to-noise ratio.

 One of the two median optimal reference levels 2 -t = 127 and 2 = 128 is to be selected so that 127 levels are on each side of the reference level. If the reference level 127 is chosen, the samples O to 126 and 128 to 254 are assigned to the negative and positive amplitudes and the upper level 255 is dropped. If the reference level 128 is chosen, the samples 1 to 127 and 129 to 255 are assigned to the negative and positive amplitudes and the lower level O is dropped.

 In both cases, in the absence of the circuit 5, the signal or phase inversion of the signal in the converter 6 introduces an error of a quantization step in the analog signal 8 the output 62: when the reference level is 127, samples 0 to 126 and 128 to 254 become, after inversion, samples 255 to 129 and 127 di when the reference level is 128, samples i to 127 and 129 to 255 become after inversion samples 254 to 128 and 126 to 0.

 The present invention therefore provides for inserting the circuit 5 before the digital-to-analog conversion, in order to add or subtract 1 to the samples to be inverted coming out of the memories and, consequently, to restore the symmetry in the outgoing analog signal with respect to the reference level. If the reference level 127 is chosen, the circuit 5 adds 1 to all the samples transmitted when the signal on the wire 50 is high. The stored samples 0 to 126 and 128 to 254 become, after addition of 1, 1 to 127 and 129 to 255, then, when inverting in the converter 6 by replacing each bit with the bit at the other logic state, they become the samples 254 to 128 and 126 to 0, which retains the symmetry with respect to the level 127. If the reference level 128 is chosen, the circuit 5 subtracts i to all the samples when the signal on the wire 50 is at The stored samples 1 to 127 and 129 to 255 become, after subtraction of 1, 0 to 126 and 128 to 254; then, during the inversion in the converter 6, they become the samples 255 to 129 and 127 to 1, which maintains the symmetry with respect to the level 128.

 Finally, it will be noted that the generator may contain one or more pairs of sample memories 111 - 121 to 11M - 12M which are in the form of plug-in boxes and / or may be switched by known means in order to select one or more signals. reference chrominance b transmit.

The table below indicates, according to a preferred embodiment, the main components included in the blocks t and 3 to 6 of the figure:
designation manufacturer memory 11, 12 ç 3628 INTEL
or 93 451 Fairchild counter 31, 32, 33 74 LS 163 Signetics register 41, 42 2 x 74 LS 174 Texas Instruments 4 bit adder 2 x 74 LS 253 Texas Instruments
with retainer 5 converter N / A 6 TDC 1016 J TRW LS I Products

Claims (8)

R e ve n d i c t i o n s  1 - Digital generator comprising means (t) for storing the digital samples of a periodic signal, logical addressing means (2, 3, 4) for reading the samples at the sampling frequency (FE) and means (6) for analogically converting the read digital samples, characterized in that the periodic signal is a signal to be included in a predetermined interval (IT) of one or more lines of the SECAM color television system, consisting of first and second second chrominance signals (R, B) each including alternately every other line, in that the memory means (1) comprise first memory storage means (11R, 12R) of the first chrominance signal (R) and second means (11B> 12B) for storing the samples of the second chrominance signal (B) and that the addressing logic means (2, 3, 4) comprises means (4) for selectively addressing a each of the first and second memory means (11R, 12R 118> t 2B) and means (2, 17) for permitting the reading of the samples during the predetermined interval (IT) of said one or more lines.  2 - digital generator according to claim 1, characterized in that each of the first and second storage means is constituted by first (11R; 118) and second (12R; 128) sub-memories of the same capacity which respectively store the samples odd and even ranks of the first, resp. second chrominance sigal (R, B), the addresses of the sub-memory cells being equal to the ranks of the adjacent sample pairs in a line period (TL), and in that the logical addressing means (2, 3, 4) comprise counting means (3) for delivering during each line duration (TL) the addresses of the cells of the sub-memories at the frequency half of the sampling frequency, means (41, 42, 36) for storing the delivered sub-memory cell address during two sampling periods, means (44) for providing each of the addresses of the first (11R, 12R) and second memory means (11B, 12B) during a line period two of the means (41, 42, 43) for storing the delivered address of the first, resp. second storage means for every other line period, and means (2, 15, 16) for reading the sub-memory cell memory address and the stored address of the first, resp. second storage means for transmitting it during two successive sampling periods respectively to the first (11R, 11B) and second (12R, 12B) sub-memories of the first, resp. second storage means.  3 - Digital generator according to claim 1 or 2, characterized in that the addressing logic means (2, 3, 4) comprise means (50) for controlling phase inversions in the conversion means according to a periodic sequence of three consecutive lines in which the phase-shifts are respec- tively 0 0, 1800 and 180 during an image frame and 180, 0, 0 during the next image frame.  4 - Digital generator according to claim 3, in which the digital samples are stored in the form of N-bit words, characterized in that the analog reference level, preferably of zero amplitude, of the corresponding conversion means (6) at the quantization level 2N-1-1, resp.2N-1 and in that it comprises, between the output (18) of the memerization means (1) and the input (51) of the conversion means (6). ), means (5) for adding, resp. Subtract the unit from each read digital sample that must be inverted during the phase shift periods of 1800 of these equations.  5 - digital generator according to one of claims t to 4, characterized in that the output of the conversion means (6) is connected to a low-pass filter (8), preferably with a bandwidth of the order of 6 MHz.  Digital generator according to one of claims 1 to 5, characterized in that it comprises a plurality of memory means (111-121 to 11M-12M) which respectively store the samples of different SECAM coded signals, such as the bar test signal, the frame identification signal, a test signal or a frequency channel modulated signal.  7 - digital generator according to claim 6, characterized in that the storage means (11 - 12) are each in the form of a plug-in housing.  8 - digital generator according to one of claims i to 7, characterized in that the sampling frequency is an integer multiple of the line frequency, such as 864 or 1008.