FR2497386A1 - PROGRAMMABLE DEAD MEMORY AND MEMORY CELL FOR USE IN SUCH A MEMORY - Google Patents

Abstract

SEMICONDUCTOR MEMORY CELL INTENDED FOR A PROGRAMMABLE DEAD MEMORY AND CONTAINING A POLYCRYSTALLINE SILICON 14 LAYER CONSTITUTED OF LATERALLY SEPARATED SURFACE REGIONS, WHICH SHOW DIFFERENT DOPING CONCENTRATIONS IN TEXTS OF 34, BODY OF DIES IN 34, BODY-DIFFERENT AND IN 34, BOTH MONODES PROGRAMMABLE 34 AND INSULATING DIODE 36. DUE TO DIFFERENT DOPING CONCENTRATIONS, THE DIODES SHOW DIFFERENT BREAKDOWN VOLTAGES IN REVERSE DIRECTION. THE PROGRAMMABLE DIODE AT THE LOWER BREAKDOWN VOLTAGE IN REVERSE DIRECTION. THE HIGH BREAKDOWN VOLTAGE IN REVERSE DIRECTION OF THE ISOLATING DIODE CAUSES THE BLOCKING OF THE CROSSING OF THE PARASITE CURRENT IN RELATION TO THE PROGRAMMING CURRENT.

Description

Programmable read only memory and memory cell to be used

in such a memory.

Background of the invention.

  The invention relates to a program read only memory.

  mable and neottmment an improved memory cell, intended for an electrically programmable read-only memory and comprising a semiconductor substrate of which a surface is covered with an insulating layer on which is

  deposited a layer of polycrystalline silicon, in the-

  what is the memory cell formed.

  One type of memory cell for an electrically programmable read-only memory is described in English patent application N 2,005,078 A, filed on April 11, 1979. This application recommends a memory cell comprising a layer of polycrystalline silicon which is formed on a insulating layer provided on a surface

  of a semiconductor substrate, the poly- silicon layer

  lens comprising three lateral semiconductor regions

  actually separated, which form two diodes mounted at the head-

  spade and having two separate pn junctions. One of these diodes serves as a programmable diode having a destructible junction, while the other diode is produced so that its junction remains intact, which diode serves

insulating diode.

  For cell programming, we apply

  at the ends of the two diodes connected in series a voltage

  sion of a polarity such that the current flows through the programmable diode in the opposite direction and the insulating diode in the direct direction. The voltage must be of sufficient value to

  destroy the junction of the program diode by short circuit

  mable. To reduce the program voltage and current

  mation at levels that can be safely transferred to other locations in the memory array, the destructible junction has a throttle

to reduce its surface.

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  However, the current levels required

  short-circuiting the junction of the program diode

  mable are considerable, and it is appropriate to further reduce the programming voltage and current. In addition, it is advisable to reduce the parasitic currents crossing already programmed cells of the matrix, cells located in the paths bypassing the cells which must qncore be programmed. The parasitic leakage currents require a programming voltage which is higher than the usual programming voltage and which could destroy the junction of an insulating diode in

a cell already programmed.

Summary of the invention.

  A programmed semiconductor memory cell

  mable according to the invention is remarkable in that

  the polycrystalline silicon layer comprises a plurality of

  lity of laterally separated regions constituting two diodes mounted head to tail and having different breakdown voltages in opposite directions. In a specific embodiment, the substrate consists of monocrystalline silicon, while the insulating layer consists of

silicon oxide.

  The polycrystalline silicon layer can be

  provided with a plurality of lateral surface regions-

  separated, which have doping concentrations

  different and constitute two diodes mounted at the head-

  spade. Following the different doping concentrations,

  the two diodes have different breakdown voltages

  annuities in reverse. The diode which has the lower breakdown voltage in the opposite direction becomes the programmable diode and the diode having the upper breakdown voltage in the opposite direction becomes the insulating diode. The high reverse breakdown voltage presented by the insulating diode has the effect of blocking the bushing.

  of the stray current with respect to the programming current.

  The description which will follow with regard to the

  sin appended, given by way of nonlimiting example, per-

  will better understand how the invention is made.

  Figure 1 shows in top view and on a greatly enlarged scale part of a read-only memory

  programmable with multiple memory cells

  forms to an embodiment of the invention.

  Figure 2 is a cross section along

line 2-2 of figure 1.

  Figures 3 to 8 are cross-sections illustrating different stages of manufacturing a cell

  memory according to another embodiment of the

vention.

  Figures 9 to 14 are cross-sections

  sales illustrating different stages of making a

  memory cell according to yet another embodiment

tion of the invention.

  Figures 15 to 20 are cross-sections

  sales illustrating different stages of making a

  memory cell according to a third embodiment

tion of the invention.

  Figure 1 shows a top view and on a greatly enlarged scale part of a matrix of memory cells according to the invention, and Figure 2 shows this part in cross section. A substrate of monocrystalline semiconductor material, such as

  silicon, has been designed to support the matrix of this

  memory cells. The silicon substrate 10 itself may include other components, not shown, which can be used in combination with the matrix of

  memory cells. A thermally and electric layer

  The insulating layer 12 is produced on a surface of the substrate 10. The insulating layer 12 can be a layer

  silicon oxide obtained by thermal growth.

  A thin layer 14 of polycrystalline silicon

  is formed on the insulating layer 12. The silicon layer

  polycrystalline cium 14 is relatively thin compared to

  to the insulating layer 12 as well as to the substrate 10.

  In a specific case, the polycrystalline silicon layer

  flax 14 has a thickness of the order of 4000 R, while the insulating layer has a thickness which is at least three p

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  times greater. FIG. 2 shows two memory cells which can be isolated from other groups of cells by insulating oxide regions 15, which are formed by localized oxidation in the polycrystalline silicon layer 14. The polycrystalline silicon layer 14, as it was originally formed, can be lightly doped and present the first type of conductivity, for example the P type. A central part of the layer 14 has a lightly doped region 16 of the second type of conductivity N. Three strongly doped regions 20, 18, 20 of first type of conductivity P + complete the double cell structure. One of these heavily doped regions, region 18, of the first type of conductivity, is formed in the lightly doped region 16 of the second type of conductivity N. while the other two regions

  heavily doped 20 of conductivity type PA are distant

  generally generated on either side of the central region 16 of second type of conductivity N, while being separated from this region by parts weakly

  doped 22 of the polycrystalline silicon layer 14.

  24 metallic conductors of a first

  level contact the regions? 20 through openings

  tures 25 formed in the first insulating layer 26, which is produced on the upper face of the layer

  polycrystalline silicon l ;. Similarly, a con-

  metallic conductor 28 of the same level contacts the P + 18 region through an opening 29. A metallic conductor of a second level contacts the metallic conductor 28, which is in contact with the P + 18 region. The contact between the conductors 30 and 28 is established through an opening 31 made in a second insulating layer 32, which also serves to isolate the conductors 24 with respect to the conductor 30. Several conductors 30 have been shown in FIG. 1 as conductors of

  column; the metallic conductors 24 have been shown

  tees like line conductors.

  According to a particular embodiment,

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  the heavily doped regions P + 18 and 20 have a doping concentration of 1.1020 boron atoms / cm3. The lightly doped region of type N 16 may have a doping concentration of 1.10 9 phosphorus atoms / cm The lightly doped region of type P may have a concentration

  doping centering of 1.10 boron atoms / cm3.

  The neighboring regions 16 and 18 constitute a semiconductive junction PN 34, while the regions

  neighbors 16 and 22 constitute a semiconductor junction

  PN 36. The P + 20 regions constitute electrical contacts of low ohmic value with the conductors

  metallic 24, preferably made of aluminum.

  The P + region 18 forms an electrical contact of low ohmic value with the metallic conductor 28 which, too, is made of aluminum. However, as opposed to

  P + 20 regions, the I + 18 region also serves as a positive side

  tif, or anode, of a semiconductor diode whose negative side, or cathode, is formed by the N + 16 region which,

  with the p + 18 region, constitutes the semiconductor junction

34.

  Referring to Figure 2, view from left to

  right half of the double cell structure

  successively carries a line conductor provided with a metallic contact 24, conductor which constitutes a contact of low ohmic value with the contact region P + 20, a region 22 of type P which is in contact with the contact region P + 20 and constitutes one side of an insulating diode, an N-type region 16 which forms a first semiconductor junction 36 with the P-type region 22 and constitutes the other side of the insulating diode as well as one of the sides of a programmable or destructible diode,

  a P + 18 region which forms a second semicon- junction

  ducting 34 with region 16 of type N and constitutes

  the other side of the destructible diode, a metal contact

  line 28 which forms a contact of low ohmic value with the region P 18, and a column conductor 30 which

  is in contact with the metallic contact 28. The structure

  ture pnp formed by regions 22, 16, 18 comprises

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  two diodes mounted head to tail.

  The right half of the double cell structure is the image of the left half and has a

  second pair of diodes mounted head to tail.

  An important feature of the invention is that the three regions 22, 16 and 18 which constitute the

  diodes, have different doping concentrations.

  The junction 36 between the lightly doped region 22 of the P type and the N type region 16 with low doping concentration has a breakdown voltage VB in the opposite direction which is higher than that of the junction 34 located between the

  weakly doped region 16 of type N and the strong region

  doped p + 18. The breakdown voltage V in the reverse direction

  B pour of a semiconductor junction is proportional to the resistivity of the high resistivity side of the junction. The breakdown voltage VB of the first junction 36 is proportional to the resistivity of the lightly doped region 22 of type P and of high resistivity, while the breakdown voltage VB of the second junction 34 is proportional to the resistivity of the lightly doped region 16 of type N ,, which is less strongly doped than the region Pi 18 of low resistivity. Among the two regions 16 and 22, which determine the respective breakdown voltages of these junctions, the lightly doped region 16 of N type has a lower resistivity than that of the lightly doped region 22 of

  type P, and this is why junction 34 has a voltage

  breakdown voltage in opposite direction lower than that of junction 36. The junction 34 having the breakdown voltage

  VB lower in opposite direction serves as destructive junction

  tible when the conductors 24 and 30 are shunted by a voltage source having a negative polarity by

  relative to the column conductor 30 and a positive polarity

  tive with respect to the line conductor 24. Following the low breakdown voltage in the opposite direction to the second junction 34, the breakdown of this junction can

  occur upon application of a programming voltage

  relatively low tion at the ends of the two diodes connected in series. However, as a result of the tension of

  relatively high breakdown in the opposite direction to the first

  first junction 36, this junction is able to withstand the same voltage which is applied to it in the opposite direction, so that there is blockage of the current in a possible parasitic path. Consequently, there is a reduction in stray currents, which makes it possible to

  reduce the current level and the programming voltage

mation to apply.

  Although the destruction mechanism of the second semiconductor junction 34 located between the two regions 16 and 18 of the polycrystalline silicon layer 14, is not yet entirely clear, it is assumed that it

  begins with an avalanche effect snap of the rush

  under the effect of a large current flow from

  Minor load headers crossing the junction in the opposite direction, breakdown which is accompanied by heating of the junction. Heat released by the junction is transmitted to the interface between the metal conductor 28 and the semiconductor surface of the P region 18, which then causes the heating of the aluminum in this interface region and the migration of the thermally activated aluminum atoms to semiconductor junction 34, where they produce a permanent short-circuit of the

junction.

  According to the aforementioned theory, for the metallic conductor 28, a metal having a low melting point, such as aluminum, is preferably used to ensure a large supply of metallic atoms at a reasonably low temperature. In addition, the insulating layer 12, on which the polycrystalline silicon layer 14 is located, must have a sufficient thickness and be made up

  with a thermally insulating material of suf- ficient quality

  so that the polycrystalline silicon layer 14

  is thermally insulated by it against the dissipation

  heat through the semiconductor substrate 10.

  Otherwise, the thermal effect required at the location of the destructible junction 34 would be affected. Furthermore, the

  polycrystalline nature of the layer 14 made of poly-

  crystal, which has gaps in the crystal lattice, helps drive the metal atoms to the

  junction 34. By the lateral extension of the metal conductor

  lique 28, extension which is in contact with the P + 18 region, we obtain the overlap of the destructible junction

  34. This overlap ensures that most of the

  of the aluminum conductor sjUrface 28 is exposed to the heat of the junction 34 for the transmission of heat by the insulating layer 26. For a transmission

  heat transfer from junction 34 to metal conductor

  overlap 28, the insulating layer 26 must be as thin as possible. By the way, the layer

  26 must have suitable electrical insulation properties

stick.

  It should be noted that the semiconductor junctions

  trices 34 and 36 are both side junctions

  rales, to be distinguished from planar junctions. A junction

  lateral is a junction in which the current cross-

  the junction essentially flows in a parallel direction

  lele to the main face of the semiconductor instead of circulating essentially in a direction perpendicular to the main face, as in a planar junction. The semiconductor regions 20, 22, 16 and 18 are all separated laterally, while none of these regions

  cuts another region vertically or perpendicularly

  cular. The junction areas are then reduced to a minimum to facilitate the destruction of the diode or the programmable junction. An even more characteristic

  important is that the reproducibility of cells present

  both the same reverse breakdown voltage

  for the insulating diode and the same rating voltage

  lower quage in the opposite direction for the programmable diode, can be obtained more easily in a lateral structure than in a planar structure, where the doping gradients near the junction are more pronounced and less controllable as a result of the more

  large and more irregular junctions.

  Figures 3 to 8 illustrate different steps

  of manufacturing another embodiment of the invention

  tion. A silicon substrate 10 is provided with a layer of silicon oxide 12 having a thickness sufficient to obtain good thermal and electrical properties. The silicon oxide layer 12 can be obtained so

known by thermal growth.

  On - the oxide layer 12, a layer 38 of intrinsic polycrystalline silicon is deposited and, thereafter, it is exposed to an N-type dopant, such as phosphorus,

  so as to give it a relative doping concentration

  very weak. During the diffusion of the phosphorus atoms, a thin layer of thermal oxide 40 is grown on

  the surface of the polycrystalline silicon layer 38.

  After the thin oxide layer has grown, low P-type doping, for example with boron, can be carried out in the polycrystalline silicon layer 38 by implantation through the thin oxide layer 40. The lightly doped P-type layer serves to stabilize the polycrystalline silicon layer and practically does not reduce the previous doping concentration, which is always low and of N type. On the thin oxide layer 40, a layer 42 of silicon nitride, after which we realize

  another thin layer of silicon oxide 44 on the

  che of silicon nitride 42. By selective masking and elimination steps, the layer is locally oxidized

  of polycrystalline silicon 38, in selected regions

  born, to define the limits of the memory cell.

  In Figure 3, these regions are represented as

insulating oxide regions 46.

  FIG. 4 illustrates the selective elimination of parts of the thin oxide layer 44 and of the silicon nitride layer 42, elimination which aims to define a large central opening 47 as well as two other remote openings 48, smaller , each located on one side of the central opening 47. On the two small remote openings 48, a mask of photosensitive lacquer is formed, represented by dotted lines to indicate its subsequent elimination, the central opening 47 being left at discovered for

  elimination of the oxide layer 40. Next, we ef-

  performs a strong doping with boron or another dopant of the type

  P through the central opening 47, for example by im-

  planting or spreading, and the dopants are penetrated

  over the entire - depth of the poly- silicon layer

  lens 38 to create a region P 52. During the endo-

  diffusion, an oxide layer a is again grown on the P + region 52 to replace the thermal oxide layer 40 which, beforehand, has been eliminated in

this region.

  In the step of Figure 5, we cover the!

  looks like another layer 56 of photosensitive lacquer, except the openings 48 and a small central opening 54

  located in the largest central opening 46.

  mines the thermal oxide layer 40a in a small central region, while also eliminating the layer

  of original thermal oxide 40 in the remote openings

  gnées48. After the elimination of the photosensitive lacquer, strong doping is carried out with an N type dopant, such as phosphorus, through the openings 48 and 54. The N type dopant is made to penetrate the entire depth of the layer. of polycrystalline silicon 38 to produce an N + 58 region in the P + 52 region as well as two I 60 regions, separated from the P 52 region and located on either side thereof. During endodiffusion, a new thin thermal oxide layer is grown

  62 on the N + 58 and 60 regions discovered.

  In the step of FIG. 6, the layer of silicon nitride 42 is eliminated after the elimination of

the thin oxide layer 44.

  In the step of figure 7, we form a mask

  64 photosensitive lacquer to cover the oxide above

  above the central region Y + 58, after which the oxide layer 62 is eliminated in the regions N + 60. After the elimination of the mask 64 of photosensitive lacquer, an alloy of platinum and nickel can be deposited on the two regions Separate N + 60, for the formation of an alloy layer 66 of low ohmic value. Such an alloy can consist of 40% nickel and 60% platinum. The alloy constitutes an alloy of platinum,

  nickel and silicon which, in English, is commonly designated

  ment under the name of "silicin platinum" and is represented in FIG. 7 by the portion of dotted line which extends as far as the N + 60 region. The presence of the oxide layers 40a and 62 prevents the alloy from being able to deposit in other regions. After the formation of

  the layer of alloy 66, a layer of oxy-

  of silicon 68 on the alloy layer 66.

  In the step of figure 8, after the deposit

  a layer of silicon nitride 70 over the entire structure

  another layer of silicon oxide 72 is formed.

  The lower oxide layer 68 is necessary for the ob-

  attention to good adhesion of the silicon nitride layer 70. The nitride layer 70 and the

  upper silicon oxide layer 72 in a confi-

  guration such that they form a fairly large opening

  ture 74 above the central region N 58, the opening

  ture 74 ending about halfway between the ex-

  lateral hoppers of the central region N 58 and the

P + 52 region.

  The thin oxide layer 62, represented by

  felt in FIG. 7, on the surface of the N + region 58 so that the original opening 54 in the layer

  thicker oxide 40a extends to region N "58.

  Then, the structure is covered with a first layer 76 of aluminum to establish contact between the central region N + 58 through the opening 54 made in the oxide layer 40a. The first aluminum layer 56 is isolated from the N + regions 60 by the oxide layers 68, 72 and the nitride layer 70. After having been brought into the required configuration, the aluminum layer 76 may constitute one of the cross bar system conductors. The first aluminum layer 76 is covered with an insulating glass layer 78. In the glass insulating layer 78, openings are made above the N 60 regions covered with silicide, these openings also passing through the oxide layers. 68, 72 and the

  nitride layer 70. These openings are not shown

  felt in figure 8, but can be represented as

  located in the extension of the openings 48,

  above the regions N 60, while being offset relative to the plane of the drawing. On the insulating layer 78, we

  deposits a second layer 80 of aluminum which is parallel

  related to the N + 60 regions covered with silicide, and which extends through the openings in the insulating glass layer 78, the openings in the oxide layers 68, 72 and the opening in the nitride layer 70 and contacts the layer of alloy 66. Finally, the second layer of aluminum 80 is covered with an upper insulating layer of

glass 82.

  In the structure completed according to FIG. 8, the central region N + 58 forms a semiconductor junction 84 with the region P + 52, while the region 38 of type N forms a semiconductor junction 86 with the region P + 52. The junction 84 has a tension breakdown VB in opposite direction lower than that of junction 86. Thus, junction 84 acts as a destructible junction, while junction 86 acts as an insulating junction. The

  N + 60 regions are used to establish low-value contact

  their resistance between the N type region 38 and the alloy region 66. In a specific embodiment, the N region can have a doping concentration of 10 atoms / cm3, the P + region 52 a doping concentration

  of 10 9 atoms / cM3 and the N-type region a concentra-

doping tion of 101 atoms / cm3.

  It should be noted that an opening was practiced

  oversized ture 74 in the silicon nitride layer 70 and the oxide layer 72, the opening 74

  about halfway between the lateral ends

  of the two junctions 84 and 86. This is done for ex-

  lay the largest possible area of the aluminum layer 76 at the destructible junction 84, which is only separated from it by the oxide layer 40a. Thus, during the breakdown of the junction 84, the heat generated at the location of this junction can be more easily transmitted at the top through the oxide layer 40a, and be communicated to a larger area of the aluminum layer. 76. In turn, the heat of the aluminum layer can be more easily transmitted to the angular regions 87 of the aluminum layer 76, regions through which this aluminum layer contacts both the oxide layer 40a and the region. No. 58. The angular regions 87 of the aluminum layer 76 are closest

  from junction 84 and constitute the source for migra-

  tion of aluminum towards junction 84.

  This same opening 84 in the oxide layer a is used for the formation of the N + region 58 and for the realization of aluminum contact with the region

  N + 58. This technique is analogous to the "emitting-

  washed out emitter in bipolar transistor technology. In this way, it can be considered that the distance between the aluminum contact region 87 and the destructible junction 84 is self-aligned so

  that it can be adjusted within tighter tolerances.

  Thus, seen from left to right in FIG. 8, a first pair of diodes is formed between a single region N + 60 and the central region N 58, while a

  second pair of diodes is formed between the central region

  trale N 58 and the other region N 60. The two cells have in common the region N 58, while being situated on either side thereof, each cell comprising two diodes whose breakdown voltages in opposite directions

are different.

  Figures 9 to 14 show another embodiment of the invention. For simplicity, the same references have been used to indicate the elements which correspond to those of the embodiment already shown.

  presented in Figures 3 to 8. In addition, there is shown 2i497386 1 4 the different photosensitive masks without references. The

  description made with regard to these figures is less detailed

* cut, since it clearly emerges from the drawn figures

  and from the previous description how the different

  process steps are carried out.

  In the step of Figure 9, we form a re-

  lightly doped n-type central region 92 in a layer

  Originally intrinsic polycrystalline silicon.

  Then, a very low P-type doping is carried out in the entire layer 90 so that the P-type doping of the mass of the layer 90 is lower than the doping

type N from the central region.

  In the step of figure 10, we form two re-

  separate regions 94 lightly doped Pt type which

  in part on the P-type region 90 and in part on the N-type region 92. In the step of FIG. 11, two heavily doped N + 96 regions are formed in the P-type region 90,

  which are separate from each of the P + 94 regions.

  In the step of FIG. 12, a contact opening is made in the insulating layer 40, above the central region 92 of type N. In the step of FIG. 13, regions are formed

  of contact of alloy 66 on the surface of regions N + 96.

  Figure 14 shows the completed structure.

  Each N + region 96 forms with the neighboring region 90 of type p a junction 98 which has a high breakdown voltage in the opposite direction and which, therefore, serves as an insulating junction. Each region P + 94 forms a junction 100 with its neighboring region 92 of type N, which has a low breakdown voltage in the opposite direction and which, therefore, serves as a destructible junction. In a mode of

  specific realization, the typeN region 92 has a

  doping concentration of 1.1018 atoms / cm3, the P-type region 90 a doping concentration of 1.1017 atoms / cm3 and the P 94 region a doping concentration of 1.10 9 atoms / cm3, while the NF 96 region has a concentration of doping of 1.10 atoms / cm3. The N-type region 92 is common to the two cells located on either side

  of the latter, each cell comprising two diodes present

  both different breakdown voltages in reverse.

  Through the oversized opening 74, a large area of the first layer of aluminum 76 is

  exposed to the destructible junction 100. The lateral distance

  line between the edge of the oversized opening 74 and the point where the junction 100 intersects the upper face of the polycrystalline silicon layer 90, is equal to or greater than the lateral distance between the junction 100 and the edge of the opening 54 made in layer

oxide 40.

  According to FIG. 10, a single step defines both the openings for the P + 94 region and the opening for the contact of aluminum with the 92 type N region. This makes it possible to easily adjust the distance between the

  aluminum contact and junction 100.

  Figures 15 to 20 show yet another embodiment of the invention. As in the case of the previous embodiment according to FIGS. 9 to 14,

  we will only give a brief description.

  In the step of figure 15, we proceed to a

  low N-type doping of a layer 102 of poly-

intrinsic lens.

  In the step of FIG. 16, openings are made in the layer of silicon nitride 42 and the layer of silicon oxide 44 to define the regions of

  polycrystalline silicon with different doping concentrations

  férentes. In the N-type layer 102, three heavily doped P-type regions are formed, namely a region

  central P + 104 and two external P regions 106.

  In the step of FIG. 17, two heavily doped regions 108 of type N conductivity are formed in the layer 102 of type N. Each of the N + regions 108 is separated from its neighboring region P + 106, but partly overlaps the region central p 104 so as to form junctions 110 near the surface of the polycrystalline silicon layer 102. The junctions 110 have a low reverse breakdown voltage. Each of the Pi regions 106 forms with the N type region 102 a junction 112 which has a high breakdown voltage in the opposite direction. In the step of FIG. 18, openings are made in the oxide layer 40 to define the

  contact regions for regions 104, 106.

  In the step of figure 19, we form re-

  10 alloy 66 regions in the surface of the external regions

laughter 106.

  The completed structure is shown in the figure

  gure 20. Here, we again use a "emitting-

  washed "for the formation of the aluminum layer contact

  minium 76 with the central P + region 104. Furthermore, during a single step, represented in FIG. 16, we define

  all regions with different doping concentrations.

  The only region Pt 104 is common to two cells of me-

  programmable moire, each cell comprising two diodes provided with junctions 110 and 112 and having different breakdown voltages in the opposite direction. Junction 110

  having the reverse breakdown voltage in reverse direction

  se is the destructible junction, while junction 112

  having the upper breakdown voltage in the opposite direction

verse is the insulating junction.

  The oversized opening 74 is located directly

  above the destructible junction 110, a junction on which only slightly overlaps or overlaps

  not at all the part of the aluminum layer 76 which re-

  poses on the oxide layer 40. In this embodiment

  tion, it is necessary to minimize the overlap

  aluminum to prevent it from entering

in regions N 108.

  In a specific embodiment, the N-type layer 102 has a doping concentration of 1018 atoms / cm3, the Ni 108 region a doping concentration of 10 atoms / cm3, while the P + 10o4 regions,

  106 have a doping concentration of b19 atoms / cm3.

Claims (15)

  1. Semiconductor memory cell comprising   a semiconductor substrate (10) whose surface is re-   covered with an insulating layer (12) on which is   placed a layer (14) of polycrystalline silicon, in which the memory cell is formed, characterized in that the layer of polycrystalline silicon comprises   a plurality of regions (16, 18, 20, 22) laterally se-   trimmed constituting two diodes (34, 36) mounted at the head-   beche and having different breakdown voltages reverse.   2. Memory cell according to claim 1, ca-   characterized in that each of the two diodes is formed   by two regions of opposite conductivity types, the dio-   of (36) having the upper breakdown voltage in direction   inverse presenting a single region (22) whose concen-   doping tration is significantly lower than that of   each of the two regions (16, 18) constituting the other di- of.   3. Memory cell according to claim 2, ca-   characterized in that the two regions of the first di-   of form an insulating semiconductor junction, while the two regions of the last diode form a   programmable semiconductor junction, the semi-junction   insulating conductor with a larger area   re to that of the programmable semiconductor junction.   4. Memory cell according to claim 1, ca-   characterized in that said layer of polycrystallized silicon   tallin comprises a first part (22) of pre-layer   mier type of conductivity, a first region (16) of   cond type of conductivity included in said layer part and forming an insulating semiconductor junction (36) therewith, a second region (18) of first type of conductivity included in said region (16) and forming a programmable semiconductor junction (34 ) with the latter, a first metallic conductor (28, 30) contacting said second region at a point located at   a shorter distance from said semiconductor junction   programmable trice (34) of said insulating junction as well as a second metallic conductor (24) connected to said first layer part and insulated from said first metallic conductor.   5. Memory cell according to claim 4, characterized in that it further comprises a thin electrically insulating layer (26) situated on said layer of polycrystalline silicon, this insulating layer   separating the programmable junction (34) from said first connector   metallic conductor (28) and having an opening (29) through which said first metallic conductor   contacts said second region (18), said first contact   metallic conductor comprising a part which is in con-   direct tact with said thin layer electrically iso-   lante, which overlaps on said programmable junction.   6. Semiconductor memory cell according to claim 1, characterized in that said polycrystalline silicon layer comprises a layer part (38) of first conductivity type, a first region (52) of second conductivity type encompassed in said part of layer and forming a semiconductor junction   insulating (86) with this part, as well as a second   gion (58) of first type of conductivity included in   said first region and forming with it a ring-   programmable semiconductor tion (84) which is separate   of said insulating semiconductor junction, said pre-   region with a higher doping concentration   re to that of said layer part, and said second region having a doping concentration greater than that of said first region.   7. Memory cell according to claim 6,   characterized in that said layer of poly-   lens is topped with a thin electric layer-   insulating material (40a), in which an or-   green (54) revealing only part of the   said second region which is separated from said programmable semiconductor junction, a first conductor ((76)   contacting said second region through said open-   ture and having a part which extends directly   on said thin electrically insulating layer and   left on said programmable semiconductor junction.   8. Memory cell according to claim 7, characterized in that said second region (58) and the part of said first metallic conductor which is in contact with it, are made in self-alignment through said opening.   9. Memory cell according to claim 1,   characterized in that said layer of poly-   lens has four regions (90, 92, 94, 96) la-   successively separated as follows: a first region (92) of first conductivity type, a second region (94) of second conductivity type forming a programmable semiconductor junction (100) with said first region, a third region (90) of second type of conductivity having a doping concentration lower than that of said second region,   and a fourth region (96) of first type of conduc-   activity forming an insulating semiconductor junction (98) with said third region, said fourth, second, first and third regions having, in   this order, decreasing doping concentrations.   10. Memory cell according to claim 9,   characterized in that said layer of poly-   lens is topped with a thin electric layer-   insulating material (40), in which an or-   groove (54) exposing only part of said first region (92) which is separated from said   programmable semiconductor junction, a first   metallic conductor (76) contacting said first reducer   gion through said opening and having a part   which extends directly over said thin electric layer   only insulating and overlaps on said semi-junction programmable driver (100).   11. Memory cell according to claim 10,   characterized in that said third region (90) constitutes   titues an original part of said polycrystalline silicon layer, while said first, second and   fourth regions are formed by the introduction of do-   pants in said polycrystalline silicon layer.   12. Semiconductor memory according to claim   1, characterized in that said layer (102) of silicon   polycrystalline cium is of first type of conductivity and in that it is finite of a first region (104) of second type of conductivity as well as of a second region (108) of first type of conductivity exhibiting a concentration doping greater than that of said polycrystalline silicon layer, said first and   said second region forming a semiconductor junction   programmable trice (110) on a surface of said polycrystalline silicon layer, which is further provided with a third region (106) of second conductivity type which is separated from said second region and forms a   insulating semiconductor junction (112) with said layer   polycrystalline silicon, said third region   having a doping concentration higher than that   the of said polycrystalline silicon layer.   13. Memory cell according to claim 12,   characterized in that said layer of poly-   lens is topped with a thin electric layer-   insulating material (40), in which an or-   green revealing only part of said first region (104) which is separated from said junction   programmable semiconductor (110), a first conduc-   metal tor (76) contacting said first region through said opening and having a portion which   is located directly on said thin electrical layer-   insulating and extends at most to a small distance   tance beyond said semiconductor junction pro-   grammable. 14. Memory cell according to claim 13,   characterized in that said first region and the par-   tie of said first metallic conductor which is in con-   tact with it, are self-aligning to through said opening.   15. Thesis including a cell system of   memory according to one or more of the preceding claims   teeth, formed on a common semiconductor substrate (10),   the cells being arranged in rows and columns.